The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/ar934xreg.h

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
    3  *
    4  * Copyright (c) 2013 Adrian Chadd <adrian@FreeBSD.org>
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  * 1. Redistributions of source code must retain the above copyright
   11  *    notice, this list of conditions and the following disclaimer.
   12  * 2. Redistributions in binary form must reproduce the above copyright
   13  *    notice, this list of conditions and the following disclaimer in the
   14  *    documentation and/or other materials provided with the distribution.
   15  *
   16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   26  * SUCH DAMAGE.
   27  *
   28  * $FreeBSD: stable/12/sys/mips/atheros/ar934xreg.h 326259 2017-11-27 15:07:26Z pfg $
   29  */
   30 
   31 #ifndef __AR934X_REG_H__
   32 #define __AR934X_REG_H__
   33 
   34 #define AR934X_GMAC_BASE        (AR71XX_APB_BASE + 0x00070000)
   35 #define AR934X_GMAC_SIZE        0x14
   36 #define AR934X_WMAC_BASE        (AR71XX_APB_BASE + 0x00100000)
   37 #define AR934X_WMAC_SIZE        0x20000
   38 #define AR934X_EHCI_BASE        0x1b000000
   39 #define AR934X_EHCI_SIZE        0x200
   40 #define AR934X_SRIF_BASE        (AR71XX_APB_BASE + 0x00116000)
   41 #define AR934X_SRIF_SIZE        0x1000
   42 
   43 /* AR934x GMAC configuration */
   44 #define AR934X_GMAC_REG_ETH_CFG         (AR934X_GMAC_BASE + 0x00)
   45 
   46 #define AR934X_ETH_CFG_RGMII_GMAC0              (1 << 0)
   47 #define AR934X_ETH_CFG_MII_GMAC0                (1 << 1)
   48 #define AR934X_ETH_CFG_GMII_GMAC0               (1 << 2)
   49 #define AR934X_ETH_CFG_MII_GMAC0_MASTER         (1 << 3)
   50 #define AR934X_ETH_CFG_MII_GMAC0_SLAVE          (1 << 4)
   51 #define AR934X_ETH_CFG_MII_GMAC0_ERR_EN         (1 << 5)
   52 #define AR934X_ETH_CFG_SW_ONLY_MODE             (1 << 6)
   53 #define AR934X_ETH_CFG_SW_PHY_SWAP              (1 << 7)
   54 #define AR934X_ETH_CFG_SW_APB_ACCESS            (1 << 9)
   55 #define AR934X_ETH_CFG_RMII_GMAC0               (1 << 10)
   56 #define AR933X_ETH_CFG_MII_CNTL_SPEED           (1 << 11)
   57 #define AR934X_ETH_CFG_RMII_GMAC0_MASTER        (1 << 12)
   58 #define AR934X_ETH_CFG_SW_ACC_MSB_FIRST         (1 << 13)
   59 
   60 #define AR934X_DDR_REG_FLUSH_GE0        (AR71XX_APB_BASE + 0x9c)
   61 #define AR934X_DDR_REG_FLUSH_GE1        (AR71XX_APB_BASE + 0xa0)
   62 #define AR934X_DDR_REG_FLUSH_USB        (AR71XX_APB_BASE + 0xa4)
   63 #define AR934X_DDR_REG_FLUSH_PCIE       (AR71XX_APB_BASE + 0xa8)
   64 #define AR934X_DDR_REG_FLUSH_WMAC       (AR71XX_APB_BASE + 0xac)
   65 
   66 #define AR934X_PLL_CPU_CONFIG_REG       (AR71XX_PLL_CPU_BASE + 0x00)
   67 #define AR934X_PLL_DDR_CONFIG_REG       (AR71XX_PLL_CPU_BASE + 0x04)
   68 #define AR934X_PLL_CPU_DDR_CLK_CTRL_REG (AR71XX_PLL_CPU_BASE + 0x08)
   69 #define AR934X_PLL_SWITCH_CLOCK_CONTROL_REG     (AR71XX_PLL_CPU_BASE + 0x24)
   70 #define         AR934X_PLL_SWITCH_CLOCK_CONTROL_MDIO_CLK_SEL   (1 << 6)
   71 #define AR934X_PLL_ETH_XMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x2c)
   72 
   73 #define AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT       0
   74 #define AR934X_PLL_CPU_CONFIG_NFRAC_MASK        0x3f
   75 #define AR934X_PLL_CPU_CONFIG_NINT_SHIFT        6
   76 #define AR934X_PLL_CPU_CONFIG_NINT_MASK         0x3f
   77 #define AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT      12
   78 #define AR934X_PLL_CPU_CONFIG_REFDIV_MASK       0x1f
   79 #define AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT      19
   80 #define AR934X_PLL_CPU_CONFIG_OUTDIV_MASK       0x3
   81 
   82 #define AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT       0
   83 #define AR934X_PLL_DDR_CONFIG_NFRAC_MASK        0x3ff
   84 #define AR934X_PLL_DDR_CONFIG_NINT_SHIFT        10
   85 #define AR934X_PLL_DDR_CONFIG_NINT_MASK         0x3f
   86 #define AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT      16
   87 #define AR934X_PLL_DDR_CONFIG_REFDIV_MASK       0x1f
   88 #define AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT      23
   89 #define AR934X_PLL_DDR_CONFIG_OUTDIV_MASK       0x7
   90 
   91 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS      (1 << 2)
   92 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS      (1 << 3)
   93 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS      (1 << 4)
   94 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT  5
   95 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK   0x1f
   96 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT  10
   97 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK   0x1f
   98 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT  15
   99 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK   0x1f
  100 #define AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL  (1 << 20)
  101 #define AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL  (1 << 21)
  102 #define AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL  (1 << 24)
  103 
  104 #define AR934X_RESET_REG_RESET_MODULE           (AR71XX_RST_BLOCK_BASE + 0x1c)
  105 #define AR934X_RESET_REG_BOOTSTRAP              (AR71XX_RST_BLOCK_BASE + 0xb0)
  106 #define AR934X_RESET_REG_PCIE_WMAC_INT_STATUS   (AR71XX_RST_BLOCK_BASE + 0xac)
  107 
  108 #define AR934X_RESET_HOST               (1U << 31)
  109 #define AR934X_RESET_SLIC               (1 << 30)
  110 #define AR934X_RESET_HDMA               (1 << 29)
  111 #define AR934X_RESET_EXTERNAL           (1 << 28)
  112 #define AR934X_RESET_RTC                (1 << 27)
  113 #define AR934X_RESET_PCIE_EP_INT        (1 << 26)
  114 #define AR934X_RESET_CHKSUM_ACC         (1 << 25)
  115 #define AR934X_RESET_FULL_CHIP          (1 << 24)
  116 #define AR934X_RESET_GE1_MDIO           (1 << 23)
  117 #define AR934X_RESET_GE0_MDIO           (1 << 22)
  118 #define AR934X_RESET_CPU_NMI            (1 << 21)
  119 #define AR934X_RESET_CPU_COLD           (1 << 20)
  120 #define AR934X_RESET_HOST_RESET_INT     (1 << 19)
  121 #define AR934X_RESET_PCIE_EP            (1 << 18)
  122 #define AR934X_RESET_UART1              (1 << 17)
  123 #define AR934X_RESET_DDR                (1 << 16)
  124 #define AR934X_RESET_USB_PHY_PLL_PWD_EXT        (1 << 15)
  125 #define AR934X_RESET_NANDF              (1 << 14)
  126 #define AR934X_RESET_GE1_MAC            (1 << 13)
  127 #define AR934X_RESET_ETH_SWITCH_ANALOG  (1 << 12)
  128 #define AR934X_RESET_USB_PHY_ANALOG     (1 << 11)
  129 #define AR934X_RESET_HOST_DMA_INT       (1 << 10)
  130 #define AR934X_RESET_GE0_MAC            (1 << 9)
  131 #define AR934X_RESET_ETH_SWITCH         (1 << 8)
  132 #define AR934X_RESET_PCIE_PHY           (1 << 7)
  133 #define AR934X_RESET_PCIE               (1 << 6)
  134 #define AR934X_RESET_USB_HOST           (1 << 5)
  135 #define AR934X_RESET_USB_PHY            (1 << 4)
  136 #define AR934X_RESET_USBSUS_OVERRIDE    (1 << 3)
  137 #define AR934X_RESET_LUT                (1 << 2)
  138 #define AR934X_RESET_MBOX               (1 << 1)
  139 #define AR934X_RESET_I2S                (1 << 0)
  140 
  141 #define AR934X_BOOTSTRAP_SW_OPTION8     (1 << 23)
  142 #define AR934X_BOOTSTRAP_SW_OPTION7     (1 << 22)
  143 #define AR934X_BOOTSTRAP_SW_OPTION6     (1 << 21)
  144 #define AR934X_BOOTSTRAP_SW_OPTION5     (1 << 20)
  145 #define AR934X_BOOTSTRAP_SW_OPTION4     (1 << 19)
  146 #define AR934X_BOOTSTRAP_SW_OPTION3     (1 << 18)
  147 #define AR934X_BOOTSTRAP_SW_OPTION2     (1 << 17)
  148 #define AR934X_BOOTSTRAP_SW_OPTION1     (1 << 16)
  149 #define AR934X_BOOTSTRAP_USB_MODE_DEVICE        (1 << 7)
  150 #define AR934X_BOOTSTRAP_PCIE_RC        (1 << 6)
  151 #define AR934X_BOOTSTRAP_EJTAG_MODE     (1 << 5)
  152 #define AR934X_BOOTSTRAP_REF_CLK_40     (1 << 4)
  153 #define AR934X_BOOTSTRAP_BOOT_FROM_SPI  (1 << 2)
  154 #define AR934X_BOOTSTRAP_SDRAM_DISABLED (1 << 1)
  155 #define AR934X_BOOTSTRAP_DDR1           (1 << 0)
  156 
  157 #define AR934X_PCIE_WMAC_INT_WMAC_MISC  (1 << 0)
  158 #define AR934X_PCIE_WMAC_INT_WMAC_TX    (1 << 1)
  159 #define AR934X_PCIE_WMAC_INT_WMAC_RXLP  (1 << 2)
  160 #define AR934X_PCIE_WMAC_INT_WMAC_RXHP  (1 << 3)
  161 #define AR934X_PCIE_WMAC_INT_PCIE_RC    (1 << 4)
  162 #define AR934X_PCIE_WMAC_INT_PCIE_RC0   (1 << 5)
  163 #define AR934X_PCIE_WMAC_INT_PCIE_RC1   (1 << 6)
  164 #define AR934X_PCIE_WMAC_INT_PCIE_RC2   (1 << 7)
  165 #define AR934X_PCIE_WMAC_INT_PCIE_RC3   (1 << 8)
  166 #define AR934X_PCIE_WMAC_INT_WMAC_ALL \
  167         (AR934X_PCIE_WMAC_INT_WMAC_MISC | AR934X_PCIE_WMAC_INT_WMAC_TX | \
  168          AR934X_PCIE_WMAC_INT_WMAC_RXLP | AR934X_PCIE_WMAC_INT_WMAC_RXHP)
  169 
  170 #define AR934X_PCIE_WMAC_INT_PCIE_ALL \
  171         (AR934X_PCIE_WMAC_INT_PCIE_RC | AR934X_PCIE_WMAC_INT_PCIE_RC0 | \
  172          AR934X_PCIE_WMAC_INT_PCIE_RC1 | AR934X_PCIE_WMAC_INT_PCIE_RC2 | \
  173          AR934X_PCIE_WMAC_INT_PCIE_RC3)
  174 
  175 #define REV_ID_MAJOR_AR9341             0x0120
  176 #define REV_ID_MAJOR_AR9342             0x1120
  177 #define REV_ID_MAJOR_AR9344             0x2120
  178 
  179 #define AR934X_REV_ID_REVISION_MASK     0xf
  180 
  181 /*
  182  * GPIO block
  183  */
  184 #define AR934X_GPIO_REG_OUT_FUNC0       0x2c
  185 #define AR934X_GPIO_REG_OUT_FUNC1       0x30
  186 #define AR934X_GPIO_REG_OUT_FUNC2       0x34
  187 #define AR934X_GPIO_REG_OUT_FUNC3       0x38
  188 #define AR934X_GPIO_REG_OUT_FUNC4       0x3c
  189 #define AR934X_GPIO_REG_OUT_FUNC5       0x40
  190 #define AR934X_GPIO_REG_FUNC            0x6c
  191 #define AR934X_GPIO_COUNT               23
  192 
  193 /* GPIO functions */
  194 #define AR934X_GPIO_FUNC_CLK_OBS7_EN           (1 << 9)
  195 #define AR934X_GPIO_FUNC_CLK_OBS6_EN           (1 << 8)
  196 #define AR934X_GPIO_FUNC_CLK_OBS5_EN           (1 << 7)
  197 #define AR934X_GPIO_FUNC_CLK_OBS4_EN           (1 << 6)
  198 #define AR934X_GPIO_FUNC_CLK_OBS3_EN           (1 << 5)
  199 #define AR934X_GPIO_FUNC_CLK_OBS2_EN           (1 << 4)
  200 #define AR934X_GPIO_FUNC_CLK_OBS1_EN           (1 << 3)
  201 #define AR934X_GPIO_FUNC_CLK_OBS0_EN           (1 << 2)
  202 #define AR934X_GPIO_FUNC_JTAG_DISABLE          (1 << 1)
  203 
  204 /* GPIO MUX output function: AR934X_GPIO_REG_OUT_FUNCx */
  205 #define AR934X_GPIO_OUT_GPIO            0       /* I'm a GPIO */
  206 #define AR934X_GPIO_OUT_SPI_CS1         7       /* I'm SPI CS1 */
  207 #define AR934X_GPIO_OUT_LED_LINK0       41      /* I'm switch phy link0 */
  208 #define AR934X_GPIO_OUT_LED_LINK1       42
  209 #define AR934X_GPIO_OUT_LED_LINK2       43
  210 #define AR934X_GPIO_OUT_LED_LINK3       44
  211 #define AR934X_GPIO_OUT_LED_LINK4       45
  212 #define AR934X_GPIO_OUT_EXT_LNA0        46      /* I'm WMAC EXT LNA chain 0 */
  213 #define AR934X_GPIO_OUT_EXT_LNA1        47      /* I'm WMAC EXT LNA chain 1 */
  214 
  215 /*
  216  * SRIF block
  217  */
  218 #define AR934X_SRIF_CPU_DPLL1_REG       (AR934X_SRIF_BASE + 0x1c0)
  219 #define AR934X_SRIF_CPU_DPLL2_REG       (AR934X_SRIF_BASE + 0x1c4)
  220 #define AR934X_SRIF_CPU_DPLL3_REG       (AR934X_SRIF_BASE + 0x1c8)
  221 
  222 #define AR934X_SRIF_DDR_DPLL1_REG       (AR934X_SRIF_BASE + 0x240)
  223 #define AR934X_SRIF_DDR_DPLL2_REG       (AR934X_SRIF_BASE + 0x244)
  224 #define AR934X_SRIF_DDR_DPLL3_REG       (AR934X_SRIF_BASE + 0x248)
  225 
  226 #define AR934X_SRIF_DPLL1_REFDIV_SHIFT  27
  227 #define AR934X_SRIF_DPLL1_REFDIV_MASK   0x1f
  228 #define AR934X_SRIF_DPLL1_NINT_SHIFT    18
  229 #define AR934X_SRIF_DPLL1_NINT_MASK     0x1ff
  230 #define AR934X_SRIF_DPLL1_NFRAC_MASK    0x0003ffff
  231 
  232 #define AR934X_SRIF_DPLL2_LOCAL_PLL     (1 << 30)
  233 #define AR934X_SRIF_DPLL2_OUTDIV_SHIFT  13
  234 #define AR934X_SRIF_DPLL2_OUTDIV_MASK   0x7
  235 
  236 /* XXX verify! */
  237 #define AR934X_PLL_VAL_1000             0x16000000
  238 #define AR934X_PLL_VAL_100              0x00000101
  239 #define AR934X_PLL_VAL_10               0x00001616
  240 
  241 #endif  /* __AR934X_REG_H__ */

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