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sys/mips/atheros/if_arge.c
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1 /*- 2 * Copyright (c) 2009, Oleksandr Tymoshenko 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/cdefs.h> 29 __FBSDID("$FreeBSD$"); 30 31 /* 32 * AR71XX gigabit ethernet driver 33 */ 34 #ifdef HAVE_KERNEL_OPTION_HEADERS 35 #include "opt_device_polling.h" 36 #endif 37 38 #include "opt_arge.h" 39 40 #include <sys/param.h> 41 #include <sys/endian.h> 42 #include <sys/systm.h> 43 #include <sys/sockio.h> 44 #include <sys/mbuf.h> 45 #include <sys/malloc.h> 46 #include <sys/kernel.h> 47 #include <sys/module.h> 48 #include <sys/socket.h> 49 #include <sys/taskqueue.h> 50 #include <sys/sysctl.h> 51 52 #include <net/if.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 59 #include <net/bpf.h> 60 61 #include <machine/bus.h> 62 #include <machine/cache.h> 63 #include <machine/resource.h> 64 #include <vm/vm_param.h> 65 #include <vm/vm.h> 66 #include <vm/pmap.h> 67 #include <machine/pmap.h> 68 #include <sys/bus.h> 69 #include <sys/rman.h> 70 71 #include <dev/mii/mii.h> 72 #include <dev/mii/miivar.h> 73 74 #include <dev/pci/pcireg.h> 75 #include <dev/pci/pcivar.h> 76 77 #include "opt_arge.h" 78 79 #if defined(ARGE_MDIO) 80 #include <dev/etherswitch/mdio.h> 81 #include <dev/etherswitch/miiproxy.h> 82 #include "mdio_if.h" 83 #endif 84 85 86 MODULE_DEPEND(arge, ether, 1, 1, 1); 87 MODULE_DEPEND(arge, miibus, 1, 1, 1); 88 MODULE_VERSION(arge, 1); 89 90 #include "miibus_if.h" 91 92 #include <mips/atheros/ar71xxreg.h> 93 #include <mips/atheros/if_argevar.h> 94 #include <mips/atheros/ar71xx_setup.h> 95 #include <mips/atheros/ar71xx_cpudef.h> 96 97 typedef enum { 98 ARGE_DBG_MII = 0x00000001, 99 ARGE_DBG_INTR = 0x00000002, 100 ARGE_DBG_TX = 0x00000004, 101 ARGE_DBG_RX = 0x00000008, 102 ARGE_DBG_ERR = 0x00000010, 103 ARGE_DBG_RESET = 0x00000020, 104 ARGE_DBG_PLL = 0x00000040, 105 } arge_debug_flags; 106 107 static const char * arge_miicfg_str[] = { 108 "NONE", 109 "GMII", 110 "MII", 111 "RGMII", 112 "RMII" 113 }; 114 115 #ifdef ARGE_DEBUG 116 #define ARGEDEBUG(_sc, _m, ...) \ 117 do { \ 118 if ((_m) & (_sc)->arge_debug) \ 119 device_printf((_sc)->arge_dev, __VA_ARGS__); \ 120 } while (0) 121 #else 122 #define ARGEDEBUG(_sc, _m, ...) 123 #endif 124 125 static int arge_attach(device_t); 126 static int arge_detach(device_t); 127 static void arge_flush_ddr(struct arge_softc *); 128 static int arge_ifmedia_upd(struct ifnet *); 129 static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 130 static int arge_ioctl(struct ifnet *, u_long, caddr_t); 131 static void arge_init(void *); 132 static void arge_init_locked(struct arge_softc *); 133 static void arge_link_task(void *, int); 134 static void arge_update_link_locked(struct arge_softc *sc); 135 static void arge_set_pll(struct arge_softc *, int, int); 136 static int arge_miibus_readreg(device_t, int, int); 137 static void arge_miibus_statchg(device_t); 138 static int arge_miibus_writereg(device_t, int, int, int); 139 static int arge_probe(device_t); 140 static void arge_reset_dma(struct arge_softc *); 141 static int arge_resume(device_t); 142 static int arge_rx_ring_init(struct arge_softc *); 143 static void arge_rx_ring_free(struct arge_softc *sc); 144 static int arge_tx_ring_init(struct arge_softc *); 145 static void arge_tx_ring_free(struct arge_softc *); 146 #ifdef DEVICE_POLLING 147 static int arge_poll(struct ifnet *, enum poll_cmd, int); 148 #endif 149 static int arge_shutdown(device_t); 150 static void arge_start(struct ifnet *); 151 static void arge_start_locked(struct ifnet *); 152 static void arge_stop(struct arge_softc *); 153 static int arge_suspend(device_t); 154 155 static int arge_rx_locked(struct arge_softc *); 156 static void arge_tx_locked(struct arge_softc *); 157 static void arge_intr(void *); 158 static int arge_intr_filter(void *); 159 static void arge_tick(void *); 160 161 static void arge_hinted_child(device_t bus, const char *dname, int dunit); 162 163 /* 164 * ifmedia callbacks for multiPHY MAC 165 */ 166 void arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *); 167 int arge_multiphy_mediachange(struct ifnet *); 168 169 static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int); 170 static int arge_dma_alloc(struct arge_softc *); 171 static void arge_dma_free(struct arge_softc *); 172 static int arge_newbuf(struct arge_softc *, int); 173 static __inline void arge_fixup_rx(struct mbuf *); 174 175 static device_method_t arge_methods[] = { 176 /* Device interface */ 177 DEVMETHOD(device_probe, arge_probe), 178 DEVMETHOD(device_attach, arge_attach), 179 DEVMETHOD(device_detach, arge_detach), 180 DEVMETHOD(device_suspend, arge_suspend), 181 DEVMETHOD(device_resume, arge_resume), 182 DEVMETHOD(device_shutdown, arge_shutdown), 183 184 /* MII interface */ 185 DEVMETHOD(miibus_readreg, arge_miibus_readreg), 186 DEVMETHOD(miibus_writereg, arge_miibus_writereg), 187 DEVMETHOD(miibus_statchg, arge_miibus_statchg), 188 189 /* bus interface */ 190 DEVMETHOD(bus_add_child, device_add_child_ordered), 191 DEVMETHOD(bus_hinted_child, arge_hinted_child), 192 193 DEVMETHOD_END 194 }; 195 196 static driver_t arge_driver = { 197 "arge", 198 arge_methods, 199 sizeof(struct arge_softc) 200 }; 201 202 static devclass_t arge_devclass; 203 204 DRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0); 205 DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0); 206 207 #if defined(ARGE_MDIO) 208 static int argemdio_probe(device_t); 209 static int argemdio_attach(device_t); 210 static int argemdio_detach(device_t); 211 212 /* 213 * Declare an additional, separate driver for accessing the MDIO bus. 214 */ 215 static device_method_t argemdio_methods[] = { 216 /* Device interface */ 217 DEVMETHOD(device_probe, argemdio_probe), 218 DEVMETHOD(device_attach, argemdio_attach), 219 DEVMETHOD(device_detach, argemdio_detach), 220 221 /* bus interface */ 222 DEVMETHOD(bus_add_child, device_add_child_ordered), 223 224 /* MDIO access */ 225 DEVMETHOD(mdio_readreg, arge_miibus_readreg), 226 DEVMETHOD(mdio_writereg, arge_miibus_writereg), 227 }; 228 229 DEFINE_CLASS_0(argemdio, argemdio_driver, argemdio_methods, 230 sizeof(struct arge_softc)); 231 static devclass_t argemdio_devclass; 232 233 DRIVER_MODULE(miiproxy, arge, miiproxy_driver, miiproxy_devclass, 0, 0); 234 DRIVER_MODULE(argemdio, nexus, argemdio_driver, argemdio_devclass, 0, 0); 235 DRIVER_MODULE(mdio, argemdio, mdio_driver, mdio_devclass, 0, 0); 236 #endif 237 238 /* 239 * RedBoot passes MAC address to entry point as environment 240 * variable. platfrom_start parses it and stores in this variable 241 */ 242 extern uint32_t ar711_base_mac[ETHER_ADDR_LEN]; 243 244 static struct mtx miibus_mtx; 245 246 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF); 247 248 /* 249 * Flushes all 250 */ 251 static void 252 arge_flush_ddr(struct arge_softc *sc) 253 { 254 255 ar71xx_device_flush_ddr_ge(sc->arge_mac_unit); 256 } 257 258 static int 259 arge_probe(device_t dev) 260 { 261 262 device_set_desc(dev, "Atheros AR71xx built-in ethernet interface"); 263 return (BUS_PROBE_NOWILDCARD); 264 } 265 266 static void 267 arge_attach_sysctl(device_t dev) 268 { 269 struct arge_softc *sc = device_get_softc(dev); 270 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev); 271 struct sysctl_oid *tree = device_get_sysctl_tree(dev); 272 273 #ifdef ARGE_DEBUG 274 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 275 "debug", CTLFLAG_RW, &sc->arge_debug, 0, 276 "arge interface debugging flags"); 277 #endif 278 279 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 280 "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0, 281 "number of TX aligned packets"); 282 283 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, 284 "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned, 285 0, "number of TX unaligned packets"); 286 287 #ifdef ARGE_DEBUG 288 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_prod", 289 CTLFLAG_RW, &sc->arge_cdata.arge_tx_prod, 0, ""); 290 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cons", 291 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cons, 0, ""); 292 SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO, "tx_cnt", 293 CTLFLAG_RW, &sc->arge_cdata.arge_tx_cnt, 0, ""); 294 #endif 295 } 296 297 static void 298 arge_reset_mac(struct arge_softc *sc) 299 { 300 uint32_t reg; 301 302 /* Step 1. Soft-reset MAC */ 303 ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET); 304 DELAY(20); 305 306 /* Step 2. Punt the MAC core from the central reset register */ 307 ar71xx_device_stop(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : 308 RST_RESET_GE1_MAC); 309 DELAY(100); 310 ar71xx_device_start(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : 311 RST_RESET_GE1_MAC); 312 313 /* Step 3. Reconfigure MAC block */ 314 ARGE_WRITE(sc, AR71XX_MAC_CFG1, 315 MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE | 316 MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE); 317 318 reg = ARGE_READ(sc, AR71XX_MAC_CFG2); 319 reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ; 320 ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg); 321 322 ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536); 323 } 324 325 static void 326 arge_reset_miibus(struct arge_softc *sc) 327 { 328 329 /* Reset MII bus */ 330 ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET); 331 DELAY(100); 332 ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_28); 333 DELAY(100); 334 } 335 336 static void 337 arge_fetch_pll_config(struct arge_softc *sc) 338 { 339 long int val; 340 341 if (resource_long_value(device_get_name(sc->arge_dev), 342 device_get_unit(sc->arge_dev), 343 "pll_10", &val) == 0) { 344 sc->arge_pllcfg.pll_10 = val; 345 device_printf(sc->arge_dev, "%s: pll_10 = 0x%x\n", 346 __func__, (int) val); 347 } 348 if (resource_long_value(device_get_name(sc->arge_dev), 349 device_get_unit(sc->arge_dev), 350 "pll_100", &val) == 0) { 351 sc->arge_pllcfg.pll_100 = val; 352 device_printf(sc->arge_dev, "%s: pll_100 = 0x%x\n", 353 __func__, (int) val); 354 } 355 if (resource_long_value(device_get_name(sc->arge_dev), 356 device_get_unit(sc->arge_dev), 357 "pll_1000", &val) == 0) { 358 sc->arge_pllcfg.pll_1000 = val; 359 device_printf(sc->arge_dev, "%s: pll_1000 = 0x%x\n", 360 __func__, (int) val); 361 } 362 } 363 364 static int 365 arge_attach(device_t dev) 366 { 367 struct ifnet *ifp; 368 struct arge_softc *sc; 369 int error = 0, rid; 370 uint32_t rnd; 371 int is_base_mac_empty, i; 372 uint32_t hint; 373 long eeprom_mac_addr = 0; 374 int miicfg = 0; 375 int readascii = 0; 376 377 sc = device_get_softc(dev); 378 sc->arge_dev = dev; 379 sc->arge_mac_unit = device_get_unit(dev); 380 381 /* 382 * Some units (eg the TP-Link WR-1043ND) do not have a convenient 383 * EEPROM location to read the ethernet MAC address from. 384 * OpenWRT simply snaffles it from a fixed location. 385 * 386 * Since multiple units seem to use this feature, include 387 * a method of setting the MAC address based on an flash location 388 * in CPU address space. 389 * 390 * Some vendors have decided to store the mac address as a literal 391 * string of 18 characters in xx:xx:xx:xx:xx:xx format instead of 392 * an array of numbers. Expose a hint to turn on this conversion 393 * feature via strtol() 394 */ 395 if (resource_long_value(device_get_name(dev), device_get_unit(dev), 396 "eeprommac", &eeprom_mac_addr) == 0) { 397 int i; 398 const char *mac = 399 (const char *) MIPS_PHYS_TO_KSEG1(eeprom_mac_addr); 400 device_printf(dev, "Overriding MAC from EEPROM\n"); 401 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 402 "readascii", &readascii) == 0) { 403 device_printf(dev, "Vendor stores MAC in ASCII format\n"); 404 for (i = 0; i < 6; i++) { 405 ar711_base_mac[i] = strtol(&(mac[i*3]), NULL, 16); 406 } 407 } else { 408 for (i = 0; i < 6; i++) { 409 ar711_base_mac[i] = mac[i]; 410 } 411 } 412 } 413 414 KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)), 415 ("if_arge: Only MAC0 and MAC1 supported")); 416 417 /* 418 * Fetch the PLL configuration. 419 */ 420 arge_fetch_pll_config(sc); 421 422 /* 423 * Get the MII configuration, if applicable. 424 */ 425 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 426 "miimode", &miicfg) == 0) { 427 /* XXX bounds check? */ 428 device_printf(dev, "%s: overriding MII mode to '%s'\n", 429 __func__, arge_miicfg_str[miicfg]); 430 sc->arge_miicfg = miicfg; 431 } 432 433 /* 434 * Get which PHY of 5 available we should use for this unit 435 */ 436 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 437 "phymask", &sc->arge_phymask) != 0) { 438 /* 439 * Use port 4 (WAN) for GE0. For any other port use 440 * its PHY the same as its unit number 441 */ 442 if (sc->arge_mac_unit == 0) 443 sc->arge_phymask = (1 << 4); 444 else 445 /* Use all phys up to 4 */ 446 sc->arge_phymask = (1 << 4) - 1; 447 448 device_printf(dev, "No PHY specified, using mask %d\n", sc->arge_phymask); 449 } 450 451 /* 452 * Get default media & duplex mode, by default its Base100T 453 * and full duplex 454 */ 455 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 456 "media", &hint) != 0) 457 hint = 0; 458 459 if (hint == 1000) 460 sc->arge_media_type = IFM_1000_T; 461 else 462 sc->arge_media_type = IFM_100_TX; 463 464 if (resource_int_value(device_get_name(dev), device_get_unit(dev), 465 "fduplex", &hint) != 0) 466 hint = 1; 467 468 if (hint) 469 sc->arge_duplex_mode = IFM_FDX; 470 else 471 sc->arge_duplex_mode = 0; 472 473 mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 474 MTX_DEF); 475 callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0); 476 TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc); 477 478 /* Map control/status registers. */ 479 sc->arge_rid = 0; 480 sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 481 &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE); 482 483 if (sc->arge_res == NULL) { 484 device_printf(dev, "couldn't map memory\n"); 485 error = ENXIO; 486 goto fail; 487 } 488 489 /* Allocate interrupts */ 490 rid = 0; 491 sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 492 RF_SHAREABLE | RF_ACTIVE); 493 494 if (sc->arge_irq == NULL) { 495 device_printf(dev, "couldn't map interrupt\n"); 496 error = ENXIO; 497 goto fail; 498 } 499 500 /* Allocate ifnet structure. */ 501 ifp = sc->arge_ifp = if_alloc(IFT_ETHER); 502 503 if (ifp == NULL) { 504 device_printf(dev, "couldn't allocate ifnet structure\n"); 505 error = ENOSPC; 506 goto fail; 507 } 508 509 ifp->if_softc = sc; 510 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 511 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 512 ifp->if_ioctl = arge_ioctl; 513 ifp->if_start = arge_start; 514 ifp->if_init = arge_init; 515 sc->arge_if_flags = ifp->if_flags; 516 517 /* XXX: add real size */ 518 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 519 ifp->if_snd.ifq_maxlen = ifqmaxlen; 520 IFQ_SET_READY(&ifp->if_snd); 521 522 ifp->if_capenable = ifp->if_capabilities; 523 #ifdef DEVICE_POLLING 524 ifp->if_capabilities |= IFCAP_POLLING; 525 #endif 526 527 is_base_mac_empty = 1; 528 for (i = 0; i < ETHER_ADDR_LEN; i++) { 529 sc->arge_eaddr[i] = ar711_base_mac[i] & 0xff; 530 if (sc->arge_eaddr[i] != 0) 531 is_base_mac_empty = 0; 532 } 533 534 if (is_base_mac_empty) { 535 /* 536 * No MAC address configured. Generate the random one. 537 */ 538 if (bootverbose) 539 device_printf(dev, 540 "Generating random ethernet address.\n"); 541 542 rnd = arc4random(); 543 sc->arge_eaddr[0] = 'b'; 544 sc->arge_eaddr[1] = 's'; 545 sc->arge_eaddr[2] = 'd'; 546 sc->arge_eaddr[3] = (rnd >> 24) & 0xff; 547 sc->arge_eaddr[4] = (rnd >> 16) & 0xff; 548 sc->arge_eaddr[5] = (rnd >> 8) & 0xff; 549 } 550 if (sc->arge_mac_unit != 0) 551 sc->arge_eaddr[5] += sc->arge_mac_unit; 552 553 if (arge_dma_alloc(sc) != 0) { 554 error = ENXIO; 555 goto fail; 556 } 557 558 /* 559 * Don't do this for the MDIO bus case - it's already done 560 * as part of the MDIO bus attachment. 561 */ 562 #if !defined(ARGE_MDIO) 563 /* Initialize the MAC block */ 564 arge_reset_mac(sc); 565 arge_reset_miibus(sc); 566 #endif 567 568 /* Configure MII mode, just for convienence */ 569 if (sc->arge_miicfg != 0) 570 ar71xx_device_set_mii_if(sc->arge_mac_unit, sc->arge_miicfg); 571 572 /* 573 * Set all Ethernet address registers to the same initial values 574 * set all four addresses to 66-88-aa-cc-dd-ee 575 */ 576 ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, (sc->arge_eaddr[2] << 24) 577 | (sc->arge_eaddr[3] << 16) | (sc->arge_eaddr[4] << 8) 578 | sc->arge_eaddr[5]); 579 ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (sc->arge_eaddr[0] << 8) 580 | sc->arge_eaddr[1]); 581 582 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0, 583 FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT); 584 585 switch (ar71xx_soc) { 586 case AR71XX_SOC_AR7240: 587 case AR71XX_SOC_AR7241: 588 case AR71XX_SOC_AR7242: 589 case AR71XX_SOC_AR9330: 590 case AR71XX_SOC_AR9331: 591 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0010ffff); 592 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x015500aa); 593 break; 594 default: 595 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000); 596 ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff); 597 } 598 599 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH, 600 FIFO_RX_FILTMATCH_DEFAULT); 601 602 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 603 FIFO_RX_FILTMASK_DEFAULT); 604 605 #if defined(ARGE_MDIO) 606 sc->arge_miiproxy = mii_attach_proxy(sc->arge_dev); 607 #endif 608 609 device_printf(sc->arge_dev, "finishing attachment, phymask %04x" 610 ", proxy %s \n", sc->arge_phymask, sc->arge_miiproxy == NULL ? 611 "null" : "set"); 612 for (i = 0; i < ARGE_NPHY; i++) { 613 if (((1 << i) & sc->arge_phymask) != 0) { 614 error = mii_attach(sc->arge_miiproxy != NULL ? 615 sc->arge_miiproxy : sc->arge_dev, 616 &sc->arge_miibus, sc->arge_ifp, 617 arge_ifmedia_upd, arge_ifmedia_sts, 618 BMSR_DEFCAPMASK, i, MII_OFFSET_ANY, 0); 619 if (error != 0) { 620 device_printf(sc->arge_dev, "unable to attach" 621 " PHY %d: %d\n", i, error); 622 goto fail; 623 } 624 } 625 } 626 if (sc->arge_miibus == NULL) { 627 /* no PHY, so use hard-coded values */ 628 ifmedia_init(&sc->arge_ifmedia, 0, 629 arge_multiphy_mediachange, 630 arge_multiphy_mediastatus); 631 ifmedia_add(&sc->arge_ifmedia, 632 IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode, 633 0, NULL); 634 ifmedia_set(&sc->arge_ifmedia, 635 IFM_ETHER | sc->arge_media_type | sc->arge_duplex_mode); 636 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode); 637 } 638 639 /* Call MI attach routine. */ 640 ether_ifattach(sc->arge_ifp, sc->arge_eaddr); 641 642 /* Hook interrupt last to avoid having to lock softc */ 643 error = bus_setup_intr(sc->arge_dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE, 644 arge_intr_filter, arge_intr, sc, &sc->arge_intrhand); 645 646 if (error) { 647 device_printf(sc->arge_dev, "couldn't set up irq\n"); 648 ether_ifdetach(sc->arge_ifp); 649 goto fail; 650 } 651 652 /* setup sysctl variables */ 653 arge_attach_sysctl(sc->arge_dev); 654 655 fail: 656 if (error) 657 arge_detach(dev); 658 659 return (error); 660 } 661 662 static int 663 arge_detach(device_t dev) 664 { 665 struct arge_softc *sc = device_get_softc(dev); 666 struct ifnet *ifp = sc->arge_ifp; 667 668 KASSERT(mtx_initialized(&sc->arge_mtx), 669 ("arge mutex not initialized")); 670 671 /* These should only be active if attach succeeded */ 672 if (device_is_attached(dev)) { 673 ARGE_LOCK(sc); 674 sc->arge_detach = 1; 675 #ifdef DEVICE_POLLING 676 if (ifp->if_capenable & IFCAP_POLLING) 677 ether_poll_deregister(ifp); 678 #endif 679 680 arge_stop(sc); 681 ARGE_UNLOCK(sc); 682 taskqueue_drain(taskqueue_swi, &sc->arge_link_task); 683 ether_ifdetach(ifp); 684 } 685 686 if (sc->arge_miibus) 687 device_delete_child(dev, sc->arge_miibus); 688 689 if (sc->arge_miiproxy) 690 device_delete_child(dev, sc->arge_miiproxy); 691 692 bus_generic_detach(dev); 693 694 if (sc->arge_intrhand) 695 bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand); 696 697 if (sc->arge_res) 698 bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid, 699 sc->arge_res); 700 701 if (ifp) 702 if_free(ifp); 703 704 arge_dma_free(sc); 705 706 mtx_destroy(&sc->arge_mtx); 707 708 return (0); 709 710 } 711 712 static int 713 arge_suspend(device_t dev) 714 { 715 716 panic("%s", __func__); 717 return 0; 718 } 719 720 static int 721 arge_resume(device_t dev) 722 { 723 724 panic("%s", __func__); 725 return 0; 726 } 727 728 static int 729 arge_shutdown(device_t dev) 730 { 731 struct arge_softc *sc; 732 733 sc = device_get_softc(dev); 734 735 ARGE_LOCK(sc); 736 arge_stop(sc); 737 ARGE_UNLOCK(sc); 738 739 return (0); 740 } 741 742 static void 743 arge_hinted_child(device_t bus, const char *dname, int dunit) 744 { 745 BUS_ADD_CHILD(bus, 0, dname, dunit); 746 device_printf(bus, "hinted child %s%d\n", dname, dunit); 747 } 748 749 static int 750 arge_miibus_readreg(device_t dev, int phy, int reg) 751 { 752 struct arge_softc * sc = device_get_softc(dev); 753 int i, result; 754 uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT) 755 | (reg & MAC_MII_REG_MASK); 756 757 mtx_lock(&miibus_mtx); 758 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); 759 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr); 760 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ); 761 762 i = ARGE_MII_TIMEOUT; 763 while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) & 764 MAC_MII_INDICATOR_BUSY) && (i--)) 765 DELAY(5); 766 767 if (i < 0) { 768 mtx_unlock(&miibus_mtx); 769 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__); 770 /* XXX: return ERRNO istead? */ 771 return (-1); 772 } 773 774 result = ARGE_MDIO_READ(sc, AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK; 775 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE); 776 mtx_unlock(&miibus_mtx); 777 778 ARGEDEBUG(sc, ARGE_DBG_MII, 779 "%s: phy=%d, reg=%02x, value[%08x]=%04x\n", 780 __func__, phy, reg, addr, result); 781 782 return (result); 783 } 784 785 static int 786 arge_miibus_writereg(device_t dev, int phy, int reg, int data) 787 { 788 struct arge_softc * sc = device_get_softc(dev); 789 int i; 790 uint32_t addr = 791 (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK); 792 793 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: phy=%d, reg=%02x, value=%04x\n", __func__, 794 phy, reg, data); 795 796 mtx_lock(&miibus_mtx); 797 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_ADDR, addr); 798 ARGE_MDIO_WRITE(sc, AR71XX_MAC_MII_CONTROL, data); 799 800 i = ARGE_MII_TIMEOUT; 801 while ((ARGE_MDIO_READ(sc, AR71XX_MAC_MII_INDICATOR) & 802 MAC_MII_INDICATOR_BUSY) && (i--)) 803 DELAY(5); 804 805 mtx_unlock(&miibus_mtx); 806 807 if (i < 0) { 808 ARGEDEBUG(sc, ARGE_DBG_MII, "%s timedout\n", __func__); 809 /* XXX: return ERRNO istead? */ 810 return (-1); 811 } 812 813 return (0); 814 } 815 816 static void 817 arge_miibus_statchg(device_t dev) 818 { 819 struct arge_softc *sc; 820 821 sc = device_get_softc(dev); 822 taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task); 823 } 824 825 static void 826 arge_link_task(void *arg, int pending) 827 { 828 struct arge_softc *sc; 829 sc = (struct arge_softc *)arg; 830 831 ARGE_LOCK(sc); 832 arge_update_link_locked(sc); 833 ARGE_UNLOCK(sc); 834 } 835 836 static void 837 arge_update_link_locked(struct arge_softc *sc) 838 { 839 struct mii_data *mii; 840 struct ifnet *ifp; 841 uint32_t media, duplex; 842 843 mii = device_get_softc(sc->arge_miibus); 844 ifp = sc->arge_ifp; 845 if (mii == NULL || ifp == NULL || 846 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 847 return; 848 } 849 850 if (mii->mii_media_status & IFM_ACTIVE) { 851 852 media = IFM_SUBTYPE(mii->mii_media_active); 853 if (media != IFM_NONE) { 854 sc->arge_link_status = 1; 855 duplex = mii->mii_media_active & IFM_GMASK; 856 ARGEDEBUG(sc, ARGE_DBG_MII, "%s: media=%d, duplex=%d\n", 857 __func__, 858 media, 859 duplex); 860 arge_set_pll(sc, media, duplex); 861 } 862 } else { 863 sc->arge_link_status = 0; 864 } 865 } 866 867 static void 868 arge_set_pll(struct arge_softc *sc, int media, int duplex) 869 { 870 uint32_t cfg, ifcontrol, rx_filtmask; 871 uint32_t fifo_tx, pll; 872 int if_speed; 873 874 ARGEDEBUG(sc, ARGE_DBG_PLL, "set_pll(%04x, %s)\n", media, 875 duplex == IFM_FDX ? "full" : "half"); 876 cfg = ARGE_READ(sc, AR71XX_MAC_CFG2); 877 cfg &= ~(MAC_CFG2_IFACE_MODE_1000 878 | MAC_CFG2_IFACE_MODE_10_100 879 | MAC_CFG2_FULL_DUPLEX); 880 881 if (duplex == IFM_FDX) 882 cfg |= MAC_CFG2_FULL_DUPLEX; 883 884 ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL); 885 ifcontrol &= ~MAC_IFCONTROL_SPEED; 886 rx_filtmask = 887 ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK); 888 rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE; 889 890 switch(media) { 891 case IFM_10_T: 892 cfg |= MAC_CFG2_IFACE_MODE_10_100; 893 if_speed = 10; 894 break; 895 case IFM_100_TX: 896 cfg |= MAC_CFG2_IFACE_MODE_10_100; 897 ifcontrol |= MAC_IFCONTROL_SPEED; 898 if_speed = 100; 899 break; 900 case IFM_1000_T: 901 case IFM_1000_SX: 902 cfg |= MAC_CFG2_IFACE_MODE_1000; 903 rx_filtmask |= FIFO_RX_MASK_BYTE_MODE; 904 if_speed = 1000; 905 break; 906 default: 907 if_speed = 100; 908 device_printf(sc->arge_dev, 909 "Unknown media %d\n", media); 910 } 911 912 ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: if_speed=%d\n", __func__, if_speed); 913 914 switch (ar71xx_soc) { 915 case AR71XX_SOC_AR7240: 916 case AR71XX_SOC_AR7241: 917 case AR71XX_SOC_AR7242: 918 case AR71XX_SOC_AR9330: 919 case AR71XX_SOC_AR9331: 920 fifo_tx = 0x01f00140; 921 break; 922 case AR71XX_SOC_AR9130: 923 case AR71XX_SOC_AR9132: 924 fifo_tx = 0x00780fff; 925 break; 926 default: 927 fifo_tx = 0x008001ff; 928 } 929 930 ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg); 931 ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol); 932 ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 933 rx_filtmask); 934 ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD, fifo_tx); 935 936 /* fetch PLL registers */ 937 pll = ar71xx_device_get_eth_pll(sc->arge_mac_unit, if_speed); 938 ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: pll=0x%x\n", __func__, pll); 939 940 /* Override if required by platform data */ 941 if (if_speed == 10 && sc->arge_pllcfg.pll_10 != 0) 942 pll = sc->arge_pllcfg.pll_10; 943 else if (if_speed == 100 && sc->arge_pllcfg.pll_100 != 0) 944 pll = sc->arge_pllcfg.pll_100; 945 else if (if_speed == 1000 && sc->arge_pllcfg.pll_1000 != 0) 946 pll = sc->arge_pllcfg.pll_1000; 947 ARGEDEBUG(sc, ARGE_DBG_PLL, "%s: final pll=0x%x\n", __func__, pll); 948 949 /* XXX ensure pll != 0 */ 950 ar71xx_device_set_pll_ge(sc->arge_mac_unit, if_speed, pll); 951 952 /* set MII registers */ 953 /* 954 * This was introduced to match what the Linux ag71xx ethernet 955 * driver does. For the AR71xx case, it does set the port 956 * MII speed. However, if this is done, non-gigabit speeds 957 * are not at all reliable when speaking via RGMII through 958 * 'bridge' PHY port that's pretending to be a local PHY. 959 * 960 * Until that gets root caused, and until an AR71xx + normal 961 * PHY board is tested, leave this disabled. 962 */ 963 #if 0 964 ar71xx_device_set_mii_speed(sc->arge_mac_unit, if_speed); 965 #endif 966 } 967 968 969 static void 970 arge_reset_dma(struct arge_softc *sc) 971 { 972 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0); 973 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0); 974 975 ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0); 976 ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0); 977 978 /* Clear all possible RX interrupts */ 979 while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD) 980 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD); 981 982 /* 983 * Clear all possible TX interrupts 984 */ 985 while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT) 986 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT); 987 988 /* 989 * Now Rx/Tx errors 990 */ 991 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, 992 DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW); 993 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, 994 DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN); 995 996 /* 997 * Force a DDR flush so any pending data is properly 998 * flushed to RAM before underlying buffers are freed. 999 */ 1000 arge_flush_ddr(sc); 1001 } 1002 1003 1004 1005 static void 1006 arge_init(void *xsc) 1007 { 1008 struct arge_softc *sc = xsc; 1009 1010 ARGE_LOCK(sc); 1011 arge_init_locked(sc); 1012 ARGE_UNLOCK(sc); 1013 } 1014 1015 static void 1016 arge_init_locked(struct arge_softc *sc) 1017 { 1018 struct ifnet *ifp = sc->arge_ifp; 1019 struct mii_data *mii; 1020 1021 ARGE_LOCK_ASSERT(sc); 1022 1023 if ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1024 return; 1025 1026 /* Init circular RX list. */ 1027 if (arge_rx_ring_init(sc) != 0) { 1028 device_printf(sc->arge_dev, 1029 "initialization failed: no memory for rx buffers\n"); 1030 arge_stop(sc); 1031 return; 1032 } 1033 1034 /* Init tx descriptors. */ 1035 arge_tx_ring_init(sc); 1036 1037 arge_reset_dma(sc); 1038 1039 if (sc->arge_miibus) { 1040 mii = device_get_softc(sc->arge_miibus); 1041 mii_mediachg(mii); 1042 } 1043 else { 1044 /* 1045 * Sun always shines over multiPHY interface 1046 */ 1047 sc->arge_link_status = 1; 1048 } 1049 1050 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1051 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1052 1053 if (sc->arge_miibus) { 1054 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc); 1055 arge_update_link_locked(sc); 1056 } 1057 1058 ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0)); 1059 ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0)); 1060 1061 /* Start listening */ 1062 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN); 1063 1064 /* Enable interrupts */ 1065 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 1066 } 1067 1068 /* 1069 * Return whether the mbuf chain is correctly aligned 1070 * for the arge TX engine. 1071 * 1072 * The TX engine requires each fragment to be aligned to a 1073 * 4 byte boundary and the size of each fragment except 1074 * the last to be a multiple of 4 bytes. 1075 */ 1076 static int 1077 arge_mbuf_chain_is_tx_aligned(struct mbuf *m0) 1078 { 1079 struct mbuf *m; 1080 1081 for (m = m0; m != NULL; m = m->m_next) { 1082 if((mtod(m, intptr_t) & 3) != 0) 1083 return 0; 1084 if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0)) 1085 return 0; 1086 } 1087 return 1; 1088 } 1089 1090 /* 1091 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1092 * pointers to the fragment pointers. 1093 */ 1094 static int 1095 arge_encap(struct arge_softc *sc, struct mbuf **m_head) 1096 { 1097 struct arge_txdesc *txd; 1098 struct arge_desc *desc, *prev_desc; 1099 bus_dma_segment_t txsegs[ARGE_MAXFRAGS]; 1100 int error, i, nsegs, prod, prev_prod; 1101 struct mbuf *m; 1102 1103 ARGE_LOCK_ASSERT(sc); 1104 1105 /* 1106 * Fix mbuf chain, all fragments should be 4 bytes aligned and 1107 * even 4 bytes 1108 */ 1109 m = *m_head; 1110 if (! arge_mbuf_chain_is_tx_aligned(m)) { 1111 sc->stats.tx_pkts_unaligned++; 1112 m = m_defrag(*m_head, M_NOWAIT); 1113 if (m == NULL) { 1114 m_freem(*m_head); 1115 *m_head = NULL; 1116 return (ENOBUFS); 1117 } 1118 *m_head = m; 1119 } else 1120 sc->stats.tx_pkts_aligned++; 1121 1122 prod = sc->arge_cdata.arge_tx_prod; 1123 txd = &sc->arge_cdata.arge_txdesc[prod]; 1124 error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag, 1125 txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1126 1127 if (error == EFBIG) { 1128 panic("EFBIG"); 1129 } else if (error != 0) 1130 return (error); 1131 1132 if (nsegs == 0) { 1133 m_freem(*m_head); 1134 *m_head = NULL; 1135 return (EIO); 1136 } 1137 1138 /* Check number of available descriptors. */ 1139 if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) { 1140 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap); 1141 return (ENOBUFS); 1142 } 1143 1144 txd->tx_m = *m_head; 1145 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap, 1146 BUS_DMASYNC_PREWRITE); 1147 1148 /* 1149 * Make a list of descriptors for this packet. DMA controller will 1150 * walk through it while arge_link is not zero. 1151 */ 1152 prev_prod = prod; 1153 desc = prev_desc = NULL; 1154 for (i = 0; i < nsegs; i++) { 1155 desc = &sc->arge_rdata.arge_tx_ring[prod]; 1156 desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len); 1157 1158 if (txsegs[i].ds_addr & 3) 1159 panic("TX packet address unaligned\n"); 1160 1161 desc->packet_addr = txsegs[i].ds_addr; 1162 1163 /* link with previous descriptor */ 1164 if (prev_desc) 1165 prev_desc->packet_ctrl |= ARGE_DESC_MORE; 1166 1167 sc->arge_cdata.arge_tx_cnt++; 1168 prev_desc = desc; 1169 ARGE_INC(prod, ARGE_TX_RING_COUNT); 1170 } 1171 1172 /* Update producer index. */ 1173 sc->arge_cdata.arge_tx_prod = prod; 1174 1175 /* Sync descriptors. */ 1176 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1177 sc->arge_cdata.arge_tx_ring_map, 1178 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1179 1180 /* Start transmitting */ 1181 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: setting DMA_TX_CONTROL_EN\n", 1182 __func__); 1183 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN); 1184 return (0); 1185 } 1186 1187 static void 1188 arge_start(struct ifnet *ifp) 1189 { 1190 struct arge_softc *sc; 1191 1192 sc = ifp->if_softc; 1193 1194 ARGE_LOCK(sc); 1195 arge_start_locked(ifp); 1196 ARGE_UNLOCK(sc); 1197 } 1198 1199 static void 1200 arge_start_locked(struct ifnet *ifp) 1201 { 1202 struct arge_softc *sc; 1203 struct mbuf *m_head; 1204 int enq = 0; 1205 1206 sc = ifp->if_softc; 1207 1208 ARGE_LOCK_ASSERT(sc); 1209 1210 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: beginning\n", __func__); 1211 1212 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1213 IFF_DRV_RUNNING || sc->arge_link_status == 0 ) 1214 return; 1215 1216 /* 1217 * Before we go any further, check whether we're already full. 1218 * The below check errors out immediately if the ring is full 1219 * and never gets a chance to set this flag. Although it's 1220 * likely never needed, this at least avoids an unexpected 1221 * situation. 1222 */ 1223 if (sc->arge_cdata.arge_tx_cnt >= ARGE_TX_RING_COUNT - 2) { 1224 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1225 ARGEDEBUG(sc, ARGE_DBG_ERR, 1226 "%s: tx_cnt %d >= max %d; setting IFF_DRV_OACTIVE\n", 1227 __func__, sc->arge_cdata.arge_tx_cnt, 1228 ARGE_TX_RING_COUNT - 2); 1229 return; 1230 } 1231 1232 arge_flush_ddr(sc); 1233 1234 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1235 sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) { 1236 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1237 if (m_head == NULL) 1238 break; 1239 1240 1241 /* 1242 * Pack the data into the transmit ring. 1243 */ 1244 if (arge_encap(sc, &m_head)) { 1245 if (m_head == NULL) 1246 break; 1247 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1248 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1249 break; 1250 } 1251 1252 enq++; 1253 /* 1254 * If there's a BPF listener, bounce a copy of this frame 1255 * to him. 1256 */ 1257 ETHER_BPF_MTAP(ifp, m_head); 1258 } 1259 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: finished; queued %d packets\n", 1260 __func__, enq); 1261 } 1262 1263 static void 1264 arge_stop(struct arge_softc *sc) 1265 { 1266 struct ifnet *ifp; 1267 1268 ARGE_LOCK_ASSERT(sc); 1269 1270 ifp = sc->arge_ifp; 1271 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1272 if (sc->arge_miibus) 1273 callout_stop(&sc->arge_stat_callout); 1274 1275 /* mask out interrupts */ 1276 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 1277 1278 arge_reset_dma(sc); 1279 1280 /* Flush FIFO and free any existing mbufs */ 1281 arge_flush_ddr(sc); 1282 arge_rx_ring_free(sc); 1283 arge_tx_ring_free(sc); 1284 } 1285 1286 1287 static int 1288 arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1289 { 1290 struct arge_softc *sc = ifp->if_softc; 1291 struct ifreq *ifr = (struct ifreq *) data; 1292 struct mii_data *mii; 1293 int error; 1294 #ifdef DEVICE_POLLING 1295 int mask; 1296 #endif 1297 1298 switch (command) { 1299 case SIOCSIFFLAGS: 1300 ARGE_LOCK(sc); 1301 if ((ifp->if_flags & IFF_UP) != 0) { 1302 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1303 if (((ifp->if_flags ^ sc->arge_if_flags) 1304 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1305 /* XXX: handle promisc & multi flags */ 1306 } 1307 1308 } else { 1309 if (!sc->arge_detach) 1310 arge_init_locked(sc); 1311 } 1312 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1313 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1314 arge_stop(sc); 1315 } 1316 sc->arge_if_flags = ifp->if_flags; 1317 ARGE_UNLOCK(sc); 1318 error = 0; 1319 break; 1320 case SIOCADDMULTI: 1321 case SIOCDELMULTI: 1322 /* XXX: implement SIOCDELMULTI */ 1323 error = 0; 1324 break; 1325 case SIOCGIFMEDIA: 1326 case SIOCSIFMEDIA: 1327 if (sc->arge_miibus) { 1328 mii = device_get_softc(sc->arge_miibus); 1329 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, 1330 command); 1331 } 1332 else 1333 error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia, 1334 command); 1335 break; 1336 case SIOCSIFCAP: 1337 /* XXX: Check other capabilities */ 1338 #ifdef DEVICE_POLLING 1339 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 1340 if (mask & IFCAP_POLLING) { 1341 if (ifr->ifr_reqcap & IFCAP_POLLING) { 1342 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 1343 error = ether_poll_register(arge_poll, ifp); 1344 if (error) 1345 return error; 1346 ARGE_LOCK(sc); 1347 ifp->if_capenable |= IFCAP_POLLING; 1348 ARGE_UNLOCK(sc); 1349 } else { 1350 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 1351 error = ether_poll_deregister(ifp); 1352 ARGE_LOCK(sc); 1353 ifp->if_capenable &= ~IFCAP_POLLING; 1354 ARGE_UNLOCK(sc); 1355 } 1356 } 1357 error = 0; 1358 break; 1359 #endif 1360 default: 1361 error = ether_ioctl(ifp, command, data); 1362 break; 1363 } 1364 1365 return (error); 1366 } 1367 1368 /* 1369 * Set media options. 1370 */ 1371 static int 1372 arge_ifmedia_upd(struct ifnet *ifp) 1373 { 1374 struct arge_softc *sc; 1375 struct mii_data *mii; 1376 struct mii_softc *miisc; 1377 int error; 1378 1379 sc = ifp->if_softc; 1380 ARGE_LOCK(sc); 1381 mii = device_get_softc(sc->arge_miibus); 1382 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1383 PHY_RESET(miisc); 1384 error = mii_mediachg(mii); 1385 ARGE_UNLOCK(sc); 1386 1387 return (error); 1388 } 1389 1390 /* 1391 * Report current media status. 1392 */ 1393 static void 1394 arge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1395 { 1396 struct arge_softc *sc = ifp->if_softc; 1397 struct mii_data *mii; 1398 1399 mii = device_get_softc(sc->arge_miibus); 1400 ARGE_LOCK(sc); 1401 mii_pollstat(mii); 1402 ifmr->ifm_active = mii->mii_media_active; 1403 ifmr->ifm_status = mii->mii_media_status; 1404 ARGE_UNLOCK(sc); 1405 } 1406 1407 struct arge_dmamap_arg { 1408 bus_addr_t arge_busaddr; 1409 }; 1410 1411 static void 1412 arge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1413 { 1414 struct arge_dmamap_arg *ctx; 1415 1416 if (error != 0) 1417 return; 1418 ctx = arg; 1419 ctx->arge_busaddr = segs[0].ds_addr; 1420 } 1421 1422 static int 1423 arge_dma_alloc(struct arge_softc *sc) 1424 { 1425 struct arge_dmamap_arg ctx; 1426 struct arge_txdesc *txd; 1427 struct arge_rxdesc *rxd; 1428 int error, i; 1429 1430 /* Create parent DMA tag. */ 1431 error = bus_dma_tag_create( 1432 bus_get_dma_tag(sc->arge_dev), /* parent */ 1433 1, 0, /* alignment, boundary */ 1434 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1435 BUS_SPACE_MAXADDR, /* highaddr */ 1436 NULL, NULL, /* filter, filterarg */ 1437 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1438 0, /* nsegments */ 1439 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1440 0, /* flags */ 1441 NULL, NULL, /* lockfunc, lockarg */ 1442 &sc->arge_cdata.arge_parent_tag); 1443 if (error != 0) { 1444 device_printf(sc->arge_dev, 1445 "failed to create parent DMA tag\n"); 1446 goto fail; 1447 } 1448 /* Create tag for Tx ring. */ 1449 error = bus_dma_tag_create( 1450 sc->arge_cdata.arge_parent_tag, /* parent */ 1451 ARGE_RING_ALIGN, 0, /* alignment, boundary */ 1452 BUS_SPACE_MAXADDR, /* lowaddr */ 1453 BUS_SPACE_MAXADDR, /* highaddr */ 1454 NULL, NULL, /* filter, filterarg */ 1455 ARGE_TX_DMA_SIZE, /* maxsize */ 1456 1, /* nsegments */ 1457 ARGE_TX_DMA_SIZE, /* maxsegsize */ 1458 0, /* flags */ 1459 NULL, NULL, /* lockfunc, lockarg */ 1460 &sc->arge_cdata.arge_tx_ring_tag); 1461 if (error != 0) { 1462 device_printf(sc->arge_dev, 1463 "failed to create Tx ring DMA tag\n"); 1464 goto fail; 1465 } 1466 1467 /* Create tag for Rx ring. */ 1468 error = bus_dma_tag_create( 1469 sc->arge_cdata.arge_parent_tag, /* parent */ 1470 ARGE_RING_ALIGN, 0, /* alignment, boundary */ 1471 BUS_SPACE_MAXADDR, /* lowaddr */ 1472 BUS_SPACE_MAXADDR, /* highaddr */ 1473 NULL, NULL, /* filter, filterarg */ 1474 ARGE_RX_DMA_SIZE, /* maxsize */ 1475 1, /* nsegments */ 1476 ARGE_RX_DMA_SIZE, /* maxsegsize */ 1477 0, /* flags */ 1478 NULL, NULL, /* lockfunc, lockarg */ 1479 &sc->arge_cdata.arge_rx_ring_tag); 1480 if (error != 0) { 1481 device_printf(sc->arge_dev, 1482 "failed to create Rx ring DMA tag\n"); 1483 goto fail; 1484 } 1485 1486 /* Create tag for Tx buffers. */ 1487 error = bus_dma_tag_create( 1488 sc->arge_cdata.arge_parent_tag, /* parent */ 1489 sizeof(uint32_t), 0, /* alignment, boundary */ 1490 BUS_SPACE_MAXADDR, /* lowaddr */ 1491 BUS_SPACE_MAXADDR, /* highaddr */ 1492 NULL, NULL, /* filter, filterarg */ 1493 MCLBYTES * ARGE_MAXFRAGS, /* maxsize */ 1494 ARGE_MAXFRAGS, /* nsegments */ 1495 MCLBYTES, /* maxsegsize */ 1496 0, /* flags */ 1497 NULL, NULL, /* lockfunc, lockarg */ 1498 &sc->arge_cdata.arge_tx_tag); 1499 if (error != 0) { 1500 device_printf(sc->arge_dev, "failed to create Tx DMA tag\n"); 1501 goto fail; 1502 } 1503 1504 /* Create tag for Rx buffers. */ 1505 error = bus_dma_tag_create( 1506 sc->arge_cdata.arge_parent_tag, /* parent */ 1507 ARGE_RX_ALIGN, 0, /* alignment, boundary */ 1508 BUS_SPACE_MAXADDR, /* lowaddr */ 1509 BUS_SPACE_MAXADDR, /* highaddr */ 1510 NULL, NULL, /* filter, filterarg */ 1511 MCLBYTES, /* maxsize */ 1512 ARGE_MAXFRAGS, /* nsegments */ 1513 MCLBYTES, /* maxsegsize */ 1514 0, /* flags */ 1515 NULL, NULL, /* lockfunc, lockarg */ 1516 &sc->arge_cdata.arge_rx_tag); 1517 if (error != 0) { 1518 device_printf(sc->arge_dev, "failed to create Rx DMA tag\n"); 1519 goto fail; 1520 } 1521 1522 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1523 error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag, 1524 (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK | 1525 BUS_DMA_COHERENT | BUS_DMA_ZERO, 1526 &sc->arge_cdata.arge_tx_ring_map); 1527 if (error != 0) { 1528 device_printf(sc->arge_dev, 1529 "failed to allocate DMA'able memory for Tx ring\n"); 1530 goto fail; 1531 } 1532 1533 ctx.arge_busaddr = 0; 1534 error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag, 1535 sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring, 1536 ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0); 1537 if (error != 0 || ctx.arge_busaddr == 0) { 1538 device_printf(sc->arge_dev, 1539 "failed to load DMA'able memory for Tx ring\n"); 1540 goto fail; 1541 } 1542 sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr; 1543 1544 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 1545 error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag, 1546 (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK | 1547 BUS_DMA_COHERENT | BUS_DMA_ZERO, 1548 &sc->arge_cdata.arge_rx_ring_map); 1549 if (error != 0) { 1550 device_printf(sc->arge_dev, 1551 "failed to allocate DMA'able memory for Rx ring\n"); 1552 goto fail; 1553 } 1554 1555 ctx.arge_busaddr = 0; 1556 error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag, 1557 sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring, 1558 ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0); 1559 if (error != 0 || ctx.arge_busaddr == 0) { 1560 device_printf(sc->arge_dev, 1561 "failed to load DMA'able memory for Rx ring\n"); 1562 goto fail; 1563 } 1564 sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr; 1565 1566 /* Create DMA maps for Tx buffers. */ 1567 for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1568 txd = &sc->arge_cdata.arge_txdesc[i]; 1569 txd->tx_m = NULL; 1570 txd->tx_dmamap = NULL; 1571 error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0, 1572 &txd->tx_dmamap); 1573 if (error != 0) { 1574 device_printf(sc->arge_dev, 1575 "failed to create Tx dmamap\n"); 1576 goto fail; 1577 } 1578 } 1579 /* Create DMA maps for Rx buffers. */ 1580 if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0, 1581 &sc->arge_cdata.arge_rx_sparemap)) != 0) { 1582 device_printf(sc->arge_dev, 1583 "failed to create spare Rx dmamap\n"); 1584 goto fail; 1585 } 1586 for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1587 rxd = &sc->arge_cdata.arge_rxdesc[i]; 1588 rxd->rx_m = NULL; 1589 rxd->rx_dmamap = NULL; 1590 error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0, 1591 &rxd->rx_dmamap); 1592 if (error != 0) { 1593 device_printf(sc->arge_dev, 1594 "failed to create Rx dmamap\n"); 1595 goto fail; 1596 } 1597 } 1598 1599 fail: 1600 return (error); 1601 } 1602 1603 static void 1604 arge_dma_free(struct arge_softc *sc) 1605 { 1606 struct arge_txdesc *txd; 1607 struct arge_rxdesc *rxd; 1608 int i; 1609 1610 /* Tx ring. */ 1611 if (sc->arge_cdata.arge_tx_ring_tag) { 1612 if (sc->arge_cdata.arge_tx_ring_map) 1613 bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag, 1614 sc->arge_cdata.arge_tx_ring_map); 1615 if (sc->arge_cdata.arge_tx_ring_map && 1616 sc->arge_rdata.arge_tx_ring) 1617 bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag, 1618 sc->arge_rdata.arge_tx_ring, 1619 sc->arge_cdata.arge_tx_ring_map); 1620 sc->arge_rdata.arge_tx_ring = NULL; 1621 sc->arge_cdata.arge_tx_ring_map = NULL; 1622 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag); 1623 sc->arge_cdata.arge_tx_ring_tag = NULL; 1624 } 1625 /* Rx ring. */ 1626 if (sc->arge_cdata.arge_rx_ring_tag) { 1627 if (sc->arge_cdata.arge_rx_ring_map) 1628 bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag, 1629 sc->arge_cdata.arge_rx_ring_map); 1630 if (sc->arge_cdata.arge_rx_ring_map && 1631 sc->arge_rdata.arge_rx_ring) 1632 bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag, 1633 sc->arge_rdata.arge_rx_ring, 1634 sc->arge_cdata.arge_rx_ring_map); 1635 sc->arge_rdata.arge_rx_ring = NULL; 1636 sc->arge_cdata.arge_rx_ring_map = NULL; 1637 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag); 1638 sc->arge_cdata.arge_rx_ring_tag = NULL; 1639 } 1640 /* Tx buffers. */ 1641 if (sc->arge_cdata.arge_tx_tag) { 1642 for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1643 txd = &sc->arge_cdata.arge_txdesc[i]; 1644 if (txd->tx_dmamap) { 1645 bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag, 1646 txd->tx_dmamap); 1647 txd->tx_dmamap = NULL; 1648 } 1649 } 1650 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag); 1651 sc->arge_cdata.arge_tx_tag = NULL; 1652 } 1653 /* Rx buffers. */ 1654 if (sc->arge_cdata.arge_rx_tag) { 1655 for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1656 rxd = &sc->arge_cdata.arge_rxdesc[i]; 1657 if (rxd->rx_dmamap) { 1658 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag, 1659 rxd->rx_dmamap); 1660 rxd->rx_dmamap = NULL; 1661 } 1662 } 1663 if (sc->arge_cdata.arge_rx_sparemap) { 1664 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag, 1665 sc->arge_cdata.arge_rx_sparemap); 1666 sc->arge_cdata.arge_rx_sparemap = 0; 1667 } 1668 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag); 1669 sc->arge_cdata.arge_rx_tag = NULL; 1670 } 1671 1672 if (sc->arge_cdata.arge_parent_tag) { 1673 bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag); 1674 sc->arge_cdata.arge_parent_tag = NULL; 1675 } 1676 } 1677 1678 /* 1679 * Initialize the transmit descriptors. 1680 */ 1681 static int 1682 arge_tx_ring_init(struct arge_softc *sc) 1683 { 1684 struct arge_ring_data *rd; 1685 struct arge_txdesc *txd; 1686 bus_addr_t addr; 1687 int i; 1688 1689 sc->arge_cdata.arge_tx_prod = 0; 1690 sc->arge_cdata.arge_tx_cons = 0; 1691 sc->arge_cdata.arge_tx_cnt = 0; 1692 1693 rd = &sc->arge_rdata; 1694 bzero(rd->arge_tx_ring, sizeof(rd->arge_tx_ring)); 1695 for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1696 if (i == ARGE_TX_RING_COUNT - 1) 1697 addr = ARGE_TX_RING_ADDR(sc, 0); 1698 else 1699 addr = ARGE_TX_RING_ADDR(sc, i + 1); 1700 rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY; 1701 rd->arge_tx_ring[i].next_desc = addr; 1702 txd = &sc->arge_cdata.arge_txdesc[i]; 1703 txd->tx_m = NULL; 1704 } 1705 1706 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1707 sc->arge_cdata.arge_tx_ring_map, 1708 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1709 1710 return (0); 1711 } 1712 1713 /* 1714 * Free the Tx ring, unload any pending dma transaction and free the mbuf. 1715 */ 1716 static void 1717 arge_tx_ring_free(struct arge_softc *sc) 1718 { 1719 struct arge_txdesc *txd; 1720 int i; 1721 1722 /* Free the Tx buffers. */ 1723 for (i = 0; i < ARGE_TX_RING_COUNT; i++) { 1724 txd = &sc->arge_cdata.arge_txdesc[i]; 1725 if (txd->tx_dmamap) { 1726 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, 1727 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1728 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, 1729 txd->tx_dmamap); 1730 } 1731 if (txd->tx_m) 1732 m_freem(txd->tx_m); 1733 txd->tx_m = NULL; 1734 } 1735 } 1736 1737 /* 1738 * Initialize the RX descriptors and allocate mbufs for them. Note that 1739 * we arrange the descriptors in a closed ring, so that the last descriptor 1740 * points back to the first. 1741 */ 1742 static int 1743 arge_rx_ring_init(struct arge_softc *sc) 1744 { 1745 struct arge_ring_data *rd; 1746 struct arge_rxdesc *rxd; 1747 bus_addr_t addr; 1748 int i; 1749 1750 sc->arge_cdata.arge_rx_cons = 0; 1751 1752 rd = &sc->arge_rdata; 1753 bzero(rd->arge_rx_ring, sizeof(rd->arge_rx_ring)); 1754 for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1755 rxd = &sc->arge_cdata.arge_rxdesc[i]; 1756 if (rxd->rx_m != NULL) { 1757 device_printf(sc->arge_dev, 1758 "%s: ring[%d] rx_m wasn't free?\n", 1759 __func__, 1760 i); 1761 } 1762 rxd->rx_m = NULL; 1763 rxd->desc = &rd->arge_rx_ring[i]; 1764 if (i == ARGE_RX_RING_COUNT - 1) 1765 addr = ARGE_RX_RING_ADDR(sc, 0); 1766 else 1767 addr = ARGE_RX_RING_ADDR(sc, i + 1); 1768 rd->arge_rx_ring[i].next_desc = addr; 1769 if (arge_newbuf(sc, i) != 0) { 1770 return (ENOBUFS); 1771 } 1772 } 1773 1774 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1775 sc->arge_cdata.arge_rx_ring_map, 1776 BUS_DMASYNC_PREWRITE); 1777 1778 return (0); 1779 } 1780 1781 /* 1782 * Free all the buffers in the RX ring. 1783 * 1784 * TODO: ensure that DMA is disabled and no pending DMA 1785 * is lurking in the FIFO. 1786 */ 1787 static void 1788 arge_rx_ring_free(struct arge_softc *sc) 1789 { 1790 int i; 1791 struct arge_rxdesc *rxd; 1792 1793 ARGE_LOCK_ASSERT(sc); 1794 1795 for (i = 0; i < ARGE_RX_RING_COUNT; i++) { 1796 rxd = &sc->arge_cdata.arge_rxdesc[i]; 1797 /* Unmap the mbuf */ 1798 if (rxd->rx_m != NULL) { 1799 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, 1800 rxd->rx_dmamap); 1801 m_free(rxd->rx_m); 1802 rxd->rx_m = NULL; 1803 } 1804 } 1805 } 1806 1807 /* 1808 * Initialize an RX descriptor and attach an MBUF cluster. 1809 */ 1810 static int 1811 arge_newbuf(struct arge_softc *sc, int idx) 1812 { 1813 struct arge_desc *desc; 1814 struct arge_rxdesc *rxd; 1815 struct mbuf *m; 1816 bus_dma_segment_t segs[1]; 1817 bus_dmamap_t map; 1818 int nsegs; 1819 1820 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1821 if (m == NULL) 1822 return (ENOBUFS); 1823 m->m_len = m->m_pkthdr.len = MCLBYTES; 1824 m_adj(m, sizeof(uint64_t)); 1825 1826 if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag, 1827 sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1828 m_freem(m); 1829 return (ENOBUFS); 1830 } 1831 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1832 1833 rxd = &sc->arge_cdata.arge_rxdesc[idx]; 1834 if (rxd->rx_m != NULL) { 1835 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap); 1836 } 1837 map = rxd->rx_dmamap; 1838 rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap; 1839 sc->arge_cdata.arge_rx_sparemap = map; 1840 rxd->rx_m = m; 1841 desc = rxd->desc; 1842 if (segs[0].ds_addr & 3) 1843 panic("RX packet address unaligned"); 1844 desc->packet_addr = segs[0].ds_addr; 1845 desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len); 1846 1847 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1848 sc->arge_cdata.arge_rx_ring_map, 1849 BUS_DMASYNC_PREWRITE); 1850 1851 return (0); 1852 } 1853 1854 static __inline void 1855 arge_fixup_rx(struct mbuf *m) 1856 { 1857 int i; 1858 uint16_t *src, *dst; 1859 1860 src = mtod(m, uint16_t *); 1861 dst = src - 1; 1862 1863 for (i = 0; i < m->m_len / sizeof(uint16_t); i++) { 1864 *dst++ = *src++; 1865 } 1866 1867 if (m->m_len % sizeof(uint16_t)) 1868 *(uint8_t *)dst = *(uint8_t *)src; 1869 1870 m->m_data -= ETHER_ALIGN; 1871 } 1872 1873 #ifdef DEVICE_POLLING 1874 static int 1875 arge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1876 { 1877 struct arge_softc *sc = ifp->if_softc; 1878 int rx_npkts = 0; 1879 1880 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1881 ARGE_LOCK(sc); 1882 arge_tx_locked(sc); 1883 rx_npkts = arge_rx_locked(sc); 1884 ARGE_UNLOCK(sc); 1885 } 1886 1887 return (rx_npkts); 1888 } 1889 #endif /* DEVICE_POLLING */ 1890 1891 1892 static void 1893 arge_tx_locked(struct arge_softc *sc) 1894 { 1895 struct arge_txdesc *txd; 1896 struct arge_desc *cur_tx; 1897 struct ifnet *ifp; 1898 uint32_t ctrl; 1899 int cons, prod; 1900 1901 ARGE_LOCK_ASSERT(sc); 1902 1903 cons = sc->arge_cdata.arge_tx_cons; 1904 prod = sc->arge_cdata.arge_tx_prod; 1905 1906 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: cons=%d, prod=%d\n", __func__, cons, 1907 prod); 1908 1909 if (cons == prod) 1910 return; 1911 1912 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1913 sc->arge_cdata.arge_tx_ring_map, 1914 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1915 1916 ifp = sc->arge_ifp; 1917 /* 1918 * Go through our tx list and free mbufs for those 1919 * frames that have been transmitted. 1920 */ 1921 for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) { 1922 cur_tx = &sc->arge_rdata.arge_tx_ring[cons]; 1923 ctrl = cur_tx->packet_ctrl; 1924 /* Check if descriptor has "finished" flag */ 1925 if ((ctrl & ARGE_DESC_EMPTY) == 0) 1926 break; 1927 1928 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT); 1929 1930 sc->arge_cdata.arge_tx_cnt--; 1931 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1932 1933 txd = &sc->arge_cdata.arge_txdesc[cons]; 1934 1935 ifp->if_opackets++; 1936 1937 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap, 1938 BUS_DMASYNC_POSTWRITE); 1939 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap); 1940 1941 /* Free only if it's first descriptor in list */ 1942 if (txd->tx_m) 1943 m_freem(txd->tx_m); 1944 txd->tx_m = NULL; 1945 1946 /* reset descriptor */ 1947 cur_tx->packet_addr = 0; 1948 } 1949 1950 sc->arge_cdata.arge_tx_cons = cons; 1951 1952 bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag, 1953 sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE); 1954 } 1955 1956 1957 static int 1958 arge_rx_locked(struct arge_softc *sc) 1959 { 1960 struct arge_rxdesc *rxd; 1961 struct ifnet *ifp = sc->arge_ifp; 1962 int cons, prog, packet_len, i; 1963 struct arge_desc *cur_rx; 1964 struct mbuf *m; 1965 int rx_npkts = 0; 1966 1967 ARGE_LOCK_ASSERT(sc); 1968 1969 cons = sc->arge_cdata.arge_rx_cons; 1970 1971 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 1972 sc->arge_cdata.arge_rx_ring_map, 1973 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1974 1975 for (prog = 0; prog < ARGE_RX_RING_COUNT; 1976 ARGE_INC(cons, ARGE_RX_RING_COUNT)) { 1977 cur_rx = &sc->arge_rdata.arge_rx_ring[cons]; 1978 rxd = &sc->arge_cdata.arge_rxdesc[cons]; 1979 m = rxd->rx_m; 1980 1981 if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0) 1982 break; 1983 1984 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD); 1985 1986 prog++; 1987 1988 packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl); 1989 bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap, 1990 BUS_DMASYNC_POSTREAD); 1991 m = rxd->rx_m; 1992 1993 arge_fixup_rx(m); 1994 m->m_pkthdr.rcvif = ifp; 1995 /* Skip 4 bytes of CRC */ 1996 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN; 1997 ifp->if_ipackets++; 1998 rx_npkts++; 1999 2000 ARGE_UNLOCK(sc); 2001 (*ifp->if_input)(ifp, m); 2002 ARGE_LOCK(sc); 2003 cur_rx->packet_addr = 0; 2004 } 2005 2006 if (prog > 0) { 2007 2008 i = sc->arge_cdata.arge_rx_cons; 2009 for (; prog > 0 ; prog--) { 2010 if (arge_newbuf(sc, i) != 0) { 2011 device_printf(sc->arge_dev, 2012 "Failed to allocate buffer\n"); 2013 break; 2014 } 2015 ARGE_INC(i, ARGE_RX_RING_COUNT); 2016 } 2017 2018 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag, 2019 sc->arge_cdata.arge_rx_ring_map, 2020 BUS_DMASYNC_PREWRITE); 2021 2022 sc->arge_cdata.arge_rx_cons = cons; 2023 } 2024 2025 return (rx_npkts); 2026 } 2027 2028 static int 2029 arge_intr_filter(void *arg) 2030 { 2031 struct arge_softc *sc = arg; 2032 uint32_t status, ints; 2033 2034 status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS); 2035 ints = ARGE_READ(sc, AR71XX_DMA_INTR); 2036 2037 ARGEDEBUG(sc, ARGE_DBG_INTR, "int mask(filter) = %b\n", ints, 2038 "\2\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD" 2039 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 2040 ARGEDEBUG(sc, ARGE_DBG_INTR, "status(filter) = %b\n", status, 2041 "\2\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD" 2042 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 2043 2044 if (status & DMA_INTR_ALL) { 2045 sc->arge_intr_status |= status; 2046 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0); 2047 return (FILTER_SCHEDULE_THREAD); 2048 } 2049 2050 sc->arge_intr_status = 0; 2051 return (FILTER_STRAY); 2052 } 2053 2054 static void 2055 arge_intr(void *arg) 2056 { 2057 struct arge_softc *sc = arg; 2058 uint32_t status; 2059 struct ifnet *ifp = sc->arge_ifp; 2060 2061 status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS); 2062 status |= sc->arge_intr_status; 2063 2064 ARGEDEBUG(sc, ARGE_DBG_INTR, "int status(intr) = %b\n", status, 2065 "\2\1\7RX_OVERFLOW\5RX_PKT_RCVD" 2066 "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT"); 2067 2068 /* 2069 * Is it our interrupt at all? 2070 */ 2071 if (status == 0) 2072 return; 2073 2074 if (status & DMA_INTR_RX_BUS_ERROR) { 2075 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR); 2076 device_printf(sc->arge_dev, "RX bus error"); 2077 return; 2078 } 2079 2080 if (status & DMA_INTR_TX_BUS_ERROR) { 2081 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR); 2082 device_printf(sc->arge_dev, "TX bus error"); 2083 return; 2084 } 2085 2086 ARGE_LOCK(sc); 2087 2088 if (status & DMA_INTR_RX_PKT_RCVD) 2089 arge_rx_locked(sc); 2090 2091 /* 2092 * RX overrun disables the receiver. 2093 * Clear indication and re-enable rx. 2094 */ 2095 if ( status & DMA_INTR_RX_OVERFLOW) { 2096 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW); 2097 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN); 2098 sc->stats.rx_overflow++; 2099 } 2100 2101 if (status & DMA_INTR_TX_PKT_SENT) 2102 arge_tx_locked(sc); 2103 /* 2104 * Underrun turns off TX. Clear underrun indication. 2105 * If there's anything left in the ring, reactivate the tx. 2106 */ 2107 if (status & DMA_INTR_TX_UNDERRUN) { 2108 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN); 2109 sc->stats.tx_underflow++; 2110 ARGEDEBUG(sc, ARGE_DBG_TX, "%s: TX underrun; tx_cnt=%d\n", 2111 __func__, sc->arge_cdata.arge_tx_cnt); 2112 if (sc->arge_cdata.arge_tx_cnt > 0 ) { 2113 ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 2114 DMA_TX_CONTROL_EN); 2115 } 2116 } 2117 2118 /* 2119 * If we've finished TXing and there's space for more packets 2120 * to be queued for TX, do so. Otherwise we may end up in a 2121 * situation where the interface send queue was filled 2122 * whilst the hardware queue was full, then the hardware 2123 * queue was drained by the interface send queue wasn't, 2124 * and thus if_start() is never called to kick-start 2125 * the send process (and all subsequent packets are simply 2126 * discarded. 2127 * 2128 * XXX TODO: make sure that the hardware deals nicely 2129 * with the possibility of the queue being enabled above 2130 * after a TX underrun, then having the hardware queue added 2131 * to below. 2132 */ 2133 if (status & (DMA_INTR_TX_PKT_SENT | DMA_INTR_TX_UNDERRUN) && 2134 (ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) { 2135 if (!IFQ_IS_EMPTY(&ifp->if_snd)) 2136 arge_start_locked(ifp); 2137 } 2138 2139 /* 2140 * We handled all bits, clear status 2141 */ 2142 sc->arge_intr_status = 0; 2143 ARGE_UNLOCK(sc); 2144 /* 2145 * re-enable all interrupts 2146 */ 2147 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL); 2148 } 2149 2150 2151 static void 2152 arge_tick(void *xsc) 2153 { 2154 struct arge_softc *sc = xsc; 2155 struct mii_data *mii; 2156 2157 ARGE_LOCK_ASSERT(sc); 2158 2159 if (sc->arge_miibus) { 2160 mii = device_get_softc(sc->arge_miibus); 2161 mii_tick(mii); 2162 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc); 2163 } 2164 } 2165 2166 int 2167 arge_multiphy_mediachange(struct ifnet *ifp) 2168 { 2169 struct arge_softc *sc = ifp->if_softc; 2170 struct ifmedia *ifm = &sc->arge_ifmedia; 2171 struct ifmedia_entry *ife = ifm->ifm_cur; 2172 2173 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 2174 return (EINVAL); 2175 2176 if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) { 2177 device_printf(sc->arge_dev, 2178 "AUTO is not supported for multiphy MAC"); 2179 return (EINVAL); 2180 } 2181 2182 /* 2183 * Ignore everything 2184 */ 2185 return (0); 2186 } 2187 2188 void 2189 arge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2190 { 2191 struct arge_softc *sc = ifp->if_softc; 2192 2193 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 2194 ifmr->ifm_active = IFM_ETHER | sc->arge_media_type | 2195 sc->arge_duplex_mode; 2196 } 2197 2198 #if defined(ARGE_MDIO) 2199 static int 2200 argemdio_probe(device_t dev) 2201 { 2202 device_set_desc(dev, "Atheros AR71xx built-in ethernet interface, MDIO controller"); 2203 return (0); 2204 } 2205 2206 static int 2207 argemdio_attach(device_t dev) 2208 { 2209 struct arge_softc *sc; 2210 int error = 0; 2211 2212 sc = device_get_softc(dev); 2213 sc->arge_dev = dev; 2214 sc->arge_mac_unit = device_get_unit(dev); 2215 sc->arge_rid = 0; 2216 sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 2217 &sc->arge_rid, RF_ACTIVE | RF_SHAREABLE); 2218 if (sc->arge_res == NULL) { 2219 device_printf(dev, "couldn't map memory\n"); 2220 error = ENXIO; 2221 goto fail; 2222 } 2223 2224 /* Reset MAC - required for AR71xx MDIO to successfully occur */ 2225 arge_reset_mac(sc); 2226 /* Reset MII bus */ 2227 arge_reset_miibus(sc); 2228 2229 bus_generic_probe(dev); 2230 bus_enumerate_hinted_children(dev); 2231 error = bus_generic_attach(dev); 2232 fail: 2233 return (error); 2234 } 2235 2236 static int 2237 argemdio_detach(device_t dev) 2238 { 2239 return (0); 2240 } 2241 2242 #endif
Cache object: a4269570816a8270c2cf51abbcee7f1b
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