The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/if_arge.c

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    1 /*-
    2  * Copyright (c) 2009, Oleksandr Tymoshenko
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice unmodified, this list of conditions, and the following
   10  *    disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  */
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: stable/8/sys/mips/atheros/if_arge.c 230714 2012-01-29 01:22:48Z marius $");
   30 
   31 /*
   32  * AR71XX gigabit ethernet driver
   33  */
   34 #ifdef HAVE_KERNEL_OPTION_HEADERS
   35 #include "opt_device_polling.h"
   36 #endif
   37 
   38 #include <sys/param.h>
   39 #include <sys/endian.h>
   40 #include <sys/systm.h>
   41 #include <sys/sockio.h>
   42 #include <sys/mbuf.h>
   43 #include <sys/malloc.h>
   44 #include <sys/kernel.h>
   45 #include <sys/module.h>
   46 #include <sys/socket.h>
   47 #include <sys/taskqueue.h>
   48 #include <sys/sysctl.h>
   49 
   50 #include <net/if.h>
   51 #include <net/if_arp.h>
   52 #include <net/ethernet.h>
   53 #include <net/if_dl.h>
   54 #include <net/if_media.h>
   55 #include <net/if_types.h>
   56 
   57 #include <net/bpf.h>
   58 
   59 #include <machine/bus.h>
   60 #include <machine/cache.h>
   61 #include <machine/resource.h>
   62 #include <vm/vm_param.h>
   63 #include <vm/vm.h>
   64 #include <vm/pmap.h>
   65 #include <machine/pmap.h>
   66 #include <sys/bus.h>
   67 #include <sys/rman.h>
   68 
   69 #include <dev/mii/mii.h>
   70 #include <dev/mii/miivar.h>
   71 
   72 #include <dev/pci/pcireg.h>
   73 #include <dev/pci/pcivar.h>
   74 
   75 MODULE_DEPEND(arge, ether, 1, 1, 1);
   76 MODULE_DEPEND(arge, miibus, 1, 1, 1);
   77 
   78 #include "miibus_if.h"
   79 
   80 #include <mips/atheros/ar71xxreg.h>
   81 #include <mips/atheros/if_argevar.h>
   82 #include <mips/atheros/ar71xx_cpudef.h>
   83 
   84 #undef ARGE_DEBUG
   85 #ifdef ARGE_DEBUG
   86 #define dprintf printf
   87 #else
   88 #define dprintf(x, arg...)
   89 #endif
   90 
   91 static int arge_attach(device_t);
   92 static int arge_detach(device_t);
   93 static void arge_flush_ddr(struct arge_softc *);
   94 static int arge_ifmedia_upd(struct ifnet *);
   95 static void arge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
   96 static int arge_ioctl(struct ifnet *, u_long, caddr_t);
   97 static void arge_init(void *);
   98 static void arge_init_locked(struct arge_softc *);
   99 static void arge_link_task(void *, int);
  100 static void arge_set_pll(struct arge_softc *, int, int);
  101 static int arge_miibus_readreg(device_t, int, int);
  102 static void arge_miibus_statchg(device_t);
  103 static int arge_miibus_writereg(device_t, int, int, int);
  104 static int arge_probe(device_t);
  105 static void arge_reset_dma(struct arge_softc *);
  106 static int arge_resume(device_t);
  107 static int arge_rx_ring_init(struct arge_softc *);
  108 static int arge_tx_ring_init(struct arge_softc *);
  109 #ifdef DEVICE_POLLING
  110 static int arge_poll(struct ifnet *, enum poll_cmd, int);
  111 #endif
  112 static int arge_shutdown(device_t);
  113 static void arge_start(struct ifnet *);
  114 static void arge_start_locked(struct ifnet *);
  115 static void arge_stop(struct arge_softc *);
  116 static int arge_suspend(device_t);
  117 
  118 static int arge_rx_locked(struct arge_softc *);
  119 static void arge_tx_locked(struct arge_softc *);
  120 static void arge_intr(void *);
  121 static int arge_intr_filter(void *);
  122 static void arge_tick(void *);
  123 
  124 /*
  125  * ifmedia callbacks for multiPHY MAC
  126  */
  127 void arge_multiphy_mediastatus(struct ifnet *, struct ifmediareq *);
  128 int arge_multiphy_mediachange(struct ifnet *);
  129 
  130 static void arge_dmamap_cb(void *, bus_dma_segment_t *, int, int);
  131 static int arge_dma_alloc(struct arge_softc *);
  132 static void arge_dma_free(struct arge_softc *);
  133 static int arge_newbuf(struct arge_softc *, int);
  134 static __inline void arge_fixup_rx(struct mbuf *);
  135 
  136 static device_method_t arge_methods[] = {
  137         /* Device interface */
  138         DEVMETHOD(device_probe,         arge_probe),
  139         DEVMETHOD(device_attach,        arge_attach),
  140         DEVMETHOD(device_detach,        arge_detach),
  141         DEVMETHOD(device_suspend,       arge_suspend),
  142         DEVMETHOD(device_resume,        arge_resume),
  143         DEVMETHOD(device_shutdown,      arge_shutdown),
  144 
  145         /* MII interface */
  146         DEVMETHOD(miibus_readreg,       arge_miibus_readreg),
  147         DEVMETHOD(miibus_writereg,      arge_miibus_writereg),
  148         DEVMETHOD(miibus_statchg,       arge_miibus_statchg),
  149 
  150         DEVMETHOD_END
  151 };
  152 
  153 static driver_t arge_driver = {
  154         "arge",
  155         arge_methods,
  156         sizeof(struct arge_softc)
  157 };
  158 
  159 static devclass_t arge_devclass;
  160 
  161 DRIVER_MODULE(arge, nexus, arge_driver, arge_devclass, 0, 0);
  162 DRIVER_MODULE(miibus, arge, miibus_driver, miibus_devclass, 0, 0);
  163 
  164 /*
  165  * RedBoot passes MAC address to entry point as environment 
  166  * variable. platfrom_start parses it and stores in this variable
  167  */
  168 extern uint32_t ar711_base_mac[ETHER_ADDR_LEN];
  169 
  170 static struct mtx miibus_mtx;
  171 
  172 MTX_SYSINIT(miibus_mtx, &miibus_mtx, "arge mii lock", MTX_DEF);
  173 
  174 
  175 /*
  176  * Flushes all 
  177  */
  178 static void
  179 arge_flush_ddr(struct arge_softc *sc)
  180 {
  181         if (sc->arge_mac_unit == 0)
  182                 ar71xx_device_flush_ddr_ge0();
  183         else
  184                 ar71xx_device_flush_ddr_ge1();
  185 }
  186 
  187 static int 
  188 arge_probe(device_t dev)
  189 {
  190 
  191         device_set_desc(dev, "Atheros AR71xx built-in ethernet interface");
  192         return (0);
  193 }
  194 
  195 static void
  196 arge_attach_sysctl(device_t dev)
  197 {
  198         struct arge_softc *sc = device_get_softc(dev);
  199         struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
  200         struct sysctl_oid *tree = device_get_sysctl_tree(dev);
  201 
  202         SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
  203                 "debug", CTLFLAG_RW, &sc->arge_debug, 0,
  204                 "arge interface debugging flags");
  205 
  206         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
  207                 "tx_pkts_aligned", CTLFLAG_RW, &sc->stats.tx_pkts_aligned, 0,
  208                 "number of TX aligned packets");
  209 
  210         SYSCTL_ADD_UINT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
  211                 "tx_pkts_unaligned", CTLFLAG_RW, &sc->stats.tx_pkts_unaligned, 0,
  212                 "number of TX unaligned packets");
  213 }
  214 
  215 static int
  216 arge_attach(device_t dev)
  217 {
  218         uint8_t                 eaddr[ETHER_ADDR_LEN];
  219         struct ifnet            *ifp;
  220         struct arge_softc       *sc;
  221         int                     error = 0, rid, phymask;
  222         uint32_t                reg, rnd;
  223         int                     is_base_mac_empty, i, phys_total;
  224         uint32_t                hint;
  225 
  226         sc = device_get_softc(dev);
  227         sc->arge_dev = dev;
  228         sc->arge_mac_unit = device_get_unit(dev);
  229 
  230         KASSERT(((sc->arge_mac_unit == 0) || (sc->arge_mac_unit == 1)), 
  231             ("if_arge: Only MAC0 and MAC1 supported"));
  232 
  233         /*
  234          *  Get which PHY of 5 available we should use for this unit
  235          */
  236         if (resource_int_value(device_get_name(dev), device_get_unit(dev), 
  237             "phymask", &phymask) != 0) {
  238                 /*
  239                  * Use port 4 (WAN) for GE0. For any other port use 
  240                  * its PHY the same as its unit number 
  241                  */
  242                 if (sc->arge_mac_unit == 0)
  243                         phymask = (1 << 4);
  244                 else
  245                         /* Use all phys up to 4 */
  246                         phymask = (1 << 4) - 1;
  247 
  248                 device_printf(dev, "No PHY specified, using mask %d\n", phymask);
  249         }
  250 
  251         /*
  252          *  Get default media & duplex mode, by default its Base100T 
  253          *  and full duplex
  254          */
  255         if (resource_int_value(device_get_name(dev), device_get_unit(dev), 
  256             "media", &hint) != 0)
  257                 hint = 0;
  258 
  259         if (hint == 1000)
  260                 sc->arge_media_type = IFM_1000_T;
  261         else
  262                 sc->arge_media_type = IFM_100_TX;
  263 
  264         if (resource_int_value(device_get_name(dev), device_get_unit(dev), 
  265             "fduplex", &hint) != 0)
  266                 hint = 1;
  267 
  268         if (hint)
  269                 sc->arge_duplex_mode = IFM_FDX;
  270         else
  271                 sc->arge_duplex_mode = 0;
  272 
  273         sc->arge_phymask = phymask;
  274 
  275         mtx_init(&sc->arge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
  276             MTX_DEF);
  277         callout_init_mtx(&sc->arge_stat_callout, &sc->arge_mtx, 0);
  278         TASK_INIT(&sc->arge_link_task, 0, arge_link_task, sc);
  279 
  280         /* Map control/status registers. */
  281         sc->arge_rid = 0;
  282         sc->arge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 
  283             &sc->arge_rid, RF_ACTIVE);
  284 
  285         if (sc->arge_res == NULL) {
  286                 device_printf(dev, "couldn't map memory\n");
  287                 error = ENXIO;
  288                 goto fail;
  289         }
  290 
  291         /* Allocate interrupts */
  292         rid = 0;
  293         sc->arge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 
  294             RF_SHAREABLE | RF_ACTIVE);
  295 
  296         if (sc->arge_irq == NULL) {
  297                 device_printf(dev, "couldn't map interrupt\n");
  298                 error = ENXIO;
  299                 goto fail;
  300         }
  301 
  302         /* Allocate ifnet structure. */
  303         ifp = sc->arge_ifp = if_alloc(IFT_ETHER);
  304 
  305         if (ifp == NULL) {
  306                 device_printf(dev, "couldn't allocate ifnet structure\n");
  307                 error = ENOSPC;
  308                 goto fail;
  309         }
  310 
  311         ifp->if_softc = sc;
  312         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
  313         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
  314         ifp->if_ioctl = arge_ioctl;
  315         ifp->if_start = arge_start;
  316         ifp->if_init = arge_init;
  317         sc->arge_if_flags = ifp->if_flags;
  318 
  319         /* XXX: add real size */
  320         IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
  321         ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
  322         IFQ_SET_READY(&ifp->if_snd);
  323 
  324         ifp->if_capenable = ifp->if_capabilities;
  325 #ifdef DEVICE_POLLING
  326         ifp->if_capabilities |= IFCAP_POLLING;
  327 #endif
  328 
  329         is_base_mac_empty = 1;
  330         for (i = 0; i < ETHER_ADDR_LEN; i++) {
  331                 eaddr[i] = ar711_base_mac[i] & 0xff;
  332                 if (eaddr[i] != 0)
  333                         is_base_mac_empty = 0;
  334         }
  335 
  336         if (is_base_mac_empty) {
  337                 /*
  338                  * No MAC address configured. Generate the random one.
  339                  */
  340                 if  (bootverbose)
  341                         device_printf(dev, 
  342                             "Generating random ethernet address.\n");
  343 
  344                 rnd = arc4random();
  345                 eaddr[0] = 'b';
  346                 eaddr[1] = 's';
  347                 eaddr[2] = 'd';
  348                 eaddr[3] = (rnd >> 24) & 0xff;
  349                 eaddr[4] = (rnd >> 16) & 0xff;
  350                 eaddr[5] = (rnd >> 8) & 0xff;
  351         }
  352 
  353         if (sc->arge_mac_unit != 0)
  354                 eaddr[5] +=  sc->arge_mac_unit;
  355 
  356         if (arge_dma_alloc(sc) != 0) {
  357                 error = ENXIO;
  358                 goto fail;
  359         }
  360 
  361         /* Initialize the MAC block */
  362         
  363         /* Step 1. Soft-reset MAC */
  364         ARGE_SET_BITS(sc, AR71XX_MAC_CFG1, MAC_CFG1_SOFT_RESET);
  365         DELAY(20);
  366 
  367         /* Step 2. Punt the MAC core from the central reset register */
  368         ar71xx_device_stop(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC);
  369         DELAY(100);
  370         ar71xx_device_start(sc->arge_mac_unit == 0 ? RST_RESET_GE0_MAC : RST_RESET_GE1_MAC);
  371 
  372         /* Step 3. Reconfigure MAC block */
  373         ARGE_WRITE(sc, AR71XX_MAC_CFG1, 
  374                 MAC_CFG1_SYNC_RX | MAC_CFG1_RX_ENABLE |
  375                 MAC_CFG1_SYNC_TX | MAC_CFG1_TX_ENABLE);
  376 
  377         reg = ARGE_READ(sc, AR71XX_MAC_CFG2);
  378         reg |= MAC_CFG2_ENABLE_PADCRC | MAC_CFG2_LENGTH_FIELD ;
  379         ARGE_WRITE(sc, AR71XX_MAC_CFG2, reg);
  380 
  381         ARGE_WRITE(sc, AR71XX_MAC_MAX_FRAME_LEN, 1536);
  382 
  383         /* Reset MII bus */
  384         ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_RESET);
  385         DELAY(100);
  386         ARGE_WRITE(sc, AR71XX_MAC_MII_CFG, MAC_MII_CFG_CLOCK_DIV_28);
  387         DELAY(100);
  388 
  389         /* 
  390          * Set all Ethernet address registers to the same initial values
  391          * set all four addresses to 66-88-aa-cc-dd-ee 
  392          */
  393         ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR1, 
  394             (eaddr[2] << 24) | (eaddr[3] << 16) | (eaddr[4] << 8)  | eaddr[5]);
  395         ARGE_WRITE(sc, AR71XX_MAC_STA_ADDR2, (eaddr[0] << 8) | eaddr[1]);
  396 
  397         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG0, 
  398             FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT);
  399         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG1, 0x0fff0000);
  400         ARGE_WRITE(sc, AR71XX_MAC_FIFO_CFG2, 0x00001fff);
  401 
  402         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMATCH, 
  403             FIFO_RX_FILTMATCH_DEFAULT);
  404 
  405         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 
  406             FIFO_RX_FILTMASK_DEFAULT);
  407 
  408         /* 
  409          * Check if we have single-PHY MAC or multi-PHY
  410          */
  411         phys_total = 0;
  412         for (i = 0; i < ARGE_NPHY; i++)
  413                 if (phymask & (1 << i))
  414                         phys_total ++;
  415 
  416         if (phys_total == 0) {
  417                 error = EINVAL;
  418                 goto fail;
  419         }
  420 
  421         if (phys_total == 1) {
  422                 /* Do MII setup. */
  423                 if (mii_phy_probe(dev, &sc->arge_miibus,
  424                     arge_ifmedia_upd, arge_ifmedia_sts)) {
  425                         device_printf(dev, "MII without any phy!\n");
  426                         error = ENXIO;
  427                         goto fail;
  428                 }
  429         }
  430         else {
  431                 ifmedia_init(&sc->arge_ifmedia, 0, 
  432                     arge_multiphy_mediachange,
  433                     arge_multiphy_mediastatus);
  434                 ifmedia_add(&sc->arge_ifmedia,
  435                     IFM_ETHER | sc->arge_media_type  | sc->arge_duplex_mode, 
  436                     0, NULL);
  437                 ifmedia_set(&sc->arge_ifmedia,
  438                     IFM_ETHER | sc->arge_media_type  | sc->arge_duplex_mode);
  439                 arge_set_pll(sc, sc->arge_media_type, sc->arge_duplex_mode);
  440         }
  441 
  442         /* Call MI attach routine. */
  443         ether_ifattach(ifp, eaddr);
  444 
  445         /* Hook interrupt last to avoid having to lock softc */
  446         error = bus_setup_intr(dev, sc->arge_irq, INTR_TYPE_NET | INTR_MPSAFE,
  447             arge_intr_filter, arge_intr, sc, &sc->arge_intrhand);
  448 
  449         if (error) {
  450                 device_printf(dev, "couldn't set up irq\n");
  451                 ether_ifdetach(ifp);
  452                 goto fail;
  453         }
  454 
  455         /* setup sysctl variables */
  456         arge_attach_sysctl(dev);
  457 
  458 fail:
  459         if (error) 
  460                 arge_detach(dev);
  461 
  462         return (error);
  463 }
  464 
  465 static int
  466 arge_detach(device_t dev)
  467 {
  468         struct arge_softc       *sc = device_get_softc(dev);
  469         struct ifnet            *ifp = sc->arge_ifp;
  470 
  471         KASSERT(mtx_initialized(&sc->arge_mtx), ("arge mutex not initialized"));
  472 
  473         /* These should only be active if attach succeeded */
  474         if (device_is_attached(dev)) {
  475                 ARGE_LOCK(sc);
  476                 sc->arge_detach = 1;
  477 #ifdef DEVICE_POLLING
  478                 if (ifp->if_capenable & IFCAP_POLLING)
  479                         ether_poll_deregister(ifp);
  480 #endif
  481 
  482                 arge_stop(sc);
  483                 ARGE_UNLOCK(sc);
  484                 taskqueue_drain(taskqueue_swi, &sc->arge_link_task);
  485                 ether_ifdetach(ifp);
  486         }
  487 
  488         if (sc->arge_miibus)
  489                 device_delete_child(dev, sc->arge_miibus);
  490 
  491         bus_generic_detach(dev);
  492 
  493         if (sc->arge_intrhand)
  494                 bus_teardown_intr(dev, sc->arge_irq, sc->arge_intrhand);
  495 
  496         if (sc->arge_res)
  497                 bus_release_resource(dev, SYS_RES_MEMORY, sc->arge_rid, 
  498                     sc->arge_res);
  499 
  500         if (ifp)
  501                 if_free(ifp);
  502 
  503         arge_dma_free(sc);
  504 
  505         mtx_destroy(&sc->arge_mtx);
  506 
  507         return (0);
  508 
  509 }
  510 
  511 static int
  512 arge_suspend(device_t dev)
  513 {
  514 
  515         panic("%s", __func__);
  516         return 0;
  517 }
  518 
  519 static int
  520 arge_resume(device_t dev)
  521 {
  522 
  523         panic("%s", __func__);
  524         return 0;
  525 }
  526 
  527 static int
  528 arge_shutdown(device_t dev)
  529 {
  530         struct arge_softc       *sc;
  531 
  532         sc = device_get_softc(dev);
  533 
  534         ARGE_LOCK(sc);
  535         arge_stop(sc);
  536         ARGE_UNLOCK(sc);
  537 
  538         return (0);
  539 }
  540 
  541 static int
  542 arge_miibus_readreg(device_t dev, int phy, int reg)
  543 {
  544         struct arge_softc * sc = device_get_softc(dev);
  545         int i, result;
  546         uint32_t addr = (phy << MAC_MII_PHY_ADDR_SHIFT) 
  547             | (reg & MAC_MII_REG_MASK);
  548 
  549         if ((sc->arge_phymask  & (1 << phy)) == 0)
  550                 return (0);
  551 
  552         mtx_lock(&miibus_mtx);
  553         ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
  554         ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr);
  555         ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_READ);
  556 
  557         i = ARGE_MII_TIMEOUT;
  558         while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) & 
  559             MAC_MII_INDICATOR_BUSY) && (i--))
  560                 DELAY(5);
  561 
  562         if (i < 0) {
  563                 mtx_unlock(&miibus_mtx);
  564                 dprintf("%s timedout\n", __func__);
  565                 /* XXX: return ERRNO istead? */
  566                 return (-1);
  567         }
  568 
  569         result = ARGE_MII_READ(AR71XX_MAC_MII_STATUS) & MAC_MII_STATUS_MASK;
  570         ARGE_MII_WRITE(AR71XX_MAC_MII_CMD, MAC_MII_CMD_WRITE);
  571         mtx_unlock(&miibus_mtx);
  572 
  573         dprintf("%s: phy=%d, reg=%02x, value[%08x]=%04x\n", __func__, 
  574                  phy, reg, addr, result);
  575 
  576         return (result);
  577 }
  578 
  579 static int
  580 arge_miibus_writereg(device_t dev, int phy, int reg, int data)
  581 {
  582         struct arge_softc * sc = device_get_softc(dev);
  583         int i;
  584         uint32_t addr = 
  585             (phy << MAC_MII_PHY_ADDR_SHIFT) | (reg & MAC_MII_REG_MASK);
  586 
  587 
  588         if ((sc->arge_phymask  & (1 << phy)) == 0)
  589                 return (-1);
  590 
  591         dprintf("%s: phy=%d, reg=%02x, value=%04x\n", __func__, 
  592             phy, reg, data);
  593 
  594         mtx_lock(&miibus_mtx);
  595         ARGE_MII_WRITE(AR71XX_MAC_MII_ADDR, addr);
  596         ARGE_MII_WRITE(AR71XX_MAC_MII_CONTROL, data);
  597 
  598         i = ARGE_MII_TIMEOUT;
  599         while ((ARGE_MII_READ(AR71XX_MAC_MII_INDICATOR) & 
  600             MAC_MII_INDICATOR_BUSY) && (i--))
  601                 DELAY(5);
  602 
  603         mtx_unlock(&miibus_mtx);
  604 
  605         if (i < 0) {
  606                 dprintf("%s timedout\n", __func__);
  607                 /* XXX: return ERRNO istead? */
  608                 return (-1);
  609         }
  610 
  611         return (0);
  612 }
  613 
  614 static void
  615 arge_miibus_statchg(device_t dev)
  616 {
  617         struct arge_softc               *sc;
  618 
  619         sc = device_get_softc(dev);
  620         taskqueue_enqueue(taskqueue_swi, &sc->arge_link_task);
  621 }
  622 
  623 static void
  624 arge_link_task(void *arg, int pending)
  625 {
  626         struct arge_softc       *sc;
  627         struct mii_data         *mii;
  628         struct ifnet            *ifp;
  629         uint32_t                media, duplex;
  630 
  631         sc = (struct arge_softc *)arg;
  632 
  633         ARGE_LOCK(sc);
  634         mii = device_get_softc(sc->arge_miibus);
  635         ifp = sc->arge_ifp;
  636         if (mii == NULL || ifp == NULL ||
  637             (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
  638                 ARGE_UNLOCK(sc);
  639                 return;
  640         }
  641 
  642         if (mii->mii_media_status & IFM_ACTIVE) {
  643 
  644                 media = IFM_SUBTYPE(mii->mii_media_active);
  645 
  646                 if (media != IFM_NONE) {
  647                         sc->arge_link_status = 1;
  648                         duplex = mii->mii_media_active & IFM_GMASK;
  649                         arge_set_pll(sc, media, duplex);
  650                 }
  651         } else
  652                 sc->arge_link_status = 0;
  653 
  654         ARGE_UNLOCK(sc);
  655 }
  656 
  657 static void
  658 arge_set_pll(struct arge_softc *sc, int media, int duplex)
  659 {
  660         uint32_t                cfg, ifcontrol, rx_filtmask;
  661         int if_speed;
  662 
  663         cfg = ARGE_READ(sc, AR71XX_MAC_CFG2);
  664         cfg &= ~(MAC_CFG2_IFACE_MODE_1000 
  665             | MAC_CFG2_IFACE_MODE_10_100 
  666             | MAC_CFG2_FULL_DUPLEX);
  667 
  668         if (duplex == IFM_FDX)
  669                 cfg |= MAC_CFG2_FULL_DUPLEX;
  670 
  671         ifcontrol = ARGE_READ(sc, AR71XX_MAC_IFCONTROL);
  672         ifcontrol &= ~MAC_IFCONTROL_SPEED;
  673         rx_filtmask = 
  674             ARGE_READ(sc, AR71XX_MAC_FIFO_RX_FILTMASK);
  675         rx_filtmask &= ~FIFO_RX_MASK_BYTE_MODE;
  676 
  677         switch(media) {
  678         case IFM_10_T:
  679                 cfg |= MAC_CFG2_IFACE_MODE_10_100;
  680                 if_speed = 10;
  681                 break;
  682         case IFM_100_TX:
  683                 cfg |= MAC_CFG2_IFACE_MODE_10_100;
  684                 ifcontrol |= MAC_IFCONTROL_SPEED;
  685                 if_speed = 100;
  686                 break;
  687         case IFM_1000_T:
  688         case IFM_1000_SX:
  689                 cfg |= MAC_CFG2_IFACE_MODE_1000;
  690                 rx_filtmask |= FIFO_RX_MASK_BYTE_MODE;
  691                 if_speed = 1000;
  692                 break;
  693         default:
  694                 if_speed = 100;
  695                 device_printf(sc->arge_dev, 
  696                     "Unknown media %d\n", media);
  697         }
  698 
  699         ARGE_WRITE(sc, AR71XX_MAC_FIFO_TX_THRESHOLD,
  700             0x008001ff);
  701 
  702         ARGE_WRITE(sc, AR71XX_MAC_CFG2, cfg);
  703         ARGE_WRITE(sc, AR71XX_MAC_IFCONTROL, ifcontrol);
  704         ARGE_WRITE(sc, AR71XX_MAC_FIFO_RX_FILTMASK, 
  705             rx_filtmask);
  706 
  707         /* set PLL registers */
  708         if (sc->arge_mac_unit == 0)
  709                 ar71xx_device_set_pll_ge0(if_speed);
  710         else
  711                 ar71xx_device_set_pll_ge1(if_speed);
  712 }
  713 
  714 
  715 static void
  716 arge_reset_dma(struct arge_softc *sc)
  717 {
  718         ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, 0);
  719         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 0);
  720 
  721         ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, 0);
  722         ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, 0);
  723 
  724         /* Clear all possible RX interrupts */
  725         while(ARGE_READ(sc, AR71XX_DMA_RX_STATUS) & DMA_RX_STATUS_PKT_RECVD)
  726                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
  727 
  728         /* 
  729          * Clear all possible TX interrupts
  730          */
  731         while(ARGE_READ(sc, AR71XX_DMA_TX_STATUS) & DMA_TX_STATUS_PKT_SENT)
  732                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
  733 
  734         /* 
  735          * Now Rx/Tx errors
  736          */
  737         ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, 
  738             DMA_RX_STATUS_BUS_ERROR | DMA_RX_STATUS_OVERFLOW);
  739         ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, 
  740             DMA_TX_STATUS_BUS_ERROR | DMA_TX_STATUS_UNDERRUN);
  741 }
  742 
  743 
  744 
  745 static void
  746 arge_init(void *xsc)
  747 {
  748         struct arge_softc        *sc = xsc;
  749 
  750         ARGE_LOCK(sc);
  751         arge_init_locked(sc);
  752         ARGE_UNLOCK(sc);
  753 }
  754 
  755 static void
  756 arge_init_locked(struct arge_softc *sc)
  757 {
  758         struct ifnet            *ifp = sc->arge_ifp;
  759         struct mii_data         *mii;
  760 
  761         ARGE_LOCK_ASSERT(sc);
  762 
  763         arge_stop(sc);
  764 
  765         /* Init circular RX list. */
  766         if (arge_rx_ring_init(sc) != 0) {
  767                 device_printf(sc->arge_dev,
  768                     "initialization failed: no memory for rx buffers\n");
  769                 arge_stop(sc);
  770                 return;
  771         }
  772 
  773         /* Init tx descriptors. */
  774         arge_tx_ring_init(sc);
  775 
  776         arge_reset_dma(sc);
  777 
  778 
  779         if (sc->arge_miibus) {
  780                 sc->arge_link_status = 0;
  781                 mii = device_get_softc(sc->arge_miibus);
  782                 mii_mediachg(mii);
  783         }
  784         else {
  785                 /*
  786                  * Sun always shines over multiPHY interface
  787                  */
  788                 sc->arge_link_status = 1;
  789         }
  790 
  791         ifp->if_drv_flags |= IFF_DRV_RUNNING;
  792         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
  793 
  794         if (sc->arge_miibus)
  795                 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
  796 
  797         ARGE_WRITE(sc, AR71XX_DMA_TX_DESC, ARGE_TX_RING_ADDR(sc, 0));
  798         ARGE_WRITE(sc, AR71XX_DMA_RX_DESC, ARGE_RX_RING_ADDR(sc, 0));
  799 
  800         /* Start listening */
  801         ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
  802 
  803         /* Enable interrupts */
  804         ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
  805 }
  806 
  807 /*
  808  * Return whether the mbuf chain is correctly aligned
  809  * for the arge TX engine.
  810  *
  811  * The TX engine requires each fragment to be aligned to a
  812  * 4 byte boundary and the size of each fragment except
  813  * the last to be a multiple of 4 bytes.
  814  */
  815 static int
  816 arge_mbuf_chain_is_tx_aligned(struct mbuf *m0)
  817 {
  818         struct mbuf *m;
  819 
  820         for (m = m0; m != NULL; m = m->m_next) {
  821                 if((mtod(m, intptr_t) & 3) != 0)
  822                         return 0;
  823                 if ((m->m_next != NULL) && ((m->m_len & 0x03) != 0))
  824                         return 0;
  825         }
  826         return 1;
  827 }
  828 
  829 /*
  830  * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
  831  * pointers to the fragment pointers.
  832  */
  833 static int
  834 arge_encap(struct arge_softc *sc, struct mbuf **m_head)
  835 {
  836         struct arge_txdesc      *txd;
  837         struct arge_desc        *desc, *prev_desc;
  838         bus_dma_segment_t       txsegs[ARGE_MAXFRAGS];
  839         int                     error, i, nsegs, prod, prev_prod;
  840         struct mbuf             *m;
  841 
  842         ARGE_LOCK_ASSERT(sc);
  843 
  844         /*
  845          * Fix mbuf chain, all fragments should be 4 bytes aligned and
  846          * even 4 bytes
  847          */
  848         m = *m_head;
  849         if (! arge_mbuf_chain_is_tx_aligned(m)) {
  850                 sc->stats.tx_pkts_unaligned++;
  851                 m = m_defrag(*m_head, M_DONTWAIT);
  852                 if (m == NULL) {
  853                         *m_head = NULL;
  854                         return (ENOBUFS);
  855                 }
  856                 *m_head = m;
  857         } else
  858                 sc->stats.tx_pkts_aligned++;
  859 
  860         prod = sc->arge_cdata.arge_tx_prod;
  861         txd = &sc->arge_cdata.arge_txdesc[prod];
  862         error = bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_tx_tag, 
  863             txd->tx_dmamap, *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT);
  864 
  865         if (error == EFBIG) {
  866                 panic("EFBIG");
  867         } else if (error != 0)
  868                 return (error);
  869 
  870         if (nsegs == 0) {
  871                 m_freem(*m_head);
  872                 *m_head = NULL;
  873                 return (EIO);
  874         }
  875 
  876         /* Check number of available descriptors. */
  877         if (sc->arge_cdata.arge_tx_cnt + nsegs >= (ARGE_TX_RING_COUNT - 1)) {
  878                 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
  879                 return (ENOBUFS);
  880         }
  881 
  882         txd->tx_m = *m_head;
  883         bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
  884             BUS_DMASYNC_PREWRITE);
  885 
  886         /* 
  887          * Make a list of descriptors for this packet. DMA controller will
  888          * walk through it while arge_link is not zero.
  889          */
  890         prev_prod = prod;
  891         desc = prev_desc = NULL;
  892         for (i = 0; i < nsegs; i++) {
  893                 desc = &sc->arge_rdata.arge_tx_ring[prod];
  894                 desc->packet_ctrl = ARGE_DMASIZE(txsegs[i].ds_len);
  895 
  896                 if (txsegs[i].ds_addr & 3)
  897                         panic("TX packet address unaligned\n");
  898 
  899                 desc->packet_addr = txsegs[i].ds_addr;
  900                 
  901                 /* link with previous descriptor */
  902                 if (prev_desc)
  903                         prev_desc->packet_ctrl |= ARGE_DESC_MORE;
  904 
  905                 sc->arge_cdata.arge_tx_cnt++;
  906                 prev_desc = desc;
  907                 ARGE_INC(prod, ARGE_TX_RING_COUNT);
  908         }
  909 
  910         /* Update producer index. */
  911         sc->arge_cdata.arge_tx_prod = prod;
  912 
  913         /* Sync descriptors. */
  914         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
  915             sc->arge_cdata.arge_tx_ring_map,
  916             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
  917 
  918         /* Start transmitting */
  919         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, DMA_TX_CONTROL_EN);
  920         return (0);
  921 }
  922 
  923 static void
  924 arge_start(struct ifnet *ifp)
  925 {
  926         struct arge_softc        *sc;
  927 
  928         sc = ifp->if_softc;
  929 
  930         ARGE_LOCK(sc);
  931         arge_start_locked(ifp);
  932         ARGE_UNLOCK(sc);
  933 }
  934 
  935 static void
  936 arge_start_locked(struct ifnet *ifp)
  937 {
  938         struct arge_softc       *sc;
  939         struct mbuf             *m_head;
  940         int                     enq;
  941 
  942         sc = ifp->if_softc;
  943 
  944         ARGE_LOCK_ASSERT(sc);
  945 
  946         if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
  947             IFF_DRV_RUNNING || sc->arge_link_status == 0 )
  948                 return;
  949 
  950         arge_flush_ddr(sc);
  951 
  952         for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
  953             sc->arge_cdata.arge_tx_cnt < ARGE_TX_RING_COUNT - 2; ) {
  954                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
  955                 if (m_head == NULL)
  956                         break;
  957 
  958 
  959                 /*
  960                  * Pack the data into the transmit ring.
  961                  */
  962                 if (arge_encap(sc, &m_head)) {
  963                         if (m_head == NULL)
  964                                 break;
  965                         IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
  966                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
  967                         break;
  968                 }
  969 
  970                 enq++;
  971                 /*
  972                  * If there's a BPF listener, bounce a copy of this frame
  973                  * to him.
  974                  */
  975                 ETHER_BPF_MTAP(ifp, m_head);
  976         }
  977 }
  978 
  979 static void
  980 arge_stop(struct arge_softc *sc)
  981 {
  982         struct ifnet        *ifp;
  983 
  984         ARGE_LOCK_ASSERT(sc);
  985 
  986         ifp = sc->arge_ifp;
  987         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
  988         if (sc->arge_miibus)
  989                 callout_stop(&sc->arge_stat_callout);
  990 
  991         /* mask out interrupts */
  992         ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
  993 
  994         arge_reset_dma(sc);
  995 }
  996 
  997 
  998 static int
  999 arge_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
 1000 {
 1001         struct arge_softc               *sc = ifp->if_softc;
 1002         struct ifreq            *ifr = (struct ifreq *) data;
 1003         struct mii_data         *mii;
 1004         int                     error;
 1005 #ifdef DEVICE_POLLING
 1006         int                     mask;
 1007 #endif
 1008 
 1009         switch (command) {
 1010         case SIOCSIFFLAGS:
 1011                 ARGE_LOCK(sc);
 1012                 if ((ifp->if_flags & IFF_UP) != 0) {
 1013                         if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
 1014                                 if (((ifp->if_flags ^ sc->arge_if_flags)
 1015                                     & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
 1016                                         /* XXX: handle promisc & multi flags */
 1017                                 }
 1018                                         
 1019                         } else {
 1020                                 if (!sc->arge_detach)
 1021                                         arge_init_locked(sc);
 1022                         }
 1023                 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
 1024                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
 1025                         arge_stop(sc);
 1026                 }
 1027                 sc->arge_if_flags = ifp->if_flags;
 1028                 ARGE_UNLOCK(sc);
 1029                 error = 0;
 1030                 break;
 1031         case SIOCADDMULTI:
 1032         case SIOCDELMULTI:
 1033                 /* XXX: implement SIOCDELMULTI */
 1034                 error = 0;
 1035                 break;
 1036         case SIOCGIFMEDIA:
 1037         case SIOCSIFMEDIA:
 1038                 if (sc->arge_miibus) {
 1039                         mii = device_get_softc(sc->arge_miibus);
 1040                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
 1041                 }
 1042                 else 
 1043                         error = ifmedia_ioctl(ifp, ifr, &sc->arge_ifmedia, command);
 1044                 break;
 1045         case SIOCSIFCAP:
 1046                 /* XXX: Check other capabilities */
 1047 #ifdef DEVICE_POLLING
 1048                 mask = ifp->if_capenable ^ ifr->ifr_reqcap;
 1049                 if (mask & IFCAP_POLLING) {
 1050                         if (ifr->ifr_reqcap & IFCAP_POLLING) {
 1051                                 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
 1052                                 error = ether_poll_register(arge_poll, ifp);
 1053                                 if (error)
 1054                                         return error;
 1055                                 ARGE_LOCK(sc);
 1056                                 ifp->if_capenable |= IFCAP_POLLING;
 1057                                 ARGE_UNLOCK(sc);
 1058                         } else {
 1059                                 ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
 1060                                 error = ether_poll_deregister(ifp);
 1061                                 ARGE_LOCK(sc);
 1062                                 ifp->if_capenable &= ~IFCAP_POLLING;
 1063                                 ARGE_UNLOCK(sc);
 1064                         }
 1065                 }
 1066                 error = 0;
 1067                 break;
 1068 #endif
 1069         default:
 1070                 error = ether_ioctl(ifp, command, data);
 1071                 break;
 1072         }
 1073 
 1074         return (error);
 1075 }
 1076 
 1077 /*
 1078  * Set media options.
 1079  */
 1080 static int
 1081 arge_ifmedia_upd(struct ifnet *ifp)
 1082 {
 1083         struct arge_softc               *sc;
 1084         struct mii_data         *mii;
 1085         struct mii_softc        *miisc;
 1086         int                     error;
 1087 
 1088         sc = ifp->if_softc;
 1089         ARGE_LOCK(sc);
 1090         mii = device_get_softc(sc->arge_miibus);
 1091         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 1092                 mii_phy_reset(miisc);
 1093         error = mii_mediachg(mii);
 1094         ARGE_UNLOCK(sc);
 1095 
 1096         return (error);
 1097 }
 1098 
 1099 /*
 1100  * Report current media status.
 1101  */
 1102 static void
 1103 arge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
 1104 {
 1105         struct arge_softc               *sc = ifp->if_softc;
 1106         struct mii_data         *mii;
 1107 
 1108         mii = device_get_softc(sc->arge_miibus);
 1109         ARGE_LOCK(sc);
 1110         mii_pollstat(mii);
 1111         ifmr->ifm_active = mii->mii_media_active;
 1112         ifmr->ifm_status = mii->mii_media_status;
 1113         ARGE_UNLOCK(sc);
 1114 }
 1115 
 1116 struct arge_dmamap_arg {
 1117         bus_addr_t      arge_busaddr;
 1118 };
 1119 
 1120 static void
 1121 arge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
 1122 {
 1123         struct arge_dmamap_arg  *ctx;
 1124 
 1125         if (error != 0)
 1126                 return;
 1127         ctx = arg;
 1128         ctx->arge_busaddr = segs[0].ds_addr;
 1129 }
 1130 
 1131 static int
 1132 arge_dma_alloc(struct arge_softc *sc)
 1133 {
 1134         struct arge_dmamap_arg  ctx;
 1135         struct arge_txdesc      *txd;
 1136         struct arge_rxdesc      *rxd;
 1137         int                     error, i;
 1138 
 1139         /* Create parent DMA tag. */
 1140         error = bus_dma_tag_create(
 1141             bus_get_dma_tag(sc->arge_dev),      /* parent */
 1142             1, 0,                       /* alignment, boundary */
 1143             BUS_SPACE_MAXADDR_32BIT,    /* lowaddr */
 1144             BUS_SPACE_MAXADDR,          /* highaddr */
 1145             NULL, NULL,                 /* filter, filterarg */
 1146             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
 1147             0,                          /* nsegments */
 1148             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
 1149             0,                          /* flags */
 1150             NULL, NULL,                 /* lockfunc, lockarg */
 1151             &sc->arge_cdata.arge_parent_tag);
 1152         if (error != 0) {
 1153                 device_printf(sc->arge_dev, "failed to create parent DMA tag\n");
 1154                 goto fail;
 1155         }
 1156         /* Create tag for Tx ring. */
 1157         error = bus_dma_tag_create(
 1158             sc->arge_cdata.arge_parent_tag,     /* parent */
 1159             ARGE_RING_ALIGN, 0,         /* alignment, boundary */
 1160             BUS_SPACE_MAXADDR,          /* lowaddr */
 1161             BUS_SPACE_MAXADDR,          /* highaddr */
 1162             NULL, NULL,                 /* filter, filterarg */
 1163             ARGE_TX_DMA_SIZE,           /* maxsize */
 1164             1,                          /* nsegments */
 1165             ARGE_TX_DMA_SIZE,           /* maxsegsize */
 1166             0,                          /* flags */
 1167             NULL, NULL,                 /* lockfunc, lockarg */
 1168             &sc->arge_cdata.arge_tx_ring_tag);
 1169         if (error != 0) {
 1170                 device_printf(sc->arge_dev, "failed to create Tx ring DMA tag\n");
 1171                 goto fail;
 1172         }
 1173 
 1174         /* Create tag for Rx ring. */
 1175         error = bus_dma_tag_create(
 1176             sc->arge_cdata.arge_parent_tag,     /* parent */
 1177             ARGE_RING_ALIGN, 0,         /* alignment, boundary */
 1178             BUS_SPACE_MAXADDR,          /* lowaddr */
 1179             BUS_SPACE_MAXADDR,          /* highaddr */
 1180             NULL, NULL,                 /* filter, filterarg */
 1181             ARGE_RX_DMA_SIZE,           /* maxsize */
 1182             1,                          /* nsegments */
 1183             ARGE_RX_DMA_SIZE,           /* maxsegsize */
 1184             0,                          /* flags */
 1185             NULL, NULL,                 /* lockfunc, lockarg */
 1186             &sc->arge_cdata.arge_rx_ring_tag);
 1187         if (error != 0) {
 1188                 device_printf(sc->arge_dev, "failed to create Rx ring DMA tag\n");
 1189                 goto fail;
 1190         }
 1191 
 1192         /* Create tag for Tx buffers. */
 1193         error = bus_dma_tag_create(
 1194             sc->arge_cdata.arge_parent_tag,     /* parent */
 1195             sizeof(uint32_t), 0,        /* alignment, boundary */
 1196             BUS_SPACE_MAXADDR,          /* lowaddr */
 1197             BUS_SPACE_MAXADDR,          /* highaddr */
 1198             NULL, NULL,                 /* filter, filterarg */
 1199             MCLBYTES * ARGE_MAXFRAGS,   /* maxsize */
 1200             ARGE_MAXFRAGS,              /* nsegments */
 1201             MCLBYTES,                   /* maxsegsize */
 1202             0,                          /* flags */
 1203             NULL, NULL,                 /* lockfunc, lockarg */
 1204             &sc->arge_cdata.arge_tx_tag);
 1205         if (error != 0) {
 1206                 device_printf(sc->arge_dev, "failed to create Tx DMA tag\n");
 1207                 goto fail;
 1208         }
 1209 
 1210         /* Create tag for Rx buffers. */
 1211         error = bus_dma_tag_create(
 1212             sc->arge_cdata.arge_parent_tag,     /* parent */
 1213             ARGE_RX_ALIGN, 0,           /* alignment, boundary */
 1214             BUS_SPACE_MAXADDR,          /* lowaddr */
 1215             BUS_SPACE_MAXADDR,          /* highaddr */
 1216             NULL, NULL,                 /* filter, filterarg */
 1217             MCLBYTES,                   /* maxsize */
 1218             ARGE_MAXFRAGS,              /* nsegments */
 1219             MCLBYTES,                   /* maxsegsize */
 1220             0,                          /* flags */
 1221             NULL, NULL,                 /* lockfunc, lockarg */
 1222             &sc->arge_cdata.arge_rx_tag);
 1223         if (error != 0) {
 1224                 device_printf(sc->arge_dev, "failed to create Rx DMA tag\n");
 1225                 goto fail;
 1226         }
 1227 
 1228         /* Allocate DMA'able memory and load the DMA map for Tx ring. */
 1229         error = bus_dmamem_alloc(sc->arge_cdata.arge_tx_ring_tag,
 1230             (void **)&sc->arge_rdata.arge_tx_ring, BUS_DMA_WAITOK |
 1231             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->arge_cdata.arge_tx_ring_map);
 1232         if (error != 0) {
 1233                 device_printf(sc->arge_dev,
 1234                     "failed to allocate DMA'able memory for Tx ring\n");
 1235                 goto fail;
 1236         }
 1237 
 1238         ctx.arge_busaddr = 0;
 1239         error = bus_dmamap_load(sc->arge_cdata.arge_tx_ring_tag,
 1240             sc->arge_cdata.arge_tx_ring_map, sc->arge_rdata.arge_tx_ring,
 1241             ARGE_TX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
 1242         if (error != 0 || ctx.arge_busaddr == 0) {
 1243                 device_printf(sc->arge_dev,
 1244                     "failed to load DMA'able memory for Tx ring\n");
 1245                 goto fail;
 1246         }
 1247         sc->arge_rdata.arge_tx_ring_paddr = ctx.arge_busaddr;
 1248 
 1249         /* Allocate DMA'able memory and load the DMA map for Rx ring. */
 1250         error = bus_dmamem_alloc(sc->arge_cdata.arge_rx_ring_tag,
 1251             (void **)&sc->arge_rdata.arge_rx_ring, BUS_DMA_WAITOK |
 1252             BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc->arge_cdata.arge_rx_ring_map);
 1253         if (error != 0) {
 1254                 device_printf(sc->arge_dev,
 1255                     "failed to allocate DMA'able memory for Rx ring\n");
 1256                 goto fail;
 1257         }
 1258 
 1259         ctx.arge_busaddr = 0;
 1260         error = bus_dmamap_load(sc->arge_cdata.arge_rx_ring_tag,
 1261             sc->arge_cdata.arge_rx_ring_map, sc->arge_rdata.arge_rx_ring,
 1262             ARGE_RX_DMA_SIZE, arge_dmamap_cb, &ctx, 0);
 1263         if (error != 0 || ctx.arge_busaddr == 0) {
 1264                 device_printf(sc->arge_dev,
 1265                     "failed to load DMA'able memory for Rx ring\n");
 1266                 goto fail;
 1267         }
 1268         sc->arge_rdata.arge_rx_ring_paddr = ctx.arge_busaddr;
 1269 
 1270         /* Create DMA maps for Tx buffers. */
 1271         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
 1272                 txd = &sc->arge_cdata.arge_txdesc[i];
 1273                 txd->tx_m = NULL;
 1274                 txd->tx_dmamap = NULL;
 1275                 error = bus_dmamap_create(sc->arge_cdata.arge_tx_tag, 0,
 1276                     &txd->tx_dmamap);
 1277                 if (error != 0) {
 1278                         device_printf(sc->arge_dev,
 1279                             "failed to create Tx dmamap\n");
 1280                         goto fail;
 1281                 }
 1282         }
 1283         /* Create DMA maps for Rx buffers. */
 1284         if ((error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
 1285             &sc->arge_cdata.arge_rx_sparemap)) != 0) {
 1286                 device_printf(sc->arge_dev,
 1287                     "failed to create spare Rx dmamap\n");
 1288                 goto fail;
 1289         }
 1290         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
 1291                 rxd = &sc->arge_cdata.arge_rxdesc[i];
 1292                 rxd->rx_m = NULL;
 1293                 rxd->rx_dmamap = NULL;
 1294                 error = bus_dmamap_create(sc->arge_cdata.arge_rx_tag, 0,
 1295                     &rxd->rx_dmamap);
 1296                 if (error != 0) {
 1297                         device_printf(sc->arge_dev,
 1298                             "failed to create Rx dmamap\n");
 1299                         goto fail;
 1300                 }
 1301         }
 1302 
 1303 fail:
 1304         return (error);
 1305 }
 1306 
 1307 static void
 1308 arge_dma_free(struct arge_softc *sc)
 1309 {
 1310         struct arge_txdesc      *txd;
 1311         struct arge_rxdesc      *rxd;
 1312         int                     i;
 1313 
 1314         /* Tx ring. */
 1315         if (sc->arge_cdata.arge_tx_ring_tag) {
 1316                 if (sc->arge_cdata.arge_tx_ring_map)
 1317                         bus_dmamap_unload(sc->arge_cdata.arge_tx_ring_tag,
 1318                             sc->arge_cdata.arge_tx_ring_map);
 1319                 if (sc->arge_cdata.arge_tx_ring_map &&
 1320                     sc->arge_rdata.arge_tx_ring)
 1321                         bus_dmamem_free(sc->arge_cdata.arge_tx_ring_tag,
 1322                             sc->arge_rdata.arge_tx_ring,
 1323                             sc->arge_cdata.arge_tx_ring_map);
 1324                 sc->arge_rdata.arge_tx_ring = NULL;
 1325                 sc->arge_cdata.arge_tx_ring_map = NULL;
 1326                 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_ring_tag);
 1327                 sc->arge_cdata.arge_tx_ring_tag = NULL;
 1328         }
 1329         /* Rx ring. */
 1330         if (sc->arge_cdata.arge_rx_ring_tag) {
 1331                 if (sc->arge_cdata.arge_rx_ring_map)
 1332                         bus_dmamap_unload(sc->arge_cdata.arge_rx_ring_tag,
 1333                             sc->arge_cdata.arge_rx_ring_map);
 1334                 if (sc->arge_cdata.arge_rx_ring_map &&
 1335                     sc->arge_rdata.arge_rx_ring)
 1336                         bus_dmamem_free(sc->arge_cdata.arge_rx_ring_tag,
 1337                             sc->arge_rdata.arge_rx_ring,
 1338                             sc->arge_cdata.arge_rx_ring_map);
 1339                 sc->arge_rdata.arge_rx_ring = NULL;
 1340                 sc->arge_cdata.arge_rx_ring_map = NULL;
 1341                 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_ring_tag);
 1342                 sc->arge_cdata.arge_rx_ring_tag = NULL;
 1343         }
 1344         /* Tx buffers. */
 1345         if (sc->arge_cdata.arge_tx_tag) {
 1346                 for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
 1347                         txd = &sc->arge_cdata.arge_txdesc[i];
 1348                         if (txd->tx_dmamap) {
 1349                                 bus_dmamap_destroy(sc->arge_cdata.arge_tx_tag,
 1350                                     txd->tx_dmamap);
 1351                                 txd->tx_dmamap = NULL;
 1352                         }
 1353                 }
 1354                 bus_dma_tag_destroy(sc->arge_cdata.arge_tx_tag);
 1355                 sc->arge_cdata.arge_tx_tag = NULL;
 1356         }
 1357         /* Rx buffers. */
 1358         if (sc->arge_cdata.arge_rx_tag) {
 1359                 for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
 1360                         rxd = &sc->arge_cdata.arge_rxdesc[i];
 1361                         if (rxd->rx_dmamap) {
 1362                                 bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
 1363                                     rxd->rx_dmamap);
 1364                                 rxd->rx_dmamap = NULL;
 1365                         }
 1366                 }
 1367                 if (sc->arge_cdata.arge_rx_sparemap) {
 1368                         bus_dmamap_destroy(sc->arge_cdata.arge_rx_tag,
 1369                             sc->arge_cdata.arge_rx_sparemap);
 1370                         sc->arge_cdata.arge_rx_sparemap = 0;
 1371                 }
 1372                 bus_dma_tag_destroy(sc->arge_cdata.arge_rx_tag);
 1373                 sc->arge_cdata.arge_rx_tag = NULL;
 1374         }
 1375 
 1376         if (sc->arge_cdata.arge_parent_tag) {
 1377                 bus_dma_tag_destroy(sc->arge_cdata.arge_parent_tag);
 1378                 sc->arge_cdata.arge_parent_tag = NULL;
 1379         }
 1380 }
 1381 
 1382 /*
 1383  * Initialize the transmit descriptors.
 1384  */
 1385 static int
 1386 arge_tx_ring_init(struct arge_softc *sc)
 1387 {
 1388         struct arge_ring_data   *rd;
 1389         struct arge_txdesc      *txd;
 1390         bus_addr_t              addr;
 1391         int                     i;
 1392 
 1393         sc->arge_cdata.arge_tx_prod = 0;
 1394         sc->arge_cdata.arge_tx_cons = 0;
 1395         sc->arge_cdata.arge_tx_cnt = 0;
 1396         sc->arge_cdata.arge_tx_pkts = 0;
 1397 
 1398         rd = &sc->arge_rdata;
 1399         bzero(rd->arge_tx_ring, sizeof(rd->arge_tx_ring));
 1400         for (i = 0; i < ARGE_TX_RING_COUNT; i++) {
 1401                 if (i == ARGE_TX_RING_COUNT - 1)
 1402                         addr = ARGE_TX_RING_ADDR(sc, 0);
 1403                 else
 1404                         addr = ARGE_TX_RING_ADDR(sc, i + 1);
 1405                 rd->arge_tx_ring[i].packet_ctrl = ARGE_DESC_EMPTY;
 1406                 rd->arge_tx_ring[i].next_desc = addr;
 1407                 txd = &sc->arge_cdata.arge_txdesc[i];
 1408                 txd->tx_m = NULL;
 1409         }
 1410 
 1411         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
 1412             sc->arge_cdata.arge_tx_ring_map,
 1413             BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
 1414 
 1415         return (0);
 1416 }
 1417 
 1418 /*
 1419  * Initialize the RX descriptors and allocate mbufs for them. Note that
 1420  * we arrange the descriptors in a closed ring, so that the last descriptor
 1421  * points back to the first.
 1422  */
 1423 static int
 1424 arge_rx_ring_init(struct arge_softc *sc)
 1425 {
 1426         struct arge_ring_data   *rd;
 1427         struct arge_rxdesc      *rxd;
 1428         bus_addr_t              addr;
 1429         int                     i;
 1430 
 1431         sc->arge_cdata.arge_rx_cons = 0;
 1432 
 1433         rd = &sc->arge_rdata;
 1434         bzero(rd->arge_rx_ring, sizeof(rd->arge_rx_ring));
 1435         for (i = 0; i < ARGE_RX_RING_COUNT; i++) {
 1436                 rxd = &sc->arge_cdata.arge_rxdesc[i];
 1437                 rxd->rx_m = NULL;
 1438                 rxd->desc = &rd->arge_rx_ring[i];
 1439                 if (i == ARGE_RX_RING_COUNT - 1)
 1440                         addr = ARGE_RX_RING_ADDR(sc, 0);
 1441                 else
 1442                         addr = ARGE_RX_RING_ADDR(sc, i + 1);
 1443                 rd->arge_rx_ring[i].next_desc = addr;
 1444                 if (arge_newbuf(sc, i) != 0) {
 1445                         return (ENOBUFS);
 1446                 }
 1447         }
 1448 
 1449         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
 1450             sc->arge_cdata.arge_rx_ring_map,
 1451             BUS_DMASYNC_PREWRITE);
 1452 
 1453         return (0);
 1454 }
 1455 
 1456 /*
 1457  * Initialize an RX descriptor and attach an MBUF cluster.
 1458  */
 1459 static int
 1460 arge_newbuf(struct arge_softc *sc, int idx)
 1461 {
 1462         struct arge_desc                *desc;
 1463         struct arge_rxdesc      *rxd;
 1464         struct mbuf             *m;
 1465         bus_dma_segment_t       segs[1];
 1466         bus_dmamap_t            map;
 1467         int                     nsegs;
 1468 
 1469         m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
 1470         if (m == NULL)
 1471                 return (ENOBUFS);
 1472         m->m_len = m->m_pkthdr.len = MCLBYTES;
 1473         m_adj(m, sizeof(uint64_t));
 1474 
 1475         if (bus_dmamap_load_mbuf_sg(sc->arge_cdata.arge_rx_tag,
 1476             sc->arge_cdata.arge_rx_sparemap, m, segs, &nsegs, 0) != 0) {
 1477                 m_freem(m);
 1478                 return (ENOBUFS);
 1479         }
 1480         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 1481 
 1482         rxd = &sc->arge_cdata.arge_rxdesc[idx];
 1483         if (rxd->rx_m != NULL) {
 1484                 bus_dmamap_unload(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap);
 1485         }
 1486         map = rxd->rx_dmamap;
 1487         rxd->rx_dmamap = sc->arge_cdata.arge_rx_sparemap;
 1488         sc->arge_cdata.arge_rx_sparemap = map;
 1489         rxd->rx_m = m;
 1490         desc = rxd->desc;
 1491         if (segs[0].ds_addr & 3)
 1492                 panic("RX packet address unaligned");
 1493         desc->packet_addr = segs[0].ds_addr;
 1494         desc->packet_ctrl = ARGE_DESC_EMPTY | ARGE_DMASIZE(segs[0].ds_len);
 1495 
 1496         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
 1497             sc->arge_cdata.arge_rx_ring_map,
 1498             BUS_DMASYNC_PREWRITE);
 1499 
 1500         return (0);
 1501 }
 1502 
 1503 static __inline void
 1504 arge_fixup_rx(struct mbuf *m)
 1505 {
 1506         int             i;
 1507         uint16_t        *src, *dst;
 1508 
 1509         src = mtod(m, uint16_t *);
 1510         dst = src - 1;
 1511 
 1512         for (i = 0; i < m->m_len / sizeof(uint16_t); i++) {
 1513                 *dst++ = *src++;
 1514         }
 1515 
 1516         if (m->m_len % sizeof(uint16_t))
 1517                 *(uint8_t *)dst = *(uint8_t *)src;
 1518 
 1519         m->m_data -= ETHER_ALIGN;
 1520 }
 1521 
 1522 #ifdef DEVICE_POLLING
 1523 static int
 1524 arge_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
 1525 {
 1526         struct arge_softc *sc = ifp->if_softc;
 1527         int rx_npkts = 0;
 1528 
 1529         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
 1530                 ARGE_LOCK(sc);
 1531                 arge_tx_locked(sc);
 1532                 rx_npkts = arge_rx_locked(sc);
 1533                 ARGE_UNLOCK(sc);
 1534         }
 1535 
 1536         return (rx_npkts);
 1537 }
 1538 #endif /* DEVICE_POLLING */
 1539 
 1540 
 1541 static void
 1542 arge_tx_locked(struct arge_softc *sc)
 1543 {
 1544         struct arge_txdesc      *txd;
 1545         struct arge_desc        *cur_tx;
 1546         struct ifnet            *ifp;
 1547         uint32_t                ctrl;
 1548         int                     cons, prod;
 1549 
 1550         ARGE_LOCK_ASSERT(sc);
 1551 
 1552         cons = sc->arge_cdata.arge_tx_cons;
 1553         prod = sc->arge_cdata.arge_tx_prod;
 1554         if (cons == prod)
 1555                 return;
 1556 
 1557         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
 1558             sc->arge_cdata.arge_tx_ring_map,
 1559             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 1560 
 1561         ifp = sc->arge_ifp;
 1562         /*
 1563          * Go through our tx list and free mbufs for those
 1564          * frames that have been transmitted.
 1565          */
 1566         for (; cons != prod; ARGE_INC(cons, ARGE_TX_RING_COUNT)) {
 1567                 cur_tx = &sc->arge_rdata.arge_tx_ring[cons];
 1568                 ctrl = cur_tx->packet_ctrl;
 1569                 /* Check if descriptor has "finished" flag */
 1570                 if ((ctrl & ARGE_DESC_EMPTY) == 0)
 1571                         break;
 1572 
 1573                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_PKT_SENT);
 1574 
 1575                 sc->arge_cdata.arge_tx_cnt--;
 1576                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
 1577 
 1578                 txd = &sc->arge_cdata.arge_txdesc[cons];
 1579 
 1580                 ifp->if_opackets++;
 1581 
 1582                 bus_dmamap_sync(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap,
 1583                     BUS_DMASYNC_POSTWRITE);
 1584                 bus_dmamap_unload(sc->arge_cdata.arge_tx_tag, txd->tx_dmamap);
 1585 
 1586                 /* Free only if it's first descriptor in list */
 1587                 if (txd->tx_m)
 1588                         m_freem(txd->tx_m);
 1589                 txd->tx_m = NULL;
 1590 
 1591                 /* reset descriptor */
 1592                 cur_tx->packet_addr = 0;
 1593         }
 1594 
 1595         sc->arge_cdata.arge_tx_cons = cons;
 1596 
 1597         bus_dmamap_sync(sc->arge_cdata.arge_tx_ring_tag,
 1598             sc->arge_cdata.arge_tx_ring_map, BUS_DMASYNC_PREWRITE);
 1599 }
 1600 
 1601 
 1602 static int
 1603 arge_rx_locked(struct arge_softc *sc)
 1604 {
 1605         struct arge_rxdesc      *rxd;
 1606         struct ifnet            *ifp = sc->arge_ifp;
 1607         int                     cons, prog, packet_len, i;
 1608         struct arge_desc        *cur_rx;
 1609         struct mbuf             *m;
 1610         int                     rx_npkts = 0;
 1611 
 1612         ARGE_LOCK_ASSERT(sc);
 1613 
 1614         cons = sc->arge_cdata.arge_rx_cons;
 1615 
 1616         bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
 1617             sc->arge_cdata.arge_rx_ring_map,
 1618             BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 1619 
 1620         for (prog = 0; prog < ARGE_RX_RING_COUNT; 
 1621             ARGE_INC(cons, ARGE_RX_RING_COUNT)) {
 1622                 cur_rx = &sc->arge_rdata.arge_rx_ring[cons];
 1623                 rxd = &sc->arge_cdata.arge_rxdesc[cons];
 1624                 m = rxd->rx_m;
 1625 
 1626                 if ((cur_rx->packet_ctrl & ARGE_DESC_EMPTY) != 0)
 1627                        break;   
 1628 
 1629                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_PKT_RECVD);
 1630 
 1631                 prog++;
 1632 
 1633                 packet_len = ARGE_DMASIZE(cur_rx->packet_ctrl);
 1634                 bus_dmamap_sync(sc->arge_cdata.arge_rx_tag, rxd->rx_dmamap,
 1635                     BUS_DMASYNC_POSTREAD);
 1636                 m = rxd->rx_m;
 1637 
 1638                 arge_fixup_rx(m);
 1639                 m->m_pkthdr.rcvif = ifp;
 1640                 /* Skip 4 bytes of CRC */
 1641                 m->m_pkthdr.len = m->m_len = packet_len - ETHER_CRC_LEN;
 1642                 ifp->if_ipackets++;
 1643                 rx_npkts++;
 1644 
 1645                 ARGE_UNLOCK(sc);
 1646                 (*ifp->if_input)(ifp, m);
 1647                 ARGE_LOCK(sc);
 1648                 cur_rx->packet_addr = 0;
 1649         }
 1650 
 1651         if (prog > 0) {
 1652 
 1653                 i = sc->arge_cdata.arge_rx_cons;
 1654                 for (; prog > 0 ; prog--) {
 1655                         if (arge_newbuf(sc, i) != 0) {
 1656                                 device_printf(sc->arge_dev, 
 1657                                     "Failed to allocate buffer\n");
 1658                                 break;
 1659                         }
 1660                         ARGE_INC(i, ARGE_RX_RING_COUNT);
 1661                 }
 1662 
 1663                 bus_dmamap_sync(sc->arge_cdata.arge_rx_ring_tag,
 1664                     sc->arge_cdata.arge_rx_ring_map,
 1665                     BUS_DMASYNC_PREWRITE);
 1666 
 1667                 sc->arge_cdata.arge_rx_cons = cons;
 1668         }
 1669 
 1670         return (rx_npkts);
 1671 }
 1672 
 1673 static int
 1674 arge_intr_filter(void *arg)
 1675 {
 1676         struct arge_softc       *sc = arg;
 1677         uint32_t                status, ints;
 1678 
 1679         status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
 1680         ints = ARGE_READ(sc, AR71XX_DMA_INTR);
 1681 
 1682 #if 0
 1683         dprintf("int mask(filter) = %b\n", ints,
 1684             "\2\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
 1685             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
 1686         dprintf("status(filter) = %b\n", status, 
 1687             "\2\10RX_BUS_ERROR\7RX_OVERFLOW\5RX_PKT_RCVD"
 1688             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
 1689 #endif
 1690 
 1691         if (status & DMA_INTR_ALL) {
 1692                 sc->arge_intr_status |= status;
 1693                 ARGE_WRITE(sc, AR71XX_DMA_INTR, 0);
 1694                 return (FILTER_SCHEDULE_THREAD);
 1695         } 
 1696 
 1697         sc->arge_intr_status = 0;
 1698         return (FILTER_STRAY);
 1699 }
 1700 
 1701 static void
 1702 arge_intr(void *arg)
 1703 {
 1704         struct arge_softc       *sc = arg;
 1705         uint32_t                status;
 1706 
 1707         status = ARGE_READ(sc, AR71XX_DMA_INTR_STATUS);
 1708         status |= sc->arge_intr_status;
 1709 
 1710 #if 0
 1711         dprintf("int status(intr) = %b\n", status, 
 1712             "\2\1\7RX_OVERFLOW\5RX_PKT_RCVD"
 1713             "\4TX_BUS_ERROR\2TX_UNDERRUN\1TX_PKT_SENT");
 1714 #endif
 1715 
 1716         /* 
 1717          * Is it our interrupt at all? 
 1718          */
 1719         if (status == 0)
 1720                 return;
 1721 
 1722         if (status & DMA_INTR_RX_BUS_ERROR) {
 1723                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_BUS_ERROR);
 1724                 device_printf(sc->arge_dev, "RX bus error");
 1725                 return;
 1726         }
 1727 
 1728         if (status & DMA_INTR_TX_BUS_ERROR) {
 1729                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_BUS_ERROR);
 1730                 device_printf(sc->arge_dev, "TX bus error");
 1731                 return;
 1732         }
 1733 
 1734         ARGE_LOCK(sc);
 1735 
 1736         if (status & DMA_INTR_RX_PKT_RCVD)
 1737                 arge_rx_locked(sc);
 1738 
 1739         /* 
 1740          * RX overrun disables the receiver. 
 1741          * Clear indication and re-enable rx. 
 1742          */
 1743         if ( status & DMA_INTR_RX_OVERFLOW) {
 1744                 ARGE_WRITE(sc, AR71XX_DMA_RX_STATUS, DMA_RX_STATUS_OVERFLOW);
 1745                 ARGE_WRITE(sc, AR71XX_DMA_RX_CONTROL, DMA_RX_CONTROL_EN);
 1746         }
 1747 
 1748         if (status & DMA_INTR_TX_PKT_SENT)
 1749                 arge_tx_locked(sc);
 1750         /* 
 1751          * Underrun turns off TX. Clear underrun indication. 
 1752          * If there's anything left in the ring, reactivate the tx. 
 1753          */
 1754         if (status & DMA_INTR_TX_UNDERRUN) {
 1755                 ARGE_WRITE(sc, AR71XX_DMA_TX_STATUS, DMA_TX_STATUS_UNDERRUN);
 1756                 if (sc->arge_cdata.arge_tx_pkts > 0 ) {
 1757                         ARGE_WRITE(sc, AR71XX_DMA_TX_CONTROL, 
 1758                             DMA_TX_CONTROL_EN);
 1759                 }
 1760         }
 1761 
 1762         /*
 1763          * We handled all bits, clear status
 1764          */
 1765         sc->arge_intr_status = 0;
 1766         ARGE_UNLOCK(sc);
 1767         /*
 1768          * re-enable all interrupts 
 1769          */
 1770         ARGE_WRITE(sc, AR71XX_DMA_INTR, DMA_INTR_ALL);
 1771 }
 1772 
 1773 
 1774 static void
 1775 arge_tick(void *xsc)
 1776 {
 1777         struct arge_softc       *sc = xsc;
 1778         struct mii_data         *mii;
 1779 
 1780         ARGE_LOCK_ASSERT(sc);
 1781 
 1782         if (sc->arge_miibus) {
 1783                 mii = device_get_softc(sc->arge_miibus);
 1784                 mii_tick(mii);
 1785                 callout_reset(&sc->arge_stat_callout, hz, arge_tick, sc);
 1786         }
 1787 }
 1788 
 1789 int
 1790 arge_multiphy_mediachange(struct ifnet *ifp)
 1791 {
 1792         struct arge_softc *sc = ifp->if_softc;
 1793         struct ifmedia *ifm = &sc->arge_ifmedia;
 1794         struct ifmedia_entry *ife = ifm->ifm_cur;
 1795 
 1796         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
 1797                 return (EINVAL);
 1798 
 1799         if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO) {
 1800                 device_printf(sc->arge_dev, 
 1801                     "AUTO is not supported for multiphy MAC");
 1802                 return (EINVAL);
 1803         }
 1804 
 1805         /*
 1806          * Ignore everything
 1807          */
 1808         return (0);
 1809 }
 1810 
 1811 void
 1812 arge_multiphy_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 1813 {
 1814         struct arge_softc *sc = ifp->if_softc;
 1815 
 1816         ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE;
 1817         ifmr->ifm_active = IFM_ETHER | sc->arge_media_type | 
 1818             sc->arge_duplex_mode;
 1819 }
 1820 

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