The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/if_argevar.h

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    1 /*-
    2  * Copyright (c) 2009, Oleksandr Tymoshenko
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice unmodified, this list of conditions, and the following
   10  *    disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * $FreeBSD: releng/11.2/sys/mips/atheros/if_argevar.h 331722 2018-03-29 02:50:57Z eadler $
   28  */
   29 
   30 #ifndef __IF_ARGEVAR_H__
   31 #define __IF_ARGEVAR_H__
   32 
   33 #define ARGE_NPHY               32
   34 #define ARGE_TX_RING_COUNT      128
   35 #define ARGE_RX_RING_COUNT      128
   36 #define ARGE_RX_DMA_SIZE        ARGE_RX_RING_COUNT * sizeof(struct arge_desc)
   37 #define ARGE_TX_DMA_SIZE        ARGE_TX_RING_COUNT * sizeof(struct arge_desc)
   38 #define ARGE_MAXFRAGS           8
   39 #define ARGE_RING_ALIGN         sizeof(struct arge_desc)
   40 #define ARGE_RX_ALIGN_4BYTE     sizeof(uint32_t)
   41 #define ARGE_RX_ALIGN_1BYTE     sizeof(char)
   42 #define ARGE_TX_ALIGN_4BYTE     sizeof(uint32_t)
   43 #define ARGE_TX_ALIGN_1BYTE     sizeof(char)
   44 #define ARGE_MAXFRAGS           8
   45 #define ARGE_TX_RING_ADDR(sc, i)        \
   46     ((sc)->arge_rdata.arge_tx_ring_paddr + sizeof(struct arge_desc) * (i))
   47 #define ARGE_RX_RING_ADDR(sc, i)        \
   48     ((sc)->arge_rdata.arge_rx_ring_paddr + sizeof(struct arge_desc) * (i))
   49 #define ARGE_INC(x,y)           (x) = (((x) + 1) % y)
   50 
   51 
   52 #define ARGE_MII_TIMEOUT        1000
   53 
   54 #define ARGE_LOCK(_sc)          mtx_lock(&(_sc)->arge_mtx)
   55 #define ARGE_UNLOCK(_sc)        mtx_unlock(&(_sc)->arge_mtx)
   56 #define ARGE_LOCK_ASSERT(_sc)   mtx_assert(&(_sc)->arge_mtx, MA_OWNED)
   57 
   58 /*
   59  * register space access macros
   60  */
   61 #define ARGE_BARRIER_READ(sc)   bus_barrier(sc->arge_res, 0, 0, \
   62                                     BUS_SPACE_BARRIER_READ)
   63 #define ARGE_BARRIER_WRITE(sc)  bus_barrier(sc->arge_res, 0, 0, \
   64                                     BUS_SPACE_BARRIER_WRITE)
   65 #define ARGE_BARRIER_RW(sc)     bus_barrier(sc->arge_res, 0, 0, \
   66                                     BUS_SPACE_BARRIER_READ | \
   67                                     BUS_SPACE_BARRIER_WRITE)
   68 #define ARGE_WRITE(sc, reg, val)        do {    \
   69                 bus_write_4(sc->arge_res, (reg), (val)); \
   70                 ARGE_BARRIER_WRITE((sc)); \
   71                 ARGE_READ((sc), (reg)); \
   72         } while (0)
   73 #define ARGE_READ(sc, reg)       bus_read_4(sc->arge_res, (reg))
   74 
   75 #define ARGE_SET_BITS(sc, reg, bits)    \
   76         ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) | (bits))
   77 
   78 #define ARGE_CLEAR_BITS(sc, reg, bits)  \
   79         ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) & ~(bits))
   80 
   81 /*
   82  * The linux driver code for the MDIO bus does a read-after-write
   83  * which seems to be required on MIPS74k platforms for correct
   84  * behaviour.
   85  *
   86  * So, ARGE_WRITE() does the write + barrier, and the following
   87  * ARGE_READ() seems to flush the thing all the way through the device
   88  * FIFO(s) before we continue issuing MDIO bus updates.
   89  */
   90 #define ARGE_MDIO_WRITE(_sc, _reg, _val) \
   91         ARGE_WRITE((_sc), (_reg), (_val))
   92 #define ARGE_MDIO_READ(_sc, _reg)       \
   93         ARGE_READ((_sc), (_reg))
   94 #define ARGE_MDIO_BARRIER_READ(_sc)     ARGE_BARRIER_READ(_sc)
   95 #define ARGE_MDIO_BARRIER_WRITE(_sc)    ARGE_BARRIER_WRITE(_sc)
   96 #define ARGE_MDIO_BARRIER_RW(_sc)       ARGE_BARRIER_RW(_sc)
   97 
   98 #define ARGE_DESC_EMPTY         (1U << 31)
   99 #define ARGE_DESC_MORE          (1 << 24)
  100 #define ARGE_DESC_SIZE_MASK     ((1 << 12) - 1)
  101 #define ARGE_DMASIZE(len)       ((len) & ARGE_DESC_SIZE_MASK)
  102 struct arge_desc {
  103         uint32_t        packet_addr;
  104         uint32_t        packet_ctrl;
  105         uint32_t        next_desc;
  106         uint32_t        padding;
  107 };
  108 
  109 struct arge_txdesc {
  110         struct mbuf     *tx_m;
  111         bus_dmamap_t    tx_dmamap;
  112 };
  113 
  114 struct arge_rxdesc {
  115         struct mbuf             *rx_m;
  116         bus_dmamap_t            rx_dmamap;
  117         struct arge_desc        *desc;
  118 };
  119 
  120 struct arge_chain_data {
  121         bus_dma_tag_t           arge_parent_tag;
  122         bus_dma_tag_t           arge_tx_tag;
  123         struct arge_txdesc      arge_txdesc[ARGE_TX_RING_COUNT];
  124         bus_dma_tag_t           arge_rx_tag;
  125         struct arge_rxdesc      arge_rxdesc[ARGE_RX_RING_COUNT];
  126         bus_dma_tag_t           arge_tx_ring_tag;
  127         bus_dma_tag_t           arge_rx_ring_tag;
  128         bus_dmamap_t            arge_tx_ring_map;
  129         bus_dmamap_t            arge_rx_ring_map;
  130         bus_dmamap_t            arge_rx_sparemap;
  131         int                     arge_tx_prod;
  132         int                     arge_tx_cons;
  133         int                     arge_tx_cnt;
  134         int                     arge_rx_cons;
  135 };
  136 
  137 struct arge_ring_data {
  138         struct arge_desc        *arge_rx_ring;
  139         struct arge_desc        *arge_tx_ring;
  140         bus_addr_t              arge_rx_ring_paddr;
  141         bus_addr_t              arge_tx_ring_paddr;
  142 };
  143 
  144 /*
  145  * Allow PLL values to be overridden.
  146  */
  147 struct arge_pll_data {
  148         uint32_t pll_10;
  149         uint32_t pll_100;
  150         uint32_t pll_1000;
  151 };
  152 
  153 /*
  154  * Hardware specific behaviours.
  155  */
  156 
  157 /*
  158  * Older chips support 4 byte only transmit and receive
  159  * addresses.
  160  *
  161  * Later chips support arbitrary TX and later later,
  162  * arbitrary RX addresses.
  163  */
  164 #define ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE 0x00000001
  165 #define ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE 0x00000002
  166 #define ARGE_HW_FLG_TX_DESC_ALIGN_1BYTE 0x00000004
  167 #define ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE 0x00000008
  168 
  169 struct arge_softc {
  170         struct ifnet            *arge_ifp;      /* interface info */
  171         device_t                arge_dev;
  172         struct ifmedia          arge_ifmedia;
  173         /*
  174          * Media & duples settings for multiPHY MAC
  175          */
  176         uint32_t                arge_media_type;
  177         uint32_t                arge_duplex_mode;
  178         uint32_t                arge_phymask;
  179         uint8_t                 arge_eaddr[ETHER_ADDR_LEN];
  180         struct resource         *arge_res;
  181         int                     arge_rid;
  182         struct resource         *arge_irq;
  183         void                    *arge_intrhand;
  184         device_t                arge_miibus;
  185         device_t                arge_miiproxy;
  186         ar71xx_mii_mode         arge_miicfg;
  187         struct arge_pll_data    arge_pllcfg;
  188         bus_dma_tag_t           arge_parent_tag;
  189         bus_dma_tag_t           arge_tag;
  190         struct mtx              arge_mtx;
  191         struct callout          arge_stat_callout;
  192         struct task             arge_link_task;
  193         struct arge_chain_data  arge_cdata;
  194         struct arge_ring_data   arge_rdata;
  195         int                     arge_link_status;
  196         int                     arge_detach;
  197         uint32_t                arge_intr_status;
  198         int                     arge_mac_unit;
  199         int                     arge_if_flags;
  200         uint32_t                arge_hw_flags;
  201         uint32_t                arge_debug;
  202         uint32_t                arge_mdiofreq;
  203         struct {
  204                 uint32_t        tx_pkts_unaligned;
  205                 uint32_t        tx_pkts_unaligned_start;
  206                 uint32_t        tx_pkts_unaligned_len;
  207                 uint32_t        tx_pkts_nosegs;
  208                 uint32_t        tx_pkts_aligned;
  209                 uint32_t        rx_overflow;
  210                 uint32_t        tx_underflow;
  211                 uint32_t        intr_stray;
  212                 uint32_t        intr_stray2;
  213                 uint32_t        intr_ok;
  214         } stats;
  215         struct {
  216                 uint32_t        count[32];
  217         } intr_stats;
  218 };
  219 
  220 #endif /* __IF_ARGEVAR_H__ */

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