1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2009, Oleksandr Tymoshenko
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
12 * disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD$
30 */
31
32 #ifndef __IF_ARGEVAR_H__
33 #define __IF_ARGEVAR_H__
34
35 #define ARGE_NPHY 32
36 #define ARGE_TX_RING_COUNT 128
37 #define ARGE_RX_RING_COUNT 128
38 #define ARGE_RX_DMA_SIZE ARGE_RX_RING_COUNT * sizeof(struct arge_desc)
39 #define ARGE_TX_DMA_SIZE ARGE_TX_RING_COUNT * sizeof(struct arge_desc)
40 #define ARGE_MAXFRAGS 8
41 #define ARGE_RING_ALIGN sizeof(struct arge_desc)
42 #define ARGE_RX_ALIGN_4BYTE sizeof(uint32_t)
43 #define ARGE_RX_ALIGN_1BYTE sizeof(char)
44 #define ARGE_TX_ALIGN_4BYTE sizeof(uint32_t)
45 #define ARGE_TX_ALIGN_1BYTE sizeof(char)
46 #define ARGE_MAXFRAGS 8
47 #define ARGE_TX_RING_ADDR(sc, i) \
48 ((sc)->arge_rdata.arge_tx_ring_paddr + sizeof(struct arge_desc) * (i))
49 #define ARGE_RX_RING_ADDR(sc, i) \
50 ((sc)->arge_rdata.arge_rx_ring_paddr + sizeof(struct arge_desc) * (i))
51 #define ARGE_INC(x,y) (x) = (((x) + 1) % y)
52
53
54 #define ARGE_MII_TIMEOUT 1000
55
56 #define ARGE_LOCK(_sc) mtx_lock(&(_sc)->arge_mtx)
57 #define ARGE_UNLOCK(_sc) mtx_unlock(&(_sc)->arge_mtx)
58 #define ARGE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->arge_mtx, MA_OWNED)
59
60 /*
61 * register space access macros
62 */
63 #define ARGE_BARRIER_READ(sc) bus_barrier(sc->arge_res, 0, 0, \
64 BUS_SPACE_BARRIER_READ)
65 #define ARGE_BARRIER_WRITE(sc) bus_barrier(sc->arge_res, 0, 0, \
66 BUS_SPACE_BARRIER_WRITE)
67 #define ARGE_BARRIER_RW(sc) bus_barrier(sc->arge_res, 0, 0, \
68 BUS_SPACE_BARRIER_READ | \
69 BUS_SPACE_BARRIER_WRITE)
70 #define ARGE_WRITE(sc, reg, val) do { \
71 bus_write_4(sc->arge_res, (reg), (val)); \
72 ARGE_BARRIER_WRITE((sc)); \
73 ARGE_READ((sc), (reg)); \
74 } while (0)
75 #define ARGE_READ(sc, reg) bus_read_4(sc->arge_res, (reg))
76
77 #define ARGE_SET_BITS(sc, reg, bits) \
78 ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) | (bits))
79
80 #define ARGE_CLEAR_BITS(sc, reg, bits) \
81 ARGE_WRITE(sc, reg, ARGE_READ(sc, (reg)) & ~(bits))
82
83 /*
84 * The linux driver code for the MDIO bus does a read-after-write
85 * which seems to be required on MIPS74k platforms for correct
86 * behaviour.
87 *
88 * So, ARGE_WRITE() does the write + barrier, and the following
89 * ARGE_READ() seems to flush the thing all the way through the device
90 * FIFO(s) before we continue issuing MDIO bus updates.
91 */
92 #define ARGE_MDIO_WRITE(_sc, _reg, _val) \
93 ARGE_WRITE((_sc), (_reg), (_val))
94 #define ARGE_MDIO_READ(_sc, _reg) \
95 ARGE_READ((_sc), (_reg))
96 #define ARGE_MDIO_BARRIER_READ(_sc) ARGE_BARRIER_READ(_sc)
97 #define ARGE_MDIO_BARRIER_WRITE(_sc) ARGE_BARRIER_WRITE(_sc)
98 #define ARGE_MDIO_BARRIER_RW(_sc) ARGE_BARRIER_RW(_sc)
99
100 #define ARGE_DESC_EMPTY (1U << 31)
101 #define ARGE_DESC_MORE (1 << 24)
102 #define ARGE_DESC_SIZE_MASK ((1 << 12) - 1)
103 #define ARGE_DMASIZE(len) ((len) & ARGE_DESC_SIZE_MASK)
104 struct arge_desc {
105 uint32_t packet_addr;
106 uint32_t packet_ctrl;
107 uint32_t next_desc;
108 uint32_t padding;
109 };
110
111 struct arge_txdesc {
112 struct mbuf *tx_m;
113 bus_dmamap_t tx_dmamap;
114 };
115
116 struct arge_rxdesc {
117 struct mbuf *rx_m;
118 bus_dmamap_t rx_dmamap;
119 struct arge_desc *desc;
120 };
121
122 struct arge_chain_data {
123 bus_dma_tag_t arge_parent_tag;
124 bus_dma_tag_t arge_tx_tag;
125 struct arge_txdesc arge_txdesc[ARGE_TX_RING_COUNT];
126 bus_dma_tag_t arge_rx_tag;
127 struct arge_rxdesc arge_rxdesc[ARGE_RX_RING_COUNT];
128 bus_dma_tag_t arge_tx_ring_tag;
129 bus_dma_tag_t arge_rx_ring_tag;
130 bus_dmamap_t arge_tx_ring_map;
131 bus_dmamap_t arge_rx_ring_map;
132 bus_dmamap_t arge_rx_sparemap;
133 int arge_tx_prod;
134 int arge_tx_cons;
135 int arge_tx_cnt;
136 int arge_rx_cons;
137 };
138
139 struct arge_ring_data {
140 struct arge_desc *arge_rx_ring;
141 struct arge_desc *arge_tx_ring;
142 bus_addr_t arge_rx_ring_paddr;
143 bus_addr_t arge_tx_ring_paddr;
144 };
145
146 /*
147 * Allow PLL values to be overridden.
148 */
149 struct arge_pll_data {
150 uint32_t pll_10;
151 uint32_t pll_100;
152 uint32_t pll_1000;
153 };
154
155 /*
156 * Hardware specific behaviours.
157 */
158
159 /*
160 * Older chips support 4 byte only transmit and receive
161 * addresses.
162 *
163 * Later chips support arbitrary TX and later later,
164 * arbitrary RX addresses.
165 */
166 #define ARGE_HW_FLG_TX_DESC_ALIGN_4BYTE 0x00000001
167 #define ARGE_HW_FLG_RX_DESC_ALIGN_4BYTE 0x00000002
168 #define ARGE_HW_FLG_TX_DESC_ALIGN_1BYTE 0x00000004
169 #define ARGE_HW_FLG_RX_DESC_ALIGN_1BYTE 0x00000008
170
171 struct arge_softc {
172 struct ifnet *arge_ifp; /* interface info */
173 device_t arge_dev;
174 struct ifmedia arge_ifmedia;
175 /*
176 * Media & duples settings for multiPHY MAC
177 */
178 uint32_t arge_media_type;
179 uint32_t arge_duplex_mode;
180 uint32_t arge_phymask;
181 uint8_t arge_eaddr[ETHER_ADDR_LEN];
182 struct resource *arge_res;
183 int arge_rid;
184 struct resource *arge_irq;
185 void *arge_intrhand;
186 device_t arge_miibus;
187 device_t arge_miiproxy;
188 ar71xx_mii_mode arge_miicfg;
189 struct arge_pll_data arge_pllcfg;
190 bus_dma_tag_t arge_parent_tag;
191 bus_dma_tag_t arge_tag;
192 struct mtx arge_mtx;
193 struct callout arge_stat_callout;
194 struct task arge_link_task;
195 struct arge_chain_data arge_cdata;
196 struct arge_ring_data arge_rdata;
197 int arge_link_status;
198 int arge_detach;
199 uint32_t arge_intr_status;
200 int arge_mac_unit;
201 int arge_if_flags;
202 uint32_t arge_hw_flags;
203 uint32_t arge_debug;
204 uint32_t arge_mdiofreq;
205 struct {
206 uint32_t tx_pkts_unaligned;
207 uint32_t tx_pkts_unaligned_start;
208 uint32_t tx_pkts_unaligned_len;
209 uint32_t tx_pkts_nosegs;
210 uint32_t tx_pkts_aligned;
211 uint32_t rx_overflow;
212 uint32_t tx_underflow;
213 uint32_t intr_stray;
214 uint32_t intr_stray2;
215 uint32_t intr_ok;
216 } stats;
217 struct {
218 uint32_t count[32];
219 } intr_stats;
220 };
221
222 #endif /* __IF_ARGEVAR_H__ */
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