The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/atheros/qca953x_chip.c

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    1 /*-
    2  * Copyright (c) 2015 Adrian Chadd <adrian@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: stable/12/sys/mips/atheros/qca953x_chip.c 298848 2016-04-30 14:41:18Z pfg $");
   29 
   30 #include "opt_ddb.h"
   31 
   32 #include <sys/param.h>
   33 #include <sys/conf.h>
   34 #include <sys/kernel.h>
   35 #include <sys/systm.h>
   36 #include <sys/bus.h>
   37 #include <sys/cons.h>
   38 #include <sys/kdb.h>
   39 #include <sys/reboot.h>
   40 
   41 #include <vm/vm.h>
   42 #include <vm/vm_page.h>
   43 
   44 #include <net/ethernet.h>
   45 
   46 #include <machine/clock.h>
   47 #include <machine/cpu.h>
   48 #include <machine/cpuregs.h>
   49 #include <machine/hwfunc.h>
   50 #include <machine/md_var.h>
   51 #include <machine/trap.h>
   52 #include <machine/vmparam.h>
   53 
   54 #include <mips/atheros/ar71xxreg.h>
   55 #include <mips/atheros/qca953xreg.h>
   56 
   57 #include <mips/atheros/ar71xx_cpudef.h>
   58 #include <mips/atheros/ar71xx_setup.h>
   59 
   60 #include <mips/atheros/ar71xx_chip.h>
   61 
   62 #include <mips/atheros/qca953x_chip.h>
   63 
   64 static void
   65 qca953x_chip_detect_mem_size(void)
   66 {
   67 }
   68 
   69 static void
   70 qca953x_chip_detect_sys_frequency(void)
   71 {
   72         unsigned long ref_rate;
   73         unsigned long cpu_rate;
   74         unsigned long ddr_rate;
   75         unsigned long ahb_rate;
   76         uint32_t pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
   77         uint32_t cpu_pll, ddr_pll;
   78         uint32_t bootstrap;
   79 
   80         bootstrap = ATH_READ_REG(QCA953X_RESET_REG_BOOTSTRAP);
   81         if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
   82                 ref_rate = 40 * 1000 * 1000;
   83         else
   84                 ref_rate = 25 * 1000 * 1000;
   85 
   86         pll = ATH_READ_REG(QCA953X_PLL_CPU_CONFIG_REG);
   87         out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
   88                   QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
   89         ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
   90                   QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
   91         nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
   92                QCA953X_PLL_CPU_CONFIG_NINT_MASK;
   93         frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
   94                QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
   95 
   96         cpu_pll = nint * ref_rate / ref_div;
   97         cpu_pll += frac * (ref_rate >> 6) / ref_div;
   98         cpu_pll /= (1 << out_div);
   99 
  100         pll = ATH_READ_REG(QCA953X_PLL_DDR_CONFIG_REG);
  101         out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  102                   QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
  103         ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  104                   QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
  105         nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
  106                QCA953X_PLL_DDR_CONFIG_NINT_MASK;
  107         frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  108                QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
  109 
  110         ddr_pll = nint * ref_rate / ref_div;
  111         ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
  112         ddr_pll /= (1 << out_div);
  113 
  114         clk_ctrl = ATH_READ_REG(QCA953X_PLL_CLK_CTRL_REG);
  115 
  116         postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
  117                   QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
  118 
  119         if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
  120                 cpu_rate = ref_rate;
  121         else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
  122                 cpu_rate = cpu_pll / (postdiv + 1);
  123         else
  124                 cpu_rate = ddr_pll / (postdiv + 1);
  125 
  126         postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
  127                   QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
  128 
  129         if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
  130                 ddr_rate = ref_rate;
  131         else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
  132                 ddr_rate = ddr_pll / (postdiv + 1);
  133         else
  134                 ddr_rate = cpu_pll / (postdiv + 1);
  135 
  136         postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
  137                   QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
  138 
  139         if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
  140                 ahb_rate = ref_rate;
  141         else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
  142                 ahb_rate = ddr_pll / (postdiv + 1);
  143         else
  144                 ahb_rate = cpu_pll / (postdiv + 1);
  145 
  146         u_ar71xx_ddr_freq = ddr_rate;
  147         u_ar71xx_cpu_freq = cpu_rate;
  148         u_ar71xx_ahb_freq = ahb_rate;
  149 
  150         u_ar71xx_wdt_freq = ref_rate;
  151         u_ar71xx_uart_freq = ref_rate;
  152         u_ar71xx_mdio_freq = ref_rate;
  153         u_ar71xx_refclk = ref_rate;
  154 }
  155 
  156 static void
  157 qca953x_chip_device_stop(uint32_t mask)
  158 {
  159         uint32_t reg;
  160 
  161         reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
  162         ATH_WRITE_REG(QCA953X_RESET_REG_RESET_MODULE, reg | mask);
  163 }
  164 
  165 static void
  166 qca953x_chip_device_start(uint32_t mask)
  167 {
  168         uint32_t reg;
  169 
  170         reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
  171         ATH_WRITE_REG(QCA953X_RESET_REG_RESET_MODULE, reg & ~mask);
  172 }
  173 
  174 static int
  175 qca953x_chip_device_stopped(uint32_t mask)
  176 {
  177         uint32_t reg;
  178 
  179         reg = ATH_READ_REG(QCA953X_RESET_REG_RESET_MODULE);
  180         return ((reg & mask) == mask);
  181 }
  182 
  183 static void
  184 qca953x_chip_set_mii_speed(uint32_t unit, uint32_t speed)
  185 {
  186 
  187         /* XXX TODO */
  188         return;
  189 }
  190 
  191 static void
  192 qca953x_chip_set_pll_ge(int unit, int speed, uint32_t pll)
  193 {
  194         switch (unit) {
  195         case 0:
  196                 ATH_WRITE_REG(QCA953X_PLL_ETH_XMII_CONTROL_REG, pll);
  197                 break;
  198         case 1:
  199                 /* nothing */
  200                 break;
  201         default:
  202                 printf("%s: invalid PLL set for arge unit: %d\n",
  203                     __func__, unit);
  204                 return;
  205         }
  206 }
  207 
  208 static void
  209 qca953x_chip_ddr_flush(ar71xx_flush_ddr_id_t id)
  210 {
  211 
  212         switch (id) {
  213         case AR71XX_CPU_DDR_FLUSH_GE0:
  214                 ar71xx_ddr_flush(QCA953X_DDR_REG_FLUSH_GE0);
  215                 break;
  216         case AR71XX_CPU_DDR_FLUSH_GE1:
  217                 ar71xx_ddr_flush(QCA953X_DDR_REG_FLUSH_GE1);
  218                 break;
  219         case AR71XX_CPU_DDR_FLUSH_USB:
  220                 ar71xx_ddr_flush(QCA953X_DDR_REG_FLUSH_USB);
  221                 break;
  222         case AR71XX_CPU_DDR_FLUSH_PCIE:
  223                 ar71xx_ddr_flush(QCA953X_DDR_REG_FLUSH_PCIE);
  224                 break;
  225         case AR71XX_CPU_DDR_FLUSH_WMAC:
  226                 ar71xx_ddr_flush(QCA953X_DDR_REG_FLUSH_WMAC);
  227                 break;
  228         default:
  229                 printf("%s: invalid flush (%d)\n", __func__, id);
  230         }
  231 }
  232 
  233 static uint32_t
  234 qca953x_chip_get_eth_pll(unsigned int mac, int speed)
  235 {
  236         uint32_t pll;
  237 
  238         switch (speed) {
  239         case 10:
  240                 pll = QCA953X_PLL_VAL_10;
  241                 break;
  242         case 100:
  243                 pll = QCA953X_PLL_VAL_100;
  244                 break;
  245         case 1000:
  246                 pll = QCA953X_PLL_VAL_1000;
  247                 break;
  248         default:
  249                 printf("%s%d: invalid speed %d\n", __func__, mac, speed);
  250                 pll = 0;
  251         }
  252         return (pll);
  253 }
  254 
  255 static void
  256 qca953x_chip_reset_ethernet_switch(void)
  257 {
  258 }
  259 
  260 static void
  261 qca953x_configure_gmac(uint32_t gmac_cfg)
  262 {
  263         uint32_t reg;
  264 
  265         reg = ATH_READ_REG(QCA953X_GMAC_REG_ETH_CFG);
  266         printf("%s: ETH_CFG=0x%08x\n", __func__, reg);
  267         reg &= ~(QCA953X_ETH_CFG_SW_ONLY_MODE |
  268             QCA953X_ETH_CFG_SW_PHY_SWAP |
  269             QCA953X_ETH_CFG_SW_APB_ACCESS |
  270             QCA953X_ETH_CFG_SW_ACC_MSB_FIRST);
  271 
  272         reg |= gmac_cfg;
  273         ATH_WRITE_REG(QCA953X_GMAC_REG_ETH_CFG, reg);
  274 }
  275 
  276 static void
  277 qca953x_chip_init_usb_peripheral(void)
  278 {
  279         uint32_t bootstrap;
  280 
  281         bootstrap = ATH_READ_REG(QCA953X_RESET_REG_BOOTSTRAP);
  282 
  283         ar71xx_device_stop(QCA953X_RESET_USBSUS_OVERRIDE);
  284         DELAY(1000);
  285 
  286         ar71xx_device_start(QCA953X_RESET_USB_PHY);
  287         DELAY(1000);
  288 
  289         ar71xx_device_start(QCA953X_RESET_USB_PHY_ANALOG);
  290         DELAY(1000);
  291 
  292         ar71xx_device_start(QCA953X_RESET_USB_HOST);
  293         DELAY(1000);
  294 }
  295 
  296 static void
  297 qca953x_chip_set_mii_if(uint32_t unit, uint32_t mii_mode)
  298 {
  299 
  300         /*
  301          * XXX !
  302          *
  303          * Nothing to see here; although gmac0 can have its
  304          * MII configuration changed, the register values
  305          * are slightly different.
  306          */
  307 }
  308 
  309 /*
  310  * XXX TODO: fetch default MII divider configuration
  311  */
  312 
  313 static void
  314 qca953x_chip_reset_wmac(void)
  315 {
  316 
  317         /* XXX TODO */
  318 }
  319 
  320 static void
  321 qca953x_chip_init_gmac(void)
  322 {
  323         long gmac_cfg;
  324 
  325         if (resource_long_value("qca953x_gmac", 0, "gmac_cfg",
  326             &gmac_cfg) == 0) {
  327                 printf("%s: gmac_cfg=0x%08lx\n",
  328                     __func__,
  329                     (long) gmac_cfg);
  330                 qca953x_configure_gmac((uint32_t) gmac_cfg);
  331         }
  332 }
  333 
  334 /*
  335  * Reset the NAND Flash Controller.
  336  *
  337  * + active=1 means "make it active".
  338  * + active=0 means "make it inactive".
  339  */
  340 static void
  341 qca953x_chip_reset_nfc(int active)
  342 {
  343 }
  344 
  345 /*
  346  * Configure the GPIO output mux setup.
  347  *
  348  * The QCA953x has an output mux which allowed
  349  * certain functions to be configured on any pin.
  350  * Specifically, the switch PHY link LEDs and
  351  * WMAC external RX LNA switches are not limited to
  352  * a specific GPIO pin.
  353  */
  354 static void
  355 qca953x_chip_gpio_output_configure(int gpio, uint8_t func)
  356 {
  357         uint32_t reg, s;
  358         uint32_t t;
  359 
  360         if (gpio > QCA953X_GPIO_COUNT)
  361                 return;
  362 
  363         reg = QCA953X_GPIO_REG_OUT_FUNC0 + rounddown(gpio, 4);
  364         s = 8 * (gpio % 4);
  365 
  366         /* read-modify-write */
  367         t = ATH_READ_REG(AR71XX_GPIO_BASE + reg);
  368         t &= ~(0xff << s);
  369         t |= func << s;
  370         ATH_WRITE_REG(AR71XX_GPIO_BASE + reg, t);
  371 
  372         /* flush write */
  373         ATH_READ_REG(AR71XX_GPIO_BASE + reg);
  374 }
  375 
  376 struct ar71xx_cpu_def qca953x_chip_def = {
  377         &qca953x_chip_detect_mem_size,
  378         &qca953x_chip_detect_sys_frequency,
  379         &qca953x_chip_device_stop,
  380         &qca953x_chip_device_start,
  381         &qca953x_chip_device_stopped,
  382         &qca953x_chip_set_pll_ge,
  383         &qca953x_chip_set_mii_speed,
  384         &qca953x_chip_set_mii_if,
  385         &qca953x_chip_get_eth_pll,
  386         &qca953x_chip_ddr_flush,
  387         &qca953x_chip_init_usb_peripheral,
  388         &qca953x_chip_reset_ethernet_switch,
  389         &qca953x_chip_reset_wmac,
  390         &qca953x_chip_init_gmac,
  391         &qca953x_chip_reset_nfc,
  392         &qca953x_chip_gpio_output_configure,
  393 };

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