Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/mips/atheros/qca955x_pci.c
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1 /*- 2 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org> 3 * Copyright (c) 2011, Luiz Otavio O Souza. 4 * Copyright (c) 2015, Adrian Chadd <adrian@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD: releng/11.2/sys/mips/atheros/qca955x_pci.c 295880 2016-02-22 09:02:20Z skra $"); 32 33 #include "opt_ar71xx.h" 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 38 #include <sys/bus.h> 39 #include <sys/interrupt.h> 40 #include <sys/malloc.h> 41 #include <sys/kernel.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 45 #include <vm/vm.h> 46 #include <vm/pmap.h> 47 #include <vm/vm_extern.h> 48 49 #include <machine/bus.h> 50 #include <machine/cpu.h> 51 #include <machine/intr_machdep.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <dev/pci/pcireg.h> 55 56 #include <dev/pci/pcib_private.h> 57 #include "pcib_if.h" 58 59 #include <mips/atheros/ar71xxreg.h> /* XXX aim to eliminate this! */ 60 #include <mips/atheros/qca955xreg.h> 61 #include <mips/atheros/ar71xx_setup.h> 62 #include <mips/atheros/ar71xx_pci_bus_space.h> 63 64 #include <mips/atheros/ar71xx_cpudef.h> 65 66 #undef AR724X_PCI_DEBUG 67 //#define AR724X_PCI_DEBUG 68 #ifdef AR724X_PCI_DEBUG 69 #define dprintf printf 70 #else 71 #define dprintf(x, arg...) 72 #endif 73 74 /* 75 * This is a PCI controller for the QCA955x and later SoCs. 76 * It needs to be aware of >1 PCIe host endpoints. 77 * 78 * XXX TODO; it may be nice to merge this with ar724x_pci.c; 79 * they're very similar. 80 */ 81 struct ar71xx_pci_irq { 82 struct ar71xx_pci_softc *sc; 83 int irq; 84 }; 85 86 struct ar71xx_pci_softc { 87 device_t sc_dev; 88 89 int sc_busno; 90 struct rman sc_mem_rman; 91 struct rman sc_irq_rman; 92 93 uint32_t sc_pci_reg_base; /* XXX until bus stuff is done */ 94 uint32_t sc_pci_crp_base; /* XXX until bus stuff is done */ 95 uint32_t sc_pci_ctrl_base; /* XXX until bus stuff is done */ 96 uint32_t sc_pci_mem_base; /* XXX until bus stuff is done */ 97 uint32_t sc_pci_membase_limit; 98 99 struct intr_event *sc_eventstab[AR71XX_PCI_NIRQS]; 100 mips_intrcnt_t sc_intr_counter[AR71XX_PCI_NIRQS]; 101 struct ar71xx_pci_irq sc_pci_irq[AR71XX_PCI_NIRQS]; 102 struct resource *sc_irq; 103 void *sc_ih; 104 }; 105 106 static int qca955x_pci_setup_intr(device_t, device_t, struct resource *, int, 107 driver_filter_t *, driver_intr_t *, void *, void **); 108 static int qca955x_pci_teardown_intr(device_t, device_t, struct resource *, 109 void *); 110 static int qca955x_pci_intr(void *); 111 112 static void 113 qca955x_pci_write(uint32_t reg, uint32_t offset, uint32_t data, int bytes) 114 { 115 uint32_t val, mask, shift; 116 117 /* Register access is 32-bit aligned */ 118 shift = (offset & 3) * 8; 119 if (bytes % 4) 120 mask = (1 << (bytes * 8)) - 1; 121 else 122 mask = 0xffffffff; 123 124 val = ATH_READ_REG(reg + (offset & ~3)); 125 val &= ~(mask << shift); 126 val |= ((data & mask) << shift); 127 ATH_WRITE_REG(reg + (offset & ~3), val); 128 129 dprintf("%s: %#x/%#x addr=%#x, data=%#x(%#x), bytes=%d\n", __func__, 130 reg, reg + (offset & ~3), offset, data, val, bytes); 131 } 132 133 static uint32_t 134 qca955x_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, 135 u_int reg, int bytes) 136 { 137 struct ar71xx_pci_softc *sc = device_get_softc(dev); 138 uint32_t data, shift, mask; 139 140 /* Register access is 32-bit aligned */ 141 shift = (reg & 3) * 8; 142 143 /* Create a mask based on the width, post-shift */ 144 if (bytes == 2) 145 mask = 0xffff; 146 else if (bytes == 1) 147 mask = 0xff; 148 else 149 mask = 0xffffffff; 150 151 dprintf("%s: tag (%x, %x, %x) reg %d(%d)\n", __func__, bus, slot, 152 func, reg, bytes); 153 154 if ((bus == 0) && (slot == 0) && (func == 0)) 155 data = ATH_READ_REG(sc->sc_pci_reg_base + (reg & ~3)); 156 else 157 data = -1; 158 159 /* Get request bytes from 32-bit word */ 160 data = (data >> shift) & mask; 161 162 dprintf("%s: read 0x%x\n", __func__, data); 163 164 return (data); 165 } 166 167 static void 168 qca955x_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, 169 u_int reg, uint32_t data, int bytes) 170 { 171 struct ar71xx_pci_softc *sc = device_get_softc(dev); 172 173 dprintf("%s: tag (%x, %x, %x) reg %d(%d): %x\n", __func__, bus, slot, 174 func, reg, bytes, data); 175 176 if ((bus != 0) || (slot != 0) || (func != 0)) 177 return; 178 179 qca955x_pci_write(sc->sc_pci_reg_base, reg, data, bytes); 180 } 181 182 static void 183 qca955x_pci_mask_irq(void *source) 184 { 185 uint32_t reg; 186 struct ar71xx_pci_irq *pirq = source; 187 struct ar71xx_pci_softc *sc = pirq->sc; 188 189 /* XXX - Only one interrupt ? Only one device ? */ 190 if (pirq->irq != AR71XX_PCI_IRQ_START) 191 return; 192 193 /* Update the interrupt mask reg */ 194 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK); 195 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK, 196 reg & ~QCA955X_PCI_INTR_DEV0); 197 198 /* Clear any pending interrupt */ 199 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS); 200 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS, 201 reg | QCA955X_PCI_INTR_DEV0); 202 } 203 204 static void 205 qca955x_pci_unmask_irq(void *source) 206 { 207 uint32_t reg; 208 struct ar71xx_pci_irq *pirq = source; 209 struct ar71xx_pci_softc *sc = pirq->sc; 210 211 if (pirq->irq != AR71XX_PCI_IRQ_START) 212 return; 213 214 /* Update the interrupt mask reg */ 215 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK); 216 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK, 217 reg | QCA955X_PCI_INTR_DEV0); 218 } 219 220 static int 221 qca955x_pci_setup(device_t dev) 222 { 223 struct ar71xx_pci_softc *sc = device_get_softc(dev); 224 uint32_t reg; 225 226 /* setup COMMAND register */ 227 reg = PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | PCIM_CMD_SERRESPEN | 228 PCIM_CMD_BACKTOBACK | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN; 229 230 qca955x_pci_write(sc->sc_pci_crp_base, PCIR_COMMAND, reg, 2); 231 232 /* These are the memory/prefetch base/limit parameters */ 233 qca955x_pci_write(sc->sc_pci_crp_base, 0x20, sc->sc_pci_membase_limit, 4); 234 qca955x_pci_write(sc->sc_pci_crp_base, 0x24, sc->sc_pci_membase_limit, 4); 235 236 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET); 237 if (reg != 0x7) { 238 DELAY(100000); 239 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET, 0); 240 ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET); 241 DELAY(100); 242 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET, 4); 243 ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET); 244 DELAY(100000); 245 } 246 247 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_APP, 0x1ffc1); 248 /* Flush write */ 249 (void) ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_APP); 250 251 DELAY(1000); 252 253 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_RESET); 254 if ((reg & QCA955X_PCI_RESET_LINK_UP) == 0) { 255 device_printf(dev, "no PCIe controller found\n"); 256 return (ENXIO); 257 } 258 259 return (0); 260 } 261 262 static int 263 qca955x_pci_probe(device_t dev) 264 { 265 266 return (BUS_PROBE_NOWILDCARD); 267 } 268 269 static int 270 qca955x_pci_attach(device_t dev) 271 { 272 struct ar71xx_pci_softc *sc = device_get_softc(dev); 273 int unit = device_get_unit(dev); 274 int rid = 0; 275 276 /* Dirty; maybe these could all just be hints */ 277 if (unit == 0) { 278 sc->sc_pci_reg_base = QCA955X_PCI_CFG_BASE0; 279 sc->sc_pci_crp_base = QCA955X_PCI_CRP_BASE0; 280 sc->sc_pci_ctrl_base = QCA955X_PCI_CTRL_BASE0; 281 sc->sc_pci_mem_base = QCA955X_PCI_MEM_BASE0; 282 /* XXX verify */ 283 sc->sc_pci_membase_limit = 0x11f01000; 284 } else if (unit == 1) { 285 sc->sc_pci_reg_base = QCA955X_PCI_CFG_BASE1; 286 sc->sc_pci_crp_base = QCA955X_PCI_CRP_BASE1; 287 sc->sc_pci_ctrl_base = QCA955X_PCI_CTRL_BASE1; 288 sc->sc_pci_mem_base = QCA955X_PCI_MEM_BASE1; 289 /* XXX verify */ 290 sc->sc_pci_membase_limit = 0x12f01200; 291 } else { 292 device_printf(dev, "%s: invalid unit (%d)\n", __func__, unit); 293 return (ENXIO); 294 } 295 296 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 297 sc->sc_mem_rman.rm_descr = "qca955x PCI memory window"; 298 if (rman_init(&sc->sc_mem_rman) != 0 || 299 rman_manage_region(&sc->sc_mem_rman, 300 sc->sc_pci_mem_base, 301 sc->sc_pci_mem_base + QCA955X_PCI_MEM_SIZE - 1) != 0) { 302 panic("qca955x_pci_attach: failed to set up I/O rman"); 303 } 304 305 sc->sc_irq_rman.rm_type = RMAN_ARRAY; 306 sc->sc_irq_rman.rm_descr = "qca955x PCI IRQs"; 307 if (rman_init(&sc->sc_irq_rman) != 0 || 308 rman_manage_region(&sc->sc_irq_rman, AR71XX_PCI_IRQ_START, 309 AR71XX_PCI_IRQ_END) != 0) 310 panic("qca955x_pci_attach: failed to set up IRQ rman"); 311 312 /* Disable interrupts */ 313 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS, 0); 314 ATH_WRITE_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK, 0); 315 316 /* Hook up our interrupt handler. */ 317 if ((sc->sc_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 318 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 319 device_printf(dev, "unable to allocate IRQ resource\n"); 320 return (ENXIO); 321 } 322 323 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, 324 qca955x_pci_intr, NULL, sc, &sc->sc_ih))) { 325 device_printf(dev, 326 "WARNING: unable to register interrupt handler\n"); 327 return (ENXIO); 328 } 329 330 /* Reset PCIe core and PCIe PHY */ 331 ar71xx_device_stop(QCA955X_RESET_PCIE); 332 ar71xx_device_stop(QCA955X_RESET_PCIE_PHY); 333 DELAY(100); 334 ar71xx_device_start(QCA955X_RESET_PCIE_PHY); 335 ar71xx_device_start(QCA955X_RESET_PCIE); 336 337 if (qca955x_pci_setup(dev)) 338 return (ENXIO); 339 340 /* 341 * Write initial base address. 342 * 343 * I'm not yet sure why this is required and/or why it isn't 344 * initialised like this. The AR71xx PCI code initialises 345 * the PCI windows for each device, but neither it or the 346 * 724x PCI bridge modules explicitly initialise the BAR. 347 * 348 * So before this gets committed, have a chat with jhb@ or 349 * someone else who knows PCI well and figure out whether 350 * the initial BAR is supposed to be determined by /other/ 351 * means. 352 */ 353 qca955x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0), 354 sc->sc_pci_mem_base, 355 4); 356 357 /* Fixup internal PCI bridge */ 358 qca955x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, 359 PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN 360 | PCIM_CMD_SERRESPEN | PCIM_CMD_BACKTOBACK 361 | PCIM_CMD_PERRESPEN | PCIM_CMD_MWRICEN, 2); 362 363 device_add_child(dev, "pci", -1); 364 return (bus_generic_attach(dev)); 365 } 366 367 static int 368 qca955x_pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 369 { 370 struct ar71xx_pci_softc *sc = device_get_softc(dev); 371 372 switch (which) { 373 case PCIB_IVAR_DOMAIN: 374 *result = 0; 375 return (0); 376 case PCIB_IVAR_BUS: 377 *result = sc->sc_busno; 378 return (0); 379 } 380 381 return (ENOENT); 382 } 383 384 static int 385 qca955x_pci_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 386 { 387 struct ar71xx_pci_softc * sc = device_get_softc(dev); 388 389 switch (which) { 390 case PCIB_IVAR_BUS: 391 sc->sc_busno = result; 392 return (0); 393 } 394 395 return (ENOENT); 396 } 397 398 static struct resource * 399 qca955x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 400 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 401 { 402 struct ar71xx_pci_softc *sc = device_get_softc(bus); 403 struct resource *rv; 404 struct rman *rm; 405 406 switch (type) { 407 case SYS_RES_IRQ: 408 rm = &sc->sc_irq_rman; 409 break; 410 case SYS_RES_MEMORY: 411 rm = &sc->sc_mem_rman; 412 break; 413 default: 414 return (NULL); 415 } 416 417 rv = rman_reserve_resource(rm, start, end, count, flags, child); 418 419 if (rv == NULL) 420 return (NULL); 421 422 rman_set_rid(rv, *rid); 423 424 if (flags & RF_ACTIVE) { 425 if (bus_activate_resource(child, type, *rid, rv)) { 426 rman_release_resource(rv); 427 return (NULL); 428 } 429 } 430 431 return (rv); 432 } 433 434 static int 435 qca955x_pci_activate_resource(device_t bus, device_t child, int type, int rid, 436 struct resource *r) 437 { 438 int res = (BUS_ACTIVATE_RESOURCE(device_get_parent(bus), 439 child, type, rid, r)); 440 441 if (!res) { 442 switch(type) { 443 case SYS_RES_MEMORY: 444 case SYS_RES_IOPORT: 445 446 rman_set_bustag(r, ar71xx_bus_space_pcimem); 447 break; 448 } 449 } 450 451 return (res); 452 } 453 454 static int 455 qca955x_pci_setup_intr(device_t bus, device_t child, struct resource *ires, 456 int flags, driver_filter_t *filt, driver_intr_t *handler, 457 void *arg, void **cookiep) 458 { 459 struct ar71xx_pci_softc *sc = device_get_softc(bus); 460 struct intr_event *event; 461 int irq, error; 462 463 irq = rman_get_start(ires); 464 if (irq > AR71XX_PCI_IRQ_END) 465 panic("%s: bad irq %d", __func__, irq); 466 467 event = sc->sc_eventstab[irq]; 468 if (event == NULL) { 469 sc->sc_pci_irq[irq].sc = sc; 470 sc->sc_pci_irq[irq].irq = irq; 471 error = intr_event_create(&event, (void *)&sc->sc_pci_irq[irq], 472 0, irq, 473 qca955x_pci_mask_irq, 474 qca955x_pci_unmask_irq, 475 NULL, NULL, 476 "pci intr%d:", irq); 477 478 if (error == 0) { 479 sc->sc_eventstab[irq] = event; 480 sc->sc_intr_counter[irq] = 481 mips_intrcnt_create(event->ie_name); 482 } 483 else 484 return error; 485 } 486 487 intr_event_add_handler(event, device_get_nameunit(child), filt, 488 handler, arg, intr_priority(flags), flags, cookiep); 489 mips_intrcnt_setname(sc->sc_intr_counter[irq], event->ie_fullname); 490 491 qca955x_pci_unmask_irq(&sc->sc_pci_irq[irq]); 492 493 return (0); 494 } 495 496 static int 497 qca955x_pci_teardown_intr(device_t dev, device_t child, struct resource *ires, 498 void *cookie) 499 { 500 struct ar71xx_pci_softc *sc = device_get_softc(dev); 501 int irq, result; 502 503 irq = rman_get_start(ires); 504 if (irq > AR71XX_PCI_IRQ_END) 505 panic("%s: bad irq %d", __func__, irq); 506 507 if (sc->sc_eventstab[irq] == NULL) 508 panic("Trying to teardown unoccupied IRQ"); 509 510 qca955x_pci_mask_irq(&sc->sc_pci_irq[irq]); 511 512 result = intr_event_remove_handler(cookie); 513 if (!result) 514 sc->sc_eventstab[irq] = NULL; 515 516 return (result); 517 } 518 519 static int 520 qca955x_pci_intr(void *arg) 521 { 522 struct ar71xx_pci_softc *sc = arg; 523 struct intr_event *event; 524 uint32_t reg, irq, mask; 525 526 /* There's only one PCIe DDR flush for both PCIe EPs */ 527 ar71xx_device_flush_ddr(AR71XX_CPU_DDR_FLUSH_PCIE); 528 529 reg = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_STATUS); 530 mask = ATH_READ_REG(sc->sc_pci_ctrl_base + QCA955X_PCI_INTR_MASK); 531 532 /* 533 * Handle only unmasked interrupts 534 */ 535 reg &= mask; 536 /* 537 * XXX TODO: handle >1 PCIe end point! 538 */ 539 if (reg & QCA955X_PCI_INTR_DEV0) { 540 irq = AR71XX_PCI_IRQ_START; 541 event = sc->sc_eventstab[irq]; 542 if (!event || TAILQ_EMPTY(&event->ie_handlers)) { 543 printf("Stray IRQ %d\n", irq); 544 return (FILTER_STRAY); 545 } 546 547 /* TODO: frame instead of NULL? */ 548 intr_event_handle(event, NULL); 549 mips_intrcnt_inc(sc->sc_intr_counter[irq]); 550 } 551 552 return (FILTER_HANDLED); 553 } 554 555 static int 556 qca955x_pci_maxslots(device_t dev) 557 { 558 559 return (PCI_SLOTMAX); 560 } 561 562 static int 563 qca955x_pci_route_interrupt(device_t pcib, device_t device, int pin) 564 { 565 566 return (pci_get_slot(device)); 567 } 568 569 static device_method_t qca955x_pci_methods[] = { 570 /* Device interface */ 571 DEVMETHOD(device_probe, qca955x_pci_probe), 572 DEVMETHOD(device_attach, qca955x_pci_attach), 573 DEVMETHOD(device_shutdown, bus_generic_shutdown), 574 DEVMETHOD(device_suspend, bus_generic_suspend), 575 DEVMETHOD(device_resume, bus_generic_resume), 576 577 /* Bus interface */ 578 DEVMETHOD(bus_read_ivar, qca955x_pci_read_ivar), 579 DEVMETHOD(bus_write_ivar, qca955x_pci_write_ivar), 580 DEVMETHOD(bus_alloc_resource, qca955x_pci_alloc_resource), 581 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 582 DEVMETHOD(bus_activate_resource, qca955x_pci_activate_resource), 583 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 584 DEVMETHOD(bus_setup_intr, qca955x_pci_setup_intr), 585 DEVMETHOD(bus_teardown_intr, qca955x_pci_teardown_intr), 586 587 /* pcib interface */ 588 DEVMETHOD(pcib_maxslots, qca955x_pci_maxslots), 589 DEVMETHOD(pcib_read_config, qca955x_pci_read_config), 590 DEVMETHOD(pcib_write_config, qca955x_pci_write_config), 591 DEVMETHOD(pcib_route_interrupt, qca955x_pci_route_interrupt), 592 593 DEVMETHOD_END 594 }; 595 596 static driver_t qca955x_pci_driver = { 597 "pcib", 598 qca955x_pci_methods, 599 sizeof(struct ar71xx_pci_softc), 600 }; 601 602 static devclass_t qca955x_pci_devclass; 603 604 DRIVER_MODULE(qca955x_pci, nexus, qca955x_pci_driver, qca955x_pci_devclass, 0, 0); 605 DRIVER_MODULE(qca955x_pci, apb, qca955x_pci_driver, qca955x_pci_devclass, 0, 0);
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