The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/mips/broadcom/bcm_bmips_exts.h

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright 2000,2001,2002,2003 Broadcom Corporation.
    3  * All rights reserved.
    4  *
    5  * This file is derived from the sbmips32.h header distributed
    6  * by Broadcom with the CFE 1.4.2 sources.
    7  *
    8  * This software is furnished under license and may be used and
    9  * copied only in accordance with the following terms and
   10  * conditions.  Subject to these conditions, you may download,
   11  * copy, install, use, modify and distribute modified or unmodified
   12  * copies of this software in source and/or binary form.  No title
   13  * or ownership is transferred hereby.
   14  *
   15  * 1) Any source code used, modified or distributed must reproduce
   16  *    and retain this copyright notice and list of conditions
   17  *    as they appear in the source file.
   18  *
   19  * 2) No right is granted to use any trade name, trademark, or
   20  *    logo of Broadcom Corporation.  The "Broadcom Corporation"
   21  *    name may not be used to endorse or promote products derived
   22  *    from this software without the prior written permission of
   23  *    Broadcom Corporation.
   24  *
   25  * 3) THIS SOFTWARE IS PROVIDED "AS-IS" AND ANY EXPRESS OR
   26  *    IMPLIED WARRANTIES, INCLUDING BUT NOT LIMITED TO, ANY IMPLIED
   27  *    WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
   28  *    PURPOSE, OR NON-INFRINGEMENT ARE DISCLAIMED. IN NO EVENT
   29  *    SHALL BROADCOM BE LIABLE FOR ANY DAMAGES WHATSOEVER, AND IN
   30  *    PARTICULAR, BROADCOM SHALL NOT BE LIABLE FOR DIRECT, INDIRECT,
   31  *    INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   32  *    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
   33  *    GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
   34  *    BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
   35  *    OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
   36  *    TORT (INCLUDING NEGLIGENCE OR OTHERWISE), EVEN IF ADVISED OF
   37  *    THE POSSIBILITY OF SUCH DAMAGE.
   38  *
   39  * $FreeBSD: releng/12.0/sys/mips/broadcom/bcm_bmips_exts.h 305953 2016-09-18 21:28:09Z landonf $
   40  */
   41 
   42 
   43 /*  *********************************************************************
   44     *  Broadcom Common Firmware Environment (CFE)
   45     *  
   46     *  MIPS32 CPU definitions                   File: sbmips32.h
   47     * 
   48     *  This module contains constants and macros specific to the
   49     *  Broadcom MIPS32 core.  In addition to generic MIPS32, it
   50     *  includes definitions for the MIP32-01 and MIPS3302 OCP cores
   51     *  for the Silicon Backplane.
   52     *
   53     *********************************************************************/
   54 
   55 #ifndef _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
   56 #define _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_
   57 
   58 #include <machine/cpufunc.h>
   59 
   60 /*
   61  * The following Broadcom Custom CP0 Registers appear in the Broadcom
   62  * BMIPS330x MIPS32 core.
   63  */
   64 
   65 #define BMIPS_COP_0_BCMCFG      22
   66 
   67 /*
   68  * Custom CP0 Accessors
   69  */
   70 
   71 #define BCM_BMIPS_RW32_COP0_SEL(n,r,s)                          \
   72 static __inline uint32_t                                        \
   73 bcm_bmips_rd_ ## n(void)                                        \
   74 {                                                               \
   75         int v0;                                                 \
   76         __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";"        \
   77                           : [v0] "=&r"(v0));                    \
   78         mips_barrier();                                         \
   79         return (v0);                                            \
   80 }                                                               \
   81 static __inline void                                            \
   82 bcm_bmips_wr_ ## n(uint32_t a0)                                 \
   83 {                                                               \
   84         __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";"        \
   85                          __XSTRING(COP0_SYNC)";"                \
   86                          "nop;"                                 \
   87                          "nop;"                                 \
   88                          :                                      \
   89                          : [a0] "r"(a0));                       \
   90         mips_barrier();                                         \
   91 } struct __hack
   92 
   93 BCM_BMIPS_RW32_COP0_SEL(pllcfg1,        MIPS_COP_0_CONFIG,      1);
   94 BCM_BMIPS_RW32_COP0_SEL(pllcfg2,        MIPS_COP_0_CONFIG,      2);
   95 BCM_BMIPS_RW32_COP0_SEL(clksync,        MIPS_COP_0_CONFIG,      3);
   96 BCM_BMIPS_RW32_COP0_SEL(pllcfg3,        MIPS_COP_0_CONFIG,      4);
   97 BCM_BMIPS_RW32_COP0_SEL(rstcfg,         MIPS_COP_0_CONFIG,      5);
   98 
   99 /*
  100  * Broadcom PLLConfig1 Register (22, select 1)
  101  */
  102 
  103 /* SoftMIPSPLLCfg */
  104 #define BMIPS_BCMCFG_PLLCFG1_MC_SHIFT   10
  105 #define BMIPS_BCMCFG_PLLCFG1_MC_MASK    0xFFFFFC00
  106 
  107 /* SoftISBPLLCfg */
  108 #define BMIPS_BCMCFG_PLLCFG1_BC_SHIFT   5
  109 #define BMIPS_BCMCFG_PLLCFG1_BC_MASK    0x000003E0
  110 
  111 /* SoftRefPLLCfg */
  112 #define BMIPS_BCMCFG_PLLCFG1_PC_SHIFT   0
  113 #define BMIPS_BCMCFG_PLLCFG1_PC_MASK    0x0000001F
  114 
  115 /*
  116  * Broadcom PLLConfig2 Register (22, select 2)
  117  */
  118 
  119 /* Soft1to1ClkRatio */
  120 #define BMIPS_BCMCFG_PLLCFG2_CR         (1<<23)
  121 
  122 /* SoftUSBxPLLCfg */
  123 #define BMIPS_BCMCFG_PLLCFG2_UC_SHIFT   15
  124 #define BMIPS_BCMCFG_PLLCFG2_UC_MASK    0x007F8000
  125 
  126 /* SoftIDExPLLCfg */
  127 #define BMIPS_BCMCFG_PLLCFG2_IC_SHIFT   7
  128 #define BMIPS_BCMCFG_PLLCFG2_IC_MASK    0x00007F80
  129 
  130 #define BMIPS_BCMCFG_PLLCFG2_BE         (1<<6)  /* ISBxSoftCfgEnable */
  131 #define BMIPS_BCMCFG_PLLCFG2_UE         (1<<5)  /* USBxSoftCfgEnable */
  132 #define BMIPS_BCMCFG_PLLCFG2_IE         (1<<4)  /* IDExSoftCfgEnable */
  133 #define BMIPS_BCMCFG_PLLCFG2_CA         (1<<3)  /* CfgActive */
  134 #define BMIPS_BCMCFG_PLLCFG2_CF         (1<<2)  /* RefSoftCfgEnable */
  135 #define BMIPS_BCMCFG_PLLCFG2_CI         (1<<1)  /* ISBSoftCfgEnable */
  136 #define BMIPS_BCMCFG_PLLCFG2_CC         (1<<0)  /* MIPSSoftCfgEnable */
  137 
  138 /*
  139  * Broadcom ClkSync Register (22, select 3)
  140  */
  141 /* SoftClkCfgHigh */
  142 #define BMIPS_BCMCFG_CLKSYNC_CH_SHIFT   16
  143 #define BMIPS_BCMCFG_CLKSYNC_CH_MASK    0xFFFF0000
  144 
  145 /* SoftClkCfgLow */
  146 #define BMIPS_BCMCFG_CLKSYNC_CL_SHIFT   0
  147 #define BMIPS_BCMCFG_CLKSYNC_CL_MASK    0x0000FFFF
  148 
  149 /*
  150  * Broadcom ISBxPLLConfig3 Register (22, select 4)
  151  */
  152 
  153 /* AsyncClkRatio */
  154 #define BMIPS_BCMCFG_PLLCFG3_AR_SHIFT   23
  155 #define BMIPS_BCMCFG_PLLCFG3_AR_MASK    0x01800000
  156 
  157 #define BMIPS_BCMCFG_PLLCFG3_SM         (1<<22) /* SyncMode */
  158 
  159 /* SoftISBxPLLCfg */
  160 #define BMIPS_BCMCFG_PLLCFG3_IC_SHIFT   0
  161 #define BMIPS_BCMCFG_PLLCFG3_IC_MASK    0x003FFFFF
  162 
  163 /*
  164  * Broadcom BRCMRstConfig Register (22, select 5)
  165  */
  166 
  167 #define BMIPS_BCMCFG_RSTCFG_SR          (1<<18) /* SSMR */
  168 #define BMIPS_BCMCFG_RSTCFG_DT          (1<<16) /* BHTD */
  169 
  170 /* RStSt */
  171 #define BMIPS_BCMCFG_RSTCFG_RS_SHIFT    8
  172 #define BMIPS_BCMCFG_RSTCFG_RS_MASK     0x00001F00
  173 #define   BMIPS_BCMCFG_RST_OTHER        0x00
  174 #define   BMIPS_BCMCFG_RST_SH           0x01
  175 #define   BMIPS_BCMCFG_RST_SS           0x02
  176 #define   BMIPS_BCMCFG_RST_EJTAG        0x04
  177 #define   BMIPS_BCMCFG_RST_WDOG         0x08
  178 #define   BMIPS_BCMCFG_RST_CRC          0x10
  179 
  180 #define BMIPS_BCMCFG_RSTCFG_CR          (1<<7)  /* RStCr */
  181 
  182 /* WBMD */
  183 #define BMIPS_BCMCFG_RSTCFG_WD_SHIFT    3
  184 #define BMIPS_BCMCFG_RSTCFG_WD_MASK     0x00000078
  185 
  186 #define BMIPS_BCMCFG_RSTCFG_SS          (1<<2)  /* SSR */
  187 #define BMIPS_BCMCFG_RSTCFG_SH          (1<<1)  /* SHR */
  188 #define BMIPS_BCMCFG_RSTCFG_BR          (1<<0)  /* BdR */
  189 
  190 #endif /* _MIPS_BROADCOM_BCM_BMIPS_EXTS_H_ */

Cache object: 56a091a111399339937faefb9cfaa9fa


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.