The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/broadcom/bcm_machdep.h

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    1 /*-
    2  * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org>
    3  * Copyright (c) 2017 The FreeBSD Foundation
    4  * All rights reserved.
    5  *
    6  * Portions of this software were developed by Landon Fuller
    7  * under sponsorship from the FreeBSD Foundation.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer,
   14  *    without modification.
   15  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
   16  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
   17  *    redistribution must be conditioned upon including a substantially
   18  *    similar Disclaimer requirement for further binary redistribution.
   19  *
   20  * NO WARRANTY
   21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   22  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   23  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
   24  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
   25  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
   26  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
   29  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   31  * THE POSSIBILITY OF SUCH DAMAGES.
   32  * 
   33  * $FreeBSD: stable/12/sys/mips/broadcom/bcm_machdep.h 326079 2017-11-21 23:15:20Z landonf $
   34  */
   35 
   36 #ifndef _MIPS_BROADCOM_BCM_MACHDEP_H_
   37 #define _MIPS_BROADCOM_BCM_MACHDEP_H_
   38 
   39 #include <machine/cpufunc.h>
   40 #include <machine/cpuregs.h>
   41 
   42 #include <dev/bhnd/bhnd.h>
   43 #include <dev/bhnd/bhnd_eromvar.h>
   44 
   45 #include <dev/bhnd/cores/pmu/bhnd_pmuvar.h>
   46 
   47 #include "bcm_nvram_cfevar.h"
   48 
   49 extern const struct bhnd_pmu_io bcm_pmu_soc_io;
   50 
   51 struct bcm_platform {
   52         struct bhnd_chipid               cid;           /**< chip id */
   53         struct bhnd_core_info            cc_id;         /**< chipc core info */
   54         uintptr_t                        cc_addr;       /**< chipc core phys address */
   55         uint32_t                         cc_caps;       /**< chipc capabilities */
   56         uint32_t                         cc_caps_ext;   /**< chipc extended capabilies */
   57 
   58         struct bhnd_core_info            cpu_id;        /**< cpu core info */
   59         uintptr_t                        cpu_addr;      /**< cpu core phys address */
   60 
   61         /* On non-AOB devices, the PMU register block is mapped to chipc;
   62          * the pmu_id and pmu_addr values will be copied from cc_id
   63          * and cc_addr. */
   64         struct bhnd_core_info            pmu_id;        /**< PMU core info */
   65         uintptr_t                        pmu_addr;      /**< PMU core phys address, or
   66                                                              0x0 if no PMU */
   67 
   68         struct bhnd_pmu_query            pmu;           /**< PMU query instance */
   69 
   70         bhnd_erom_class_t               *erom_impl;     /**< erom parser class */
   71         struct kobj_ops                  erom_ops;      /**< compiled kobj opcache */
   72         struct bhnd_erom_iobus           erom_io;       /**< erom I/O callbacks */
   73         union {
   74                 bhnd_erom_static_t       data;
   75                 bhnd_erom_t              obj;
   76         } erom;
   77 
   78         struct bhnd_nvram_io            *nvram_io;      /**< NVRAM I/O context, or NULL if unavailable */
   79         bhnd_nvram_data_class           *nvram_cls;     /**< NVRAM data class, or NULL if unavailable */
   80 
   81         struct bhnd_service_registry     services;      /**< platform service providers */
   82 
   83 #ifdef CFE
   84         int                              cfe_console;   /**< Console handle, or -1 */
   85 #endif
   86 };
   87 
   88 struct bcm_platform     *bcm_get_platform(void);
   89 
   90 uint64_t                 bcm_get_cpufreq(struct bcm_platform *bp);
   91 uint64_t                 bcm_get_sifreq(struct bcm_platform *bp);
   92 uint64_t                 bcm_get_alpfreq(struct bcm_platform *bp);
   93 uint64_t                 bcm_get_ilpfreq(struct bcm_platform *bp);
   94 
   95 u_int                    bcm_get_uart_rclk(struct bcm_platform *bp);
   96 
   97 int                      bcm_get_nvram(struct bcm_platform *bp,
   98                              const char *name, void *outp, size_t *olen,
   99                              bhnd_nvram_type type);
  100 
  101 #define BCM_ERR(fmt, ...)       \
  102         printf("%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
  103 
  104 #define BCM_SOC_BSH(_addr, _offset)                     \
  105         ((bus_space_handle_t)BCM_SOC_ADDR((_addr), (_offset)))
  106 
  107 #define BCM_SOC_ADDR(_addr, _offset)                    \
  108         MIPS_PHYS_TO_KSEG1((_addr) + (_offset))
  109 
  110 #define BCM_SOC_READ_4(_addr, _offset)                  \
  111         readl(BCM_SOC_ADDR((_addr), (_offset)))
  112 #define BCM_SOC_WRITE_4(_addr, _reg, _val)              \
  113         writel(BCM_SOC_ADDR((_addr), (_offset)), (_val))
  114 
  115 #define BCM_CORE_ADDR(_bp, _name, _reg)                 \
  116         BCM_SOC_ADDR(_bp->_name, (_reg))
  117 
  118 #define BCM_CORE_READ_4(_bp, _name, _reg)               \
  119         readl(BCM_CORE_ADDR(_bp, _name, (_reg)))
  120 #define BCM_CORE_WRITE_4(_bp, _name, _reg, _val)        \
  121         writel(BCM_CORE_ADDR(_bp, _name, (_reg)), (_val))
  122 
  123 #define BCM_CHIPC_READ_4(_bp, _reg)                     \
  124         BCM_CORE_READ_4(_bp, cc_addr, (_reg))
  125 #define BCM_CHIPC_WRITE_4(_bp, _reg, _val)              \
  126         BCM_CORE_WRITE_4(_bp, cc_addr, (_reg), (_val))
  127 
  128 #define BCM_CPU_READ_4(_bp, _reg)                       \
  129         BCM_CORE_READ_4(_bp, cpu_addr, (_reg))
  130 #define BCM_CPU_WRITE_4(_bp, _reg, _val)                \
  131         BCM_CORE_WRITE_4(_bp, cpu_addr, (_reg), (_val))
  132 
  133 #define BCM_PMU_READ_4(_bp, _reg)                       \
  134         BCM_CORE_READ_4(_bp, pmu_addr, (_reg))
  135 #define BCM_PMU_WRITE_4(_bp, _reg, _val)                \
  136         BCM_CORE_WRITE_4(_bp, pmu_addr, (_reg), (_val))
  137 
  138 #endif /* _MIPS_BROADCOM_BCM_MACHDEP_H_ */

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