The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/mips/broadcom/bcm_mipsvar.h

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 2017 The FreeBSD Foundation
    3  * All rights reserved.
    4  *
    5  * This software was developed by Landon Fuller under sponsorship from
    6  * the FreeBSD Foundation.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer,
   13  *    without modification.
   14  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
   15  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
   16  *    redistribution must be conditioned upon including a substantially
   17  *    similar Disclaimer requirement for further binary redistribution.
   18  *
   19  * NO WARRANTY
   20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
   21  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
   22  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
   23  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
   24  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
   25  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   26  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   27  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
   28  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   29  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   30  * THE POSSIBILITY OF SUCH DAMAGES.
   31  * 
   32  * $FreeBSD: stable/12/sys/mips/broadcom/bcm_mipsvar.h 326079 2017-11-21 23:15:20Z landonf $
   33  */
   34 
   35 #ifndef _MIPS_BROADCOM_BCM_MIPSVAR_H_
   36 #define _MIPS_BROADCOM_BCM_MIPSVAR_H_
   37 
   38 #include <sys/param.h>
   39 #include <sys/bus.h>
   40 #include <sys/intr.h>
   41 #include <sys/lock.h>
   42 
   43 #include <machine/intr.h>
   44 
   45 DECLARE_CLASS(bcm_mips_driver);
   46 
   47 struct bcm_mips_irqsrc;
   48 struct bcm_mips_softc;
   49 
   50 #define BCM_MIPS_NINTR          32                      /**< maximum number of addressable backplane interrupt vectors */
   51 #define BCM_MIPS_IRQ_SHARED     0                       /**< MIPS CPU IRQ reserved for shared interrupt handling */
   52 #define INTR_MAP_DATA_BCM_MIPS  INTR_MAP_DATA_PLAT_2    /**< Broadcom MIPS PIC interrupt map data type */
   53 
   54 
   55 int     bcm_mips_attach(device_t dev, u_int num_cpuirqs, u_int timer_irq,
   56             driver_filter_t filter);
   57 int     bcm_mips_detach(device_t dev);
   58 
   59 /**
   60  * Broadcom MIPS PIC interrupt map data.
   61  */
   62 struct bcm_mips_intr_map_data {
   63         struct intr_map_data    mdata;
   64         u_int                   ivec;   /**< bus interrupt vector */
   65 };
   66 
   67 /**
   68  * Nested MIPS CPU interrupt handler state.
   69  */
   70 struct bcm_mips_cpuirq {
   71         struct bcm_mips_softc   *sc;            /**< driver instance state, or NULL if uninitialized. */
   72         u_int                    mips_irq;      /**< mips hardware interrupt number (relative to NSOFT_IRQ) */
   73         int                      irq_rid;       /**< mips IRQ resource id, or -1 if this entry is unavailable */
   74         struct resource         *irq_res;       /**< mips interrupt resource */
   75         void                    *irq_cookie;    /**< mips interrupt handler cookie, or NULL */
   76         struct bcm_mips_irqsrc  *isrc_solo;     /**< solo isrc assigned to this interrupt, or NULL */
   77         u_int                    refs;          /**< isrc consumer refcount */
   78 };
   79 
   80 /**
   81  * Broadcom MIPS PIC interrupt source definition.
   82  */
   83 struct bcm_mips_irqsrc {
   84         struct intr_irqsrc       isrc;
   85         u_int                    ivec;          /**< bus interrupt vector */
   86         u_int                    refs;          /**< active reference count */
   87         struct bcm_mips_cpuirq  *cpuirq;        /**< assigned MIPS HW IRQ, or NULL if no assignment */
   88 };
   89 
   90 /**
   91  * bcm_mips driver instance state. Must be first member of all subclass
   92  * softc structures.
   93  */
   94 struct bcm_mips_softc {
   95         device_t                 dev;
   96         struct bcm_mips_cpuirq   cpuirqs[NREAL_IRQS];   /**< nested CPU IRQ handlers */
   97         u_int                    num_cpuirqs;           /**< number of nested CPU IRQ handlers */
   98         u_int                    timer_irq;             /**< CPU timer IRQ */
   99         struct bcm_mips_irqsrc   isrcs[BCM_MIPS_NINTR];
  100         struct mtx               mtx;
  101 };
  102 
  103 
  104 #define BCM_MIPS_IVEC_MASK(_isrc)       (1 << ((_isrc)->ivec))
  105 
  106 #define BCM_MIPS_LOCK_INIT(sc) \
  107         mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
  108             "bhnd mips driver lock", MTX_DEF)
  109 #define BCM_MIPS_LOCK(sc)               mtx_lock(&(sc)->mtx)
  110 #define BCM_MIPS_UNLOCK(sc)             mtx_unlock(&(sc)->mtx)
  111 #define BCM_MIPS_LOCK_ASSERT(sc, what)  mtx_assert(&(sc)->mtx, what)
  112 #define BCM_MIPS_LOCK_DESTROY(sc)       mtx_destroy(&(sc)->mtx)
  113 
  114 #endif /* _MIPS_BROADCOM_BCM_MIPSVAR_H_ */

Cache object: ef2384a3334483848105691645ad9519


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.