The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/mips/cavium/octe/mv88e61xxphyreg.h

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    1 /*-
    2  * Copyright (c) 2010 Juli Mallett <jmallett@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: releng/8.4/sys/mips/cavium/octe/mv88e61xxphyreg.h 215938 2010-11-27 12:26:40Z jchandra $
   27  */
   28 
   29 /*
   30  * Register definitions for Marvell MV88E61XX
   31  *
   32  * Note that names and definitions were gleaned from Linux and U-Boot patches
   33  * released by Marvell, often by looking at contextual use of the registers
   34  * involved, and may not be representative of the full functionality of those
   35  * registers and are certainly not an exhaustive enumeration of registers.
   36  *
   37  * For an exhaustive enumeration of registers, check out the QD-DSDT package
   38  * included in the Marvell ARM Feroceon Board Support Package for Linux.
   39  */
   40 
   41 #ifndef _MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_
   42 #define _MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_
   43 
   44 /*
   45  * Port addresses & per-port registers.
   46  */
   47 #define MV88E61XX_PORT(x)       (0x10 + (x))
   48 #define MV88E61XX_HOST_PORT     (5)
   49 #define MV88E61XX_PORTS         (6)
   50 
   51 #define MV88E61XX_PORT_STATUS           (0x00)
   52 #define MV88E61XX_PORT_FORCE_MAC        (0x01)
   53 #define MV88E61XX_PORT_PAUSE_CONTROL    (0x02)
   54 #define MV88E61XX_PORT_REVISION         (0x03)
   55 #define MV88E61XX_PORT_CONTROL          (0x04)
   56 #define MV88E61XX_PORT_CONTROL2         (0x05)
   57 #define MV88E61XX_PORT_VLAN_MAP         (0x06)
   58 #define MV88E61XX_PORT_VLAN             (0x07)
   59 #define MV88E61XX_PORT_FILTER           (0x08)
   60 #define MV88E61XX_PORT_EGRESS_CONTROL   (0x09)
   61 #define MV88E61XX_PORT_EGRESS_CONTROL2  (0x0a)
   62 #define MV88E61XX_PORT_PORT_LEARN       (0x0b)
   63 #define MV88E61XX_PORT_ATU_CONTROL      (0x0c)
   64 #define MV88E61XX_PORT_PRIORITY_CONTROL (0x0d)
   65 #define MV88E61XX_PORT_ETHER_PROTO      (0x0f)
   66 #define MV88E61XX_PORT_PROVIDER_PROTO   (0x1a)
   67 #define MV88E61XX_PORT_PRIORITY_MAP     (0x18)
   68 #define MV88E61XX_PORT_PRIORITY_MAP2    (0x19)
   69 
   70 /*
   71  * Fields and values in each register.
   72  */
   73 #define MV88E61XX_PORT_STATUS_MEDIA             (0x0300)
   74 #define MV88E61XX_PORT_STATUS_MEDIA_10M         (0x0000)
   75 #define MV88E61XX_PORT_STATUS_MEDIA_100M        (0x0100)
   76 #define MV88E61XX_PORT_STATUS_MEDIA_1G          (0x0200)
   77 #define MV88E61XX_PORT_STATUS_DUPLEX            (0x0400)
   78 #define MV88E61XX_PORT_STATUS_LINK              (0x0800)
   79 #define MV88E61XX_PORT_STATUS_FC                (0x8000)
   80 
   81 #define MV88E61XX_PORT_CONTROL_DOUBLE_TAG       (0x0200)
   82 
   83 #define MV88E61XX_PORT_FILTER_MAP_DEST          (0x0080)
   84 #define MV88E61XX_PORT_FILTER_DISCARD_UNTAGGED  (0x0100)
   85 #define MV88E61XX_PORT_FILTER_DISCARD_TAGGED    (0x0200)
   86 #define MV88E61XX_PORT_FILTER_8021Q_MODE        (0x0c00)
   87 #define MV88E61XX_PORT_FILTER_8021Q_DISABLED    (0x0000)
   88 #define MV88E61XX_PORT_FILTER_8021Q_FALLBACK    (0x0400)
   89 #define MV88E61XX_PORT_FILTER_8021Q_CHECK       (0x0800)
   90 #define MV88E61XX_PORT_FILTER_8021Q_SECURE      (0x0c00)
   91 
   92 /*
   93  * Global address & global registers.
   94  */
   95 #define MV88E61XX_GLOBAL        (0x1b)
   96 
   97 #define MV88E61XX_GLOBAL_STATUS         (0x00)
   98 #define MV88E61XX_GLOBAL_CONTROL        (0x04)
   99 #define MV88E61XX_GLOBAL_VTU_OP         (0x05)
  100 #define MV88E61XX_GLOBAL_VTU_VID        (0x06)
  101 #define MV88E61XX_GLOBAL_VTU_DATA_P0P3  (0x07)
  102 #define MV88E61XX_GLOBAL_VTU_DATA_P4P5  (0x08)
  103 #define MV88E61XX_GLOBAL_ATU_CONTROL    (0x0a)
  104 #define MV88E61XX_GLOBAL_PRIORITY_MAP   (0x18)
  105 #define MV88E61XX_GLOBAL_MONITOR        (0x1a)
  106 #define MV88E61XX_GLOBAL_REMOTE_MGMT    (0x1c)
  107 #define MV88E61XX_GLOBAL_STATS          (0x1d)
  108 
  109 /*
  110  * Fields and values in each register.
  111  */
  112 #define MV88E61XX_GLOBAL_VTU_OP_BUSY            (0x8000)
  113 #define MV88E61XX_GLOBAL_VTU_OP_OP              (0x7000)
  114 #define MV88E61XX_GLOBAL_VTU_OP_OP_FLUSH        (0x1000)
  115 #define MV88E61XX_GLOBAL_VTU_OP_OP_VTU_LOAD     (0x3000)
  116 
  117 #define MV88E61XX_GLOBAL_VTU_VID_VALID          (0x1000)
  118 
  119 /*
  120  * Second global address & second global registers.
  121  */
  122 #define MV88E61XX_GLOBAL2       (0x1c)
  123 
  124 #define MV88E61XX_GLOBAL2_MANAGE_2X     (0x02)
  125 #define MV88E61XX_GLOBAL2_MANAGE_0X     (0x03)
  126 #define MV88E61XX_GLOBAL2_CONTROL2      (0x05)
  127 #define MV88E61XX_GLOBAL2_TRUNK_MASK    (0x07)
  128 #define MV88E61XX_GLOBAL2_TRUNK_MAP     (0x08)
  129 #define MV88E61XX_GLOBAL2_RATELIMIT     (0x09)
  130 #define MV88E61XX_GLOBAL2_VLAN_CONTROL  (0x0b)
  131 #define MV88E61XX_GLOBAL2_MAC_ADDRESS   (0x0d)
  132 
  133 /*
  134  * Fields and values in each register.
  135  */
  136 #define MV88E61XX_GLOBAL2_CONTROL2_DOUBLE_USE   (0x8000)
  137 #define MV88E61XX_GLOBAL2_CONTROL2_LOOP_PREVENT (0x4000)
  138 #define MV88E61XX_GLOBAL2_CONTROL2_FLOW_MESSAGE (0x2000)
  139 #define MV88E61XX_GLOBAL2_CONTROL2_FLOOD_BC     (0x1000)
  140 #define MV88E61XX_GLOBAL2_CONTROL2_REMOVE_PTAG  (0x0800)
  141 #define MV88E61XX_GLOBAL2_CONTROL2_AGE_INT      (0x0400)
  142 #define MV88E61XX_GLOBAL2_CONTROL2_FLOW_TAG     (0x0200)
  143 #define MV88E61XX_GLOBAL2_CONTROL2_ALWAYS_VTU   (0x0100)
  144 #define MV88E61XX_GLOBAL2_CONTROL2_FORCE_FC_PRI (0x0080)
  145 #define MV88E61XX_GLOBAL2_CONTROL2_FC_PRI       (0x0070)
  146 #define MV88E61XX_GLOBAL2_CONTROL2_MGMT_TO_HOST (0x0008)
  147 #define MV88E61XX_GLOBAL2_CONTROL2_MGMT_PRI     (0x0007)
  148 
  149 #endif /* !_MIPS_CAVIUM_OCTE_MV88E61XXPHYREG_H_ */

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