1 /***********************license start***************
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39 ***********************license end**************************************/
40
41 /*
42 * octeon_ebt3000_cf.c
43 *
44 */
45
46 #include <sys/cdefs.h>
47 __FBSDID("$FreeBSD$");
48
49 #include <sys/param.h>
50 #include <sys/bio.h>
51 #include <sys/systm.h>
52 #include <sys/sysctl.h>
53 #include <sys/ata.h>
54 #include <sys/bus.h>
55 #include <sys/kernel.h>
56 #include <sys/module.h>
57 #include <sys/rman.h>
58 #include <sys/power.h>
59 #include <sys/smp.h>
60 #include <sys/time.h>
61 #include <sys/timetc.h>
62 #include <sys/malloc.h>
63
64 #include <geom/geom.h>
65
66 #include <machine/clock.h>
67 #include <machine/locore.h>
68 #include <machine/md_var.h>
69 #include <machine/cpuregs.h>
70
71 #include <mips/cavium/octeon_pcmap_regs.h>
72
73 #include <contrib/octeon-sdk/cvmx.h>
74
75 /* ATA Commands */
76 #define CMD_READ_SECTOR 0x20
77 #define CMD_WRITE_SECTOR 0x30
78 #define CMD_IDENTIFY 0xEC
79
80 /* The ATA Task File */
81 #define TF_DATA 0x00
82 #define TF_ERROR 0x01
83 #define TF_PRECOMP 0x01
84 #define TF_SECTOR_COUNT 0x02
85 #define TF_SECTOR_NUMBER 0x03
86 #define TF_CYL_LSB 0x04
87 #define TF_CYL_MSB 0x05
88 #define TF_DRV_HEAD 0x06
89 #define TF_STATUS 0x07
90 #define TF_COMMAND 0x07
91
92 /* Status Register */
93 #define STATUS_BSY 0x80 /* Drive is busy */
94 #define STATUS_RDY 0x40 /* Drive is ready */
95 #define STATUS_DF 0x20 /* Device fault */
96 #define STATUS_DRQ 0x08 /* Data can be transferred */
97
98 /* Miscelaneous */
99 #define SECTOR_SIZE 512
100 #define WAIT_DELAY 1000
101 #define NR_TRIES 1000
102 #define SWAP_SHORT(x) ((x << 8) | (x >> 8))
103 #define MODEL_STR_SIZE 40
104
105 /* Globals */
106 /*
107 * There's three bus types supported by this driver.
108 *
109 * CF_8 -- Traditional PC Card IDE interface on an 8-bit wide bus. We assume
110 * the bool loader has configure attribute memory properly. We then access
111 * the device like old-school 8-bit IDE card (which is all a traditional PC Card
112 * interface really is).
113 * CF_16 -- Traditional PC Card IDE interface on a 16-bit wide bus. Registers on
114 * this bus are 16-bits wide too. When accessing registers in the task file, you
115 * have to do it in 16-bit chunks, and worry about masking out what you don't want
116 * or ORing together the traditional 8-bit values. We assume the bootloader does
117 * the right attribute memory initialization dance.
118 * CF_TRUE_IDE_8 - CF Card wired to True IDE mode. There's no Attribute memory
119 * space at all. Instead all the traditional 8-bit registers are there, but
120 * on a 16-bit bus where addr0 isn't wired. This means we need to read/write them
121 * 16-bit chunks, but only the lower 8 bits are valid. We do not (and can not)
122 * access this like CF_16 with the comingled registers. Yet we can't access
123 * this like CF_8 because of the register offset. Except the TF_DATA register
124 * appears to be full width?
125 */
126 void *base_addr;
127 int bus_type;
128 #define CF_8 1 /* 8-bit bus, no offsets - PC Card */
129 #define CF_16 2 /* 16-bit bus, registers shared - PC Card */
130 #define CF_TRUE_IDE_8 3 /* 16-bit bus, only lower 8-bits, TrueIDE */
131 const char *const cf_type[] = {
132 "impossible type",
133 "CF 8-bit",
134 "CF 16-bit",
135 "True IDE"
136 };
137
138 /* Device parameters */
139 struct drive_param{
140 union {
141 char buf[SECTOR_SIZE];
142 struct ata_params driveid;
143 } u;
144
145 char model[MODEL_STR_SIZE];
146 uint32_t nr_sectors;
147 uint16_t sector_size;
148 uint16_t heads;
149 uint16_t tracks;
150 uint16_t sec_track;
151 };
152
153 /* Device softc */
154 struct cf_priv {
155 device_t dev;
156 struct drive_param drive_param;
157
158 struct bio_queue_head cf_bq;
159 struct g_geom *cf_geom;
160 struct g_provider *cf_provider;
161
162 };
163
164 /* GEOM class implementation */
165 static g_access_t cf_access;
166 static g_start_t cf_start;
167 static g_ioctl_t cf_ioctl;
168
169 struct g_class g_cf_class = {
170 .name = "CF",
171 .version = G_VERSION,
172 .start = cf_start,
173 .access = cf_access,
174 .ioctl = cf_ioctl,
175 };
176
177 DECLARE_GEOM_CLASS(g_cf_class, g_cf);
178
179 /* Device methods */
180 static int cf_probe(device_t);
181 static void cf_identify(driver_t *, device_t);
182 static int cf_attach(device_t);
183 static void cf_attach_geom(void *, int);
184
185 /* ATA methods */
186 static int cf_cmd_identify(struct cf_priv *);
187 static int cf_cmd_write(uint32_t, uint32_t, void *);
188 static int cf_cmd_read(uint32_t, uint32_t, void *);
189 static int cf_wait_busy(void);
190 static int cf_send_cmd(uint32_t, uint8_t);
191
192 /* Miscelenous */
193 static void cf_swap_ascii(unsigned char[], char[]);
194
195 /* ------------------------------------------------------------------- *
196 * cf_access() *
197 * ------------------------------------------------------------------- */
198 static int cf_access (struct g_provider *pp, int r, int w, int e)
199 {
200 return (0);
201 }
202
203 /* ------------------------------------------------------------------- *
204 * cf_start() *
205 * ------------------------------------------------------------------- */
206 static void cf_start (struct bio *bp)
207 {
208 struct cf_priv *cf_priv;
209 int error;
210
211 cf_priv = bp->bio_to->geom->softc;
212
213 /*
214 * Handle actual I/O requests. The request is passed down through
215 * the bio struct.
216 */
217
218 switch (bp->bio_cmd) {
219 case BIO_GETATTR:
220 if (g_handleattr_int(bp, "GEOM::fwsectors", cf_priv->drive_param.sec_track))
221 return;
222 if (g_handleattr_int(bp, "GEOM::fwheads", cf_priv->drive_param.heads))
223 return;
224 g_io_deliver(bp, ENOIOCTL);
225 return;
226
227 case BIO_READ:
228 error = cf_cmd_read(bp->bio_length / cf_priv->drive_param.sector_size,
229 bp->bio_offset / cf_priv->drive_param.sector_size, bp->bio_data);
230 break;
231 case BIO_WRITE:
232 error = cf_cmd_write(bp->bio_length / cf_priv->drive_param.sector_size,
233 bp->bio_offset/cf_priv->drive_param.sector_size, bp->bio_data);
234 break;
235
236 default:
237 printf("%s: unrecognized bio_cmd %x.\n", __func__, bp->bio_cmd);
238 error = ENOTSUP;
239 break;
240 }
241
242 if (error != 0) {
243 g_io_deliver(bp, error);
244 return;
245 }
246
247 bp->bio_resid = 0;
248 bp->bio_completed = bp->bio_length;
249 g_io_deliver(bp, 0);
250 }
251
252 static int cf_ioctl (struct g_provider *pp, u_long cmd, void *data, int fflag, struct thread *td)
253 {
254 return (0);
255 }
256
257 static uint8_t cf_inb_8(int port)
258 {
259 /*
260 * Traditional 8-bit PC Card/CF bus access.
261 */
262 if (bus_type == CF_8) {
263 volatile uint8_t *task_file = (volatile uint8_t *)base_addr;
264 return task_file[port];
265 }
266
267 /*
268 * True IDE access. lower 8 bits on a 16-bit bus (see above).
269 */
270 volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
271 return task_file[port] & 0xff;
272 }
273
274 static void cf_outb_8(int port, uint8_t val)
275 {
276 /*
277 * Traditional 8-bit PC Card/CF bus access.
278 */
279 if (bus_type == CF_8) {
280 volatile uint8_t *task_file = (volatile uint8_t *)base_addr;
281 task_file[port] = val;
282 return;
283 }
284
285 /*
286 * True IDE access. lower 8 bits on a 16-bit bus (see above).
287 */
288 volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
289 task_file[port] = val & 0xff;
290 }
291
292 static uint8_t cf_inb_16(int port)
293 {
294 volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
295 uint16_t val = task_file[port / 2];
296 if (port & 1)
297 return (val >> 8) & 0xff;
298 return val & 0xff;
299 }
300
301 static uint16_t cf_inw_16(int port)
302 {
303 volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
304 uint16_t val = task_file[port / 2];
305 return val;
306 }
307
308 static void cf_outw_16(int port, uint16_t val)
309 {
310 volatile uint16_t *task_file = (volatile uint16_t *)base_addr;
311 task_file[port / 2] = val;
312 }
313
314 /* ------------------------------------------------------------------- *
315 * cf_cmd_read() *
316 * ------------------------------------------------------------------- *
317 *
318 * Read nr_sectors from the device starting from start_sector.
319 */
320 static int cf_cmd_read (uint32_t nr_sectors, uint32_t start_sector, void *buf)
321 {
322 unsigned long lba;
323 uint32_t count;
324 uint16_t *ptr_16;
325 uint8_t *ptr_8;
326 int error;
327
328 ptr_8 = (uint8_t*)buf;
329 ptr_16 = (uint16_t*)buf;
330 lba = start_sector;
331
332 while (nr_sectors--) {
333 error = cf_send_cmd(lba, CMD_READ_SECTOR);
334 if (error != 0) {
335 printf("%s: cf_send_cmd(CMD_READ_SECTOR) failed: %d\n", __func__, error);
336 return (error);
337 }
338
339 switch (bus_type)
340 {
341 case CF_8:
342 for (count = 0; count < SECTOR_SIZE; count++) {
343 *ptr_8++ = cf_inb_8(TF_DATA);
344 if ((count & 0xf) == 0)
345 (void)cf_inb_8(TF_STATUS);
346 }
347 break;
348 case CF_TRUE_IDE_8:
349 case CF_16:
350 default:
351 for (count = 0; count < SECTOR_SIZE; count+=2) {
352 uint16_t temp;
353 temp = cf_inw_16(TF_DATA);
354 *ptr_16++ = SWAP_SHORT(temp);
355 if ((count & 0xf) == 0)
356 (void)cf_inb_16(TF_STATUS);
357 }
358 break;
359 }
360
361 lba++;
362 }
363 return (0);
364 }
365
366 /* ------------------------------------------------------------------- *
367 * cf_cmd_write() *
368 * ------------------------------------------------------------------- *
369 *
370 * Write nr_sectors to the device starting from start_sector.
371 */
372 static int cf_cmd_write (uint32_t nr_sectors, uint32_t start_sector, void *buf)
373 {
374 uint32_t lba;
375 uint32_t count;
376 uint16_t *ptr_16;
377 uint8_t *ptr_8;
378 int error;
379
380 lba = start_sector;
381 ptr_8 = (uint8_t*)buf;
382 ptr_16 = (uint16_t*)buf;
383
384 while (nr_sectors--) {
385 error = cf_send_cmd(lba, CMD_WRITE_SECTOR);
386 if (error != 0) {
387 printf("%s: cf_send_cmd(CMD_WRITE_SECTOR) failed: %d\n", __func__, error);
388 return (error);
389 }
390
391 switch (bus_type)
392 {
393 case CF_8:
394 for (count = 0; count < SECTOR_SIZE; count++) {
395 cf_outb_8(TF_DATA, *ptr_8++);
396 if ((count & 0xf) == 0)
397 (void)cf_inb_8(TF_STATUS);
398 }
399 break;
400 case CF_TRUE_IDE_8:
401 case CF_16:
402 default:
403 for (count = 0; count < SECTOR_SIZE; count+=2) {
404 uint16_t temp = *ptr_16++;
405 cf_outw_16(TF_DATA, SWAP_SHORT(temp));
406 if ((count & 0xf) == 0)
407 (void)cf_inb_16(TF_STATUS);
408 }
409 break;
410 }
411
412 lba++;
413 }
414 return (0);
415 }
416
417 /* ------------------------------------------------------------------- *
418 * cf_cmd_identify() *
419 * ------------------------------------------------------------------- *
420 *
421 * Read parameters and other information from the drive and store
422 * it in the drive_param structure
423 *
424 */
425 static int cf_cmd_identify(struct cf_priv *cf_priv)
426 {
427 int count;
428 int error;
429
430 error = cf_send_cmd(0, CMD_IDENTIFY);
431 if (error != 0) {
432 printf("%s: identify failed: %d\n", __func__, error);
433 return (error);
434 }
435 switch (bus_type)
436 {
437 case CF_8:
438 for (count = 0; count < SECTOR_SIZE; count++)
439 cf_priv->drive_param.u.buf[count] = cf_inb_8(TF_DATA);
440 break;
441 case CF_TRUE_IDE_8:
442 case CF_16:
443 default:
444 for (count = 0; count < SECTOR_SIZE; count += 2) {
445 uint16_t temp;
446 temp = cf_inw_16(TF_DATA);
447
448 /* endianess will be swapped below */
449 cf_priv->drive_param.u.buf[count] = (temp & 0xff);
450 cf_priv->drive_param.u.buf[count + 1] = (temp & 0xff00) >> 8;
451 }
452 break;
453 }
454
455 cf_swap_ascii(cf_priv->drive_param.u.driveid.model, cf_priv->drive_param.model);
456
457 cf_priv->drive_param.sector_size = 512; //= SWAP_SHORT (cf_priv->drive_param.u.driveid.sector_bytes);
458 cf_priv->drive_param.heads = SWAP_SHORT (cf_priv->drive_param.u.driveid.current_heads);
459 cf_priv->drive_param.tracks = SWAP_SHORT (cf_priv->drive_param.u.driveid.current_cylinders);
460 cf_priv->drive_param.sec_track = SWAP_SHORT (cf_priv->drive_param.u.driveid.current_sectors);
461 cf_priv->drive_param.nr_sectors = (uint32_t)SWAP_SHORT (cf_priv->drive_param.u.driveid.lba_size_1) |
462 ((uint32_t)SWAP_SHORT (cf_priv->drive_param.u.driveid.lba_size_2));
463 if (bootverbose) {
464 printf(" model %s\n", cf_priv->drive_param.model);
465 printf(" heads %d tracks %d sec_tracks %d sectors %d\n",
466 cf_priv->drive_param.heads, cf_priv->drive_param.tracks,
467 cf_priv->drive_param.sec_track, cf_priv->drive_param.nr_sectors);
468 }
469
470 return (0);
471 }
472
473 /* ------------------------------------------------------------------- *
474 * cf_send_cmd() *
475 * ------------------------------------------------------------------- *
476 *
477 * Send command to read/write one sector specified by lba.
478 *
479 */
480 static int cf_send_cmd (uint32_t lba, uint8_t cmd)
481 {
482 switch (bus_type)
483 {
484 case CF_8:
485 case CF_TRUE_IDE_8:
486 while (cf_inb_8(TF_STATUS) & STATUS_BSY)
487 DELAY(WAIT_DELAY);
488 cf_outb_8(TF_SECTOR_COUNT, 1);
489 cf_outb_8(TF_SECTOR_NUMBER, lba & 0xff);
490 cf_outb_8(TF_CYL_LSB, (lba >> 8) & 0xff);
491 cf_outb_8(TF_CYL_MSB, (lba >> 16) & 0xff);
492 cf_outb_8(TF_DRV_HEAD, ((lba >> 24) & 0xff) | 0xe0);
493 cf_outb_8(TF_COMMAND, cmd);
494 break;
495 case CF_16:
496 default:
497 while (cf_inb_16(TF_STATUS) & STATUS_BSY)
498 DELAY(WAIT_DELAY);
499 cf_outw_16(TF_SECTOR_COUNT, 1 | ((lba & 0xff) << 8));
500 cf_outw_16(TF_CYL_LSB, ((lba >> 8) & 0xff) | (((lba >> 16) & 0xff) << 8));
501 cf_outw_16(TF_DRV_HEAD, (((lba >> 24) & 0xff) | 0xe0) | (cmd << 8));
502 break;
503 }
504
505 return (cf_wait_busy());
506 }
507
508 /* ------------------------------------------------------------------- *
509 * cf_wait_busy() *
510 * ------------------------------------------------------------------- *
511 *
512 * Wait until the drive finishes a given command and data is
513 * ready to be transferred. This is done by repeatedly checking
514 * the BSY bit of the status register. When the controller is ready for
515 * data transfer, it clears the BSY bit and sets the DRQ bit.
516 *
517 * If the DF bit is ever set, we return error.
518 *
519 * This code originally spun on DRQ. If that behavior turns out to be
520 * necessary, a flag can be added or this function can be called
521 * repeatedly as long as it is returning ENXIO.
522 */
523 static int cf_wait_busy (void)
524 {
525 uint8_t status;
526
527 switch (bus_type)
528 {
529 case CF_8:
530 case CF_TRUE_IDE_8:
531 status = cf_inb_8(TF_STATUS);
532 while ((status & STATUS_BSY) == STATUS_BSY) {
533 if ((status & STATUS_DF) != 0) {
534 printf("%s: device fault (status=%x)\n", __func__, status);
535 return (EIO);
536 }
537 DELAY(WAIT_DELAY);
538 status = cf_inb_8(TF_STATUS);
539 }
540 break;
541 case CF_16:
542 default:
543 status = cf_inb_16(TF_STATUS);
544 while ((status & STATUS_BSY) == STATUS_BSY) {
545 if ((status & STATUS_DF) != 0) {
546 printf("%s: device fault (status=%x)\n", __func__, status);
547 return (EIO);
548 }
549 DELAY(WAIT_DELAY);
550 status = cf_inb_16(TF_STATUS);
551 }
552 break;
553 }
554
555 /* DRQ is only for when read data is actually available; check BSY */
556 /* Some vendors do assert DRQ, but not all. Check BSY instead. */
557 if (status & STATUS_BSY) {
558 printf("%s: device not ready (status=%x)\n", __func__, status);
559 return (ENXIO);
560 }
561
562 return (0);
563 }
564
565 /* ------------------------------------------------------------------- *
566 * cf_swap_ascii() *
567 * ------------------------------------------------------------------- *
568 *
569 * The ascii string returned by the controller specifying
570 * the model of the drive is byte-swaped. This routine
571 * corrects the byte ordering.
572 *
573 */
574 static void cf_swap_ascii (unsigned char str1[], char str2[])
575 {
576 int i;
577
578 for(i = 0; i < MODEL_STR_SIZE; i++)
579 str2[i] = str1[i ^ 1];
580 }
581
582 /* ------------------------------------------------------------------- *
583 * cf_probe() *
584 * ------------------------------------------------------------------- */
585
586 static int cf_probe (device_t dev)
587 {
588 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
589 return (ENXIO);
590
591 if (device_get_unit(dev) != 0) {
592 panic("can't attach more devices\n");
593 }
594
595 device_set_desc(dev, "Octeon Compact Flash Driver");
596
597 return (BUS_PROBE_NOWILDCARD);
598 }
599
600 /* ------------------------------------------------------------------- *
601 * cf_identify() *
602 * ------------------------------------------------------------------- *
603 *
604 * Find the bootbus region for the CF to determine
605 * 16 or 8 bit and check to see if device is
606 * inserted.
607 *
608 */
609 static void cf_identify (driver_t *drv, device_t parent)
610 {
611 int bus_region;
612 int count = 0;
613 cvmx_mio_boot_reg_cfgx_t cfg;
614 uint64_t phys_base;
615
616 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
617 return;
618
619 phys_base = cvmx_sysinfo_get()->compact_flash_common_base_addr;
620 if (phys_base == 0)
621 return;
622 base_addr = cvmx_phys_to_ptr(phys_base);
623
624 for (bus_region = 0; bus_region < 8; bus_region++)
625 {
626 cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(bus_region));
627 if (cfg.s.base == phys_base >> 16)
628 {
629 if (cvmx_sysinfo_get()->compact_flash_attribute_base_addr == 0)
630 bus_type = CF_TRUE_IDE_8;
631 else
632 bus_type = (cfg.s.width) ? CF_16 : CF_8;
633 printf("Compact flash found in bootbus region %d (%s).\n", bus_region, cf_type[bus_type]);
634 break;
635 }
636 }
637
638 switch (bus_type)
639 {
640 case CF_8:
641 case CF_TRUE_IDE_8:
642 /* Check if CF is inserted */
643 while (cf_inb_8(TF_STATUS) & STATUS_BSY) {
644 if ((count++) == NR_TRIES ) {
645 printf("Compact Flash not present\n");
646 return;
647 }
648 DELAY(WAIT_DELAY);
649 }
650 break;
651 case CF_16:
652 default:
653 /* Check if CF is inserted */
654 while (cf_inb_16(TF_STATUS) & STATUS_BSY) {
655 if ((count++) == NR_TRIES ) {
656 printf("Compact Flash not present\n");
657 return;
658 }
659 DELAY(WAIT_DELAY);
660 }
661 break;
662 }
663
664 BUS_ADD_CHILD(parent, 0, "cf", 0);
665 }
666
667 /* ------------------------------------------------------------------- *
668 * cf_attach_geom() *
669 * ------------------------------------------------------------------- */
670
671 static void cf_attach_geom (void *arg, int flag)
672 {
673 struct cf_priv *cf_priv;
674
675 cf_priv = (struct cf_priv *) arg;
676 cf_priv->cf_geom = g_new_geomf(&g_cf_class, "cf%d", device_get_unit(cf_priv->dev));
677 cf_priv->cf_geom->softc = cf_priv;
678 cf_priv->cf_provider = g_new_providerf(cf_priv->cf_geom, "%s",
679 cf_priv->cf_geom->name);
680 cf_priv->cf_provider->sectorsize = cf_priv->drive_param.sector_size;
681 cf_priv->cf_provider->mediasize = cf_priv->drive_param.nr_sectors * cf_priv->cf_provider->sectorsize;
682 g_error_provider(cf_priv->cf_provider, 0);
683 }
684
685 /* ------------------------------------------------------------------- *
686 * cf_attach() *
687 * ------------------------------------------------------------------- */
688
689 static int cf_attach (device_t dev)
690 {
691 struct cf_priv *cf_priv;
692 int error;
693
694 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM)
695 return (ENXIO);
696
697 cf_priv = device_get_softc(dev);
698 cf_priv->dev = dev;
699
700 error = cf_cmd_identify(cf_priv);
701 if (error != 0) {
702 device_printf(dev, "cf_cmd_identify failed: %d\n", error);
703 return (error);
704 }
705
706 g_post_event(cf_attach_geom, cf_priv, M_WAITOK, NULL);
707 bioq_init(&cf_priv->cf_bq);
708
709 return 0;
710 }
711
712 static device_method_t cf_methods[] = {
713 /* Device interface */
714 DEVMETHOD(device_probe, cf_probe),
715 DEVMETHOD(device_identify, cf_identify),
716 DEVMETHOD(device_attach, cf_attach),
717 DEVMETHOD(device_detach, bus_generic_detach),
718 DEVMETHOD(device_shutdown, bus_generic_shutdown),
719 { 0, 0 }
720 };
721
722 static driver_t cf_driver = {
723 "cf",
724 cf_methods,
725 sizeof(struct cf_priv)
726 };
727
728 static devclass_t cf_devclass;
729
730 DRIVER_MODULE(cf, nexus, cf_driver, cf_devclass, 0, 0);
Cache object: 35b91ab1622c2a0af1fe3d99b378e68a
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