1 /*-
2 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: releng/10.1/sys/mips/cavium/octeon_machdep.c 247297 2013-02-26 01:00:11Z attilio $
27 */
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD: releng/10.1/sys/mips/cavium/octeon_machdep.c 247297 2013-02-26 01:00:11Z attilio $");
30
31 #include <sys/param.h>
32 #include <sys/conf.h>
33 #include <sys/kernel.h>
34 #include <sys/systm.h>
35 #include <sys/imgact.h>
36 #include <sys/bio.h>
37 #include <sys/buf.h>
38 #include <sys/bus.h>
39 #include <sys/cpu.h>
40 #include <sys/cons.h>
41 #include <sys/exec.h>
42 #include <sys/ucontext.h>
43 #include <sys/proc.h>
44 #include <sys/kdb.h>
45 #include <sys/ptrace.h>
46 #include <sys/reboot.h>
47 #include <sys/signalvar.h>
48 #include <sys/sysctl.h>
49 #include <sys/sysent.h>
50 #include <sys/sysproto.h>
51 #include <sys/time.h>
52 #include <sys/timetc.h>
53 #include <sys/user.h>
54
55 #include <vm/vm.h>
56 #include <vm/vm_object.h>
57 #include <vm/vm_page.h>
58
59 #include <machine/atomic.h>
60 #include <machine/cache.h>
61 #include <machine/clock.h>
62 #include <machine/cpu.h>
63 #include <machine/cpuregs.h>
64 #include <machine/cpufunc.h>
65 #include <mips/cavium/octeon_pcmap_regs.h>
66 #include <machine/hwfunc.h>
67 #include <machine/intr_machdep.h>
68 #include <machine/locore.h>
69 #include <machine/md_var.h>
70 #include <machine/pcpu.h>
71 #include <machine/pte.h>
72 #include <machine/trap.h>
73 #include <machine/vmparam.h>
74
75 #include <contrib/octeon-sdk/cvmx.h>
76 #include <contrib/octeon-sdk/cvmx-bootmem.h>
77 #include <contrib/octeon-sdk/cvmx-ebt3000.h>
78 #include <contrib/octeon-sdk/cvmx-helper-cfg.h>
79 #include <contrib/octeon-sdk/cvmx-interrupt.h>
80 #include <contrib/octeon-sdk/cvmx-version.h>
81
82 #include <mips/cavium/octeon_irq.h>
83
84 #if defined(__mips_n64)
85 #define MAX_APP_DESC_ADDR 0xffffffffafffffff
86 #else
87 #define MAX_APP_DESC_ADDR 0xafffffff
88 #endif
89
90 struct octeon_feature_description {
91 octeon_feature_t ofd_feature;
92 const char *ofd_string;
93 };
94
95 extern int *end;
96 extern char cpu_model[];
97 extern char cpu_board[];
98
99 static const struct octeon_feature_description octeon_feature_descriptions[] = {
100 { OCTEON_FEATURE_SAAD, "SAAD" },
101 { OCTEON_FEATURE_ZIP, "ZIP" },
102 { OCTEON_FEATURE_CRYPTO, "CRYPTO" },
103 { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" },
104 { OCTEON_FEATURE_PCIE, "PCIE" },
105 { OCTEON_FEATURE_SRIO, "SRIO" },
106 { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" },
107 { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" },
108 { OCTEON_FEATURE_TRA, "TRA" },
109 { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" },
110 { OCTEON_FEATURE_RAID, "RAID" },
111 { OCTEON_FEATURE_USB, "USB" },
112 { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" },
113 { OCTEON_FEATURE_DFA, "DFA" },
114 { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" },
115 { OCTEON_FEATURE_NPEI, "NPEI" },
116 { OCTEON_FEATURE_ILK, "ILK" },
117 { OCTEON_FEATURE_HFA, "HFA" },
118 { OCTEON_FEATURE_DFM, "DFM" },
119 { OCTEON_FEATURE_CIU2, "CIU2" },
120 { OCTEON_FEATURE_DICI_MODE, "DICI_MODE" },
121 { OCTEON_FEATURE_BIT_EXTRACTOR, "BIT_EXTRACTOR" },
122 { OCTEON_FEATURE_NAND, "NAND" },
123 { OCTEON_FEATURE_MMC, "MMC" },
124 { OCTEON_FEATURE_PKND, "PKND" },
125 { OCTEON_FEATURE_CN68XX_WQE, "CN68XX_WQE" },
126 { 0, NULL }
127 };
128
129 static uint64_t octeon_get_ticks(void);
130 static unsigned octeon_get_timecount(struct timecounter *tc);
131
132 static void octeon_boot_params_init(register_t ptr);
133
134 static struct timecounter octeon_timecounter = {
135 octeon_get_timecount, /* get_timecount */
136 0, /* no poll_pps */
137 0xffffffffu, /* octeon_mask */
138 0, /* frequency */
139 "Octeon", /* name */
140 900, /* quality (adjusted in code) */
141 };
142
143 void
144 platform_cpu_init()
145 {
146 /* Nothing special yet */
147 }
148
149 /*
150 * Perform a board-level soft-reset.
151 */
152 void
153 platform_reset(void)
154 {
155 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
156 }
157
158 /*
159 * octeon_debug_symbol
160 *
161 * Does nothing.
162 * Used to mark the point for simulator to begin tracing
163 */
164 void
165 octeon_debug_symbol(void)
166 {
167 }
168
169 /*
170 * octeon_ciu_reset
171 *
172 * Shutdown all CIU to IP2, IP3 mappings
173 */
174 void
175 octeon_ciu_reset(void)
176 {
177 uint64_t cvmctl;
178
179 /* Disable all CIU interrupts by default */
180 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
181 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
182 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
183 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
184
185 #ifdef SMP
186 /* Enable the MBOX interrupts. */
187 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1),
188 (1ull << (OCTEON_IRQ_MBOX0 - 8)) |
189 (1ull << (OCTEON_IRQ_MBOX1 - 8)));
190 #endif
191
192 /*
193 * Move the Performance Counter interrupt to OCTEON_PMC_IRQ
194 */
195 cvmctl = mips_rd_cvmctl();
196 cvmctl &= ~(7 << 7);
197 cvmctl |= (OCTEON_PMC_IRQ + 2) << 7;
198 mips_wr_cvmctl(cvmctl);
199 }
200
201 static void
202 octeon_memory_init(void)
203 {
204 vm_paddr_t phys_end;
205 int64_t addr;
206 unsigned i, j;
207
208 phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end));
209
210 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) {
211 /* Simulator we limit to 96 meg */
212 phys_avail[0] = phys_end;
213 phys_avail[1] = 96 << 20;
214
215 dump_avail[0] = phys_avail[0];
216 dump_avail[1] = phys_avail[1];
217
218 realmem = physmem = btoc(phys_avail[1] - phys_avail[0]);
219 return;
220 }
221
222 /*
223 * Allocate memory from bootmem 1MB at a time and merge
224 * adjacent entries.
225 */
226 i = 0;
227 while (i < PHYS_AVAIL_ENTRIES) {
228 /*
229 * If there is less than 2MB of memory available in 128-byte
230 * blocks, do not steal any more memory. We need to leave some
231 * memory for the command queues to be allocated out of.
232 */
233 if (cvmx_bootmem_available_mem(128) < 2 << 20)
234 break;
235
236 addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end,
237 ~(vm_paddr_t)0, PAGE_SIZE, 0);
238 if (addr == -1)
239 break;
240
241 /*
242 * The SDK needs to be able to easily map any memory that might
243 * come to it e.g. in the form of an mbuf. Because on !n64 we
244 * can't direct-map some addresses and we don't want to manage
245 * temporary mappings within the SDK, don't feed memory that
246 * can't be direct-mapped to the kernel.
247 */
248 #if !defined(__mips_n64)
249 if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1))
250 continue;
251 #endif
252
253 physmem += btoc(1 << 20);
254
255 if (i > 0 && phys_avail[i - 1] == addr) {
256 phys_avail[i - 1] += 1 << 20;
257 continue;
258 }
259
260 phys_avail[i + 0] = addr;
261 phys_avail[i + 1] = addr + (1 << 20);
262
263 i += 2;
264 }
265
266 for (j = 0; j < i; j++)
267 dump_avail[j] = phys_avail[j];
268
269 realmem = physmem;
270 }
271
272 void
273 platform_start(__register_t a0, __register_t a1, __register_t a2 __unused,
274 __register_t a3)
275 {
276 const struct octeon_feature_description *ofd;
277 uint64_t platform_counter_freq;
278 int rv;
279
280 mips_postboot_fixup();
281
282 /*
283 * Initialize boot parameters so that we can determine things like
284 * which console we shoud use, etc.
285 */
286 octeon_boot_params_init(a3);
287
288 /* Initialize pcpu stuff */
289 mips_pcpu0_init();
290 mips_timer_early_init(cvmx_sysinfo_get()->cpu_clock_hz);
291
292 /* Initialize console. */
293 cninit();
294
295 /*
296 * Display information about the CPU.
297 */
298 #if !defined(OCTEON_MODEL)
299 printf("Using runtime CPU model checks.\n");
300 #else
301 printf("Compiled for CPU model: " __XSTRING(OCTEON_MODEL) "\n");
302 #endif
303 strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id()));
304 printf("CPU Model: %s\n", cpu_model);
305 printf("CPU clock: %uMHz Core Mask: %#x\n",
306 cvmx_sysinfo_get()->cpu_clock_hz / 1000000,
307 cvmx_sysinfo_get()->core_mask);
308 rv = octeon_model_version_check(cvmx_get_proc_id());
309 if (rv == -1)
310 panic("%s: kernel not compatible with this processor.", __func__);
311
312 /*
313 * Display information about the board.
314 */
315 #if defined(OCTEON_BOARD_CAPK_0100ND)
316 strcpy(cpu_board, "CAPK-0100ND");
317 if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) {
318 panic("Compiled for %s, but board type is %s.", cpu_board,
319 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
320 }
321 #else
322 strcpy(cpu_board,
323 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
324 #endif
325 printf("Board: %s\n", cpu_board);
326 printf("Board Type: %u Revision: %u/%u\n",
327 cvmx_sysinfo_get()->board_type,
328 cvmx_sysinfo_get()->board_rev_major,
329 cvmx_sysinfo_get()->board_rev_minor);
330 printf("Serial number: %s\n", cvmx_sysinfo_get()->board_serial_number);
331
332 /*
333 * Additional on-chip hardware/settings.
334 *
335 * XXX Display PCI host/target? What else?
336 */
337 printf("MAC address base: %6D (%u configured)\n",
338 cvmx_sysinfo_get()->mac_addr_base, ":",
339 cvmx_sysinfo_get()->mac_addr_count);
340
341
342 octeon_ciu_reset();
343 /*
344 * XXX
345 * We can certainly parse command line arguments or U-Boot environment
346 * to determine whether to bootverbose / single user / ... I think
347 * stass has patches to add support for loader things to U-Boot even.
348 */
349 bootverbose = 1;
350
351 /*
352 * For some reason on the cn38xx simulator ebase register is set to
353 * 0x80001000 at bootup time. Move it back to the default, but
354 * when we move to having support for multiple executives, we need
355 * to rethink this.
356 */
357 mips_wr_ebase(0x80000000);
358
359 octeon_memory_init();
360 init_param1();
361 init_param2(physmem);
362 mips_cpu_init();
363 pmap_bootstrap();
364 mips_proc0_init();
365 mutex_init();
366 kdb_init();
367 #ifdef KDB
368 if (boothowto & RB_KDB)
369 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
370 #endif
371 cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz;
372 platform_counter_freq = cpu_clock;
373 octeon_timecounter.tc_frequency = cpu_clock;
374 platform_timecounter = &octeon_timecounter;
375 mips_timer_init_params(platform_counter_freq, 0);
376 set_cputicker(octeon_get_ticks, cpu_clock, 0);
377
378 #ifdef SMP
379 /*
380 * Clear any pending IPIs.
381 */
382 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff);
383 #endif
384
385 printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING);
386 printf("Available Octeon features:");
387 for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++)
388 if (octeon_has_feature(ofd->ofd_feature))
389 printf(" %s", ofd->ofd_string);
390 printf("\n");
391 }
392
393 static uint64_t
394 octeon_get_ticks(void)
395 {
396 uint64_t cvmcount;
397
398 CVMX_MF_CYCLE(cvmcount);
399 return (cvmcount);
400 }
401
402 static unsigned
403 octeon_get_timecount(struct timecounter *tc)
404 {
405 return ((unsigned)octeon_get_ticks());
406 }
407
408 static int
409 sysctl_machdep_led_display(SYSCTL_HANDLER_ARGS)
410 {
411 size_t buflen;
412 char buf[9];
413 int error;
414
415 if (req->newptr == NULL)
416 return (EINVAL);
417
418 if (cvmx_sysinfo_get()->led_display_base_addr == 0)
419 return (ENODEV);
420
421 /*
422 * Revision 1.x of the EBT3000 only supports 4 characters, but
423 * other devices support 8.
424 */
425 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 &&
426 cvmx_sysinfo_get()->board_rev_major == 1)
427 buflen = 4;
428 else
429 buflen = 8;
430
431 if (req->newlen > buflen)
432 return (E2BIG);
433
434 error = SYSCTL_IN(req, buf, req->newlen);
435 if (error != 0)
436 return (error);
437
438 buf[req->newlen] = '\0';
439 ebt3000_str_write(buf);
440
441 return (0);
442 }
443
444 SYSCTL_PROC(_machdep, OID_AUTO, led_display, CTLTYPE_STRING | CTLFLAG_WR,
445 NULL, 0, sysctl_machdep_led_display, "A",
446 "String to display on LED display");
447
448 void
449 cvmx_dvprintf(const char *fmt, va_list ap)
450 {
451 if (!bootverbose)
452 return;
453 vprintf(fmt, ap);
454 }
455
456 void
457 cvmx_dprintf(const char *fmt, ...)
458 {
459 va_list ap;
460
461 va_start(ap, fmt);
462 cvmx_dvprintf(fmt, ap);
463 va_end(ap);
464 }
465
466 /**
467 * version of printf that works better in exception context.
468 *
469 * @param format
470 *
471 * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version.
472 */
473 void cvmx_safe_printf(const char *format, ...)
474 {
475 char buffer[256];
476 char *ptr = buffer;
477 int count;
478 va_list args;
479
480 va_start(args, format);
481 #ifndef __U_BOOT__
482 count = vsnprintf(buffer, sizeof(buffer), format, args);
483 #else
484 count = vsprintf(buffer, format, args);
485 #endif
486 va_end(args);
487
488 while (count-- > 0)
489 {
490 cvmx_uart_lsr_t lsrval;
491
492 /* Spin until there is room */
493 do
494 {
495 lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0));
496 #if !defined(CONFIG_OCTEON_SIM_SPEED)
497 if (lsrval.s.temt == 0)
498 cvmx_wait(10000); /* Just to reduce the load on the system */
499 #endif
500 }
501 while (lsrval.s.temt == 0);
502
503 if (*ptr == '\n')
504 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r');
505 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++);
506 }
507 }
508
509 /* impSTART: This stuff should move back into the Cavium SDK */
510 /*
511 ****************************************************************************************
512 *
513 * APP/BOOT DESCRIPTOR STUFF
514 *
515 ****************************************************************************************
516 */
517
518 /* Define the struct that is initialized by the bootloader used by the
519 * startup code.
520 *
521 * Copyright (c) 2004, 2005, 2006 Cavium Networks.
522 *
523 * The authors hereby grant permission to use, copy, modify, distribute,
524 * and license this software and its documentation for any purpose, provided
525 * that existing copyright notices are retained in all copies and that this
526 * notice is included verbatim in any distributions. No written agreement,
527 * license, or royalty fee is required for any of the authorized uses.
528 * Modifications to this software may be copyrighted by their authors
529 * and need not follow the licensing terms described here, provided that
530 * the new terms are clearly indicated on the first page of each file where
531 * they apply.
532 */
533
534 #define OCTEON_CURRENT_DESC_VERSION 6
535 #define OCTEON_ARGV_MAX_ARGS (64)
536 #define OCTOEN_SERIAL_LEN 20
537
538 typedef struct {
539 /* Start of block referenced by assembly code - do not change! */
540 uint32_t desc_version;
541 uint32_t desc_size;
542
543 uint64_t stack_top;
544 uint64_t heap_base;
545 uint64_t heap_end;
546 uint64_t entry_point; /* Only used by bootloader */
547 uint64_t desc_vaddr;
548 /* End of This block referenced by assembly code - do not change! */
549
550 uint32_t exception_base_addr;
551 uint32_t stack_size;
552 uint32_t heap_size;
553 uint32_t argc; /* Argc count for application */
554 uint32_t argv[OCTEON_ARGV_MAX_ARGS];
555 uint32_t flags;
556 uint32_t core_mask;
557 uint32_t dram_size; /**< DRAM size in megabyes */
558 uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/
559 uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */
560 uint32_t eclock_hz; /**< CPU clock speed, in hz */
561 uint32_t dclock_hz; /**< DRAM clock speed, in hz */
562 uint32_t spi_clock_hz; /**< SPI4 clock in hz */
563 uint16_t board_type;
564 uint8_t board_rev_major;
565 uint8_t board_rev_minor;
566 uint16_t chip_type;
567 uint8_t chip_rev_major;
568 uint8_t chip_rev_minor;
569 char board_serial_number[OCTOEN_SERIAL_LEN];
570 uint8_t mac_addr_base[6];
571 uint8_t mac_addr_count;
572 uint64_t cvmx_desc_vaddr;
573 } octeon_boot_descriptor_t;
574
575 static cvmx_bootinfo_t *
576 octeon_process_app_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr)
577 {
578 cvmx_bootinfo_t *octeon_bootinfo;
579
580 /* XXX Why is 0x00000000ffffffffULL a bad value? */
581 if (app_desc_ptr->cvmx_desc_vaddr == 0 ||
582 app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) {
583 cvmx_safe_printf("Bad octeon_bootinfo %#jx\n",
584 (uintmax_t)app_desc_ptr->cvmx_desc_vaddr);
585 return (NULL);
586 }
587
588 octeon_bootinfo = cvmx_phys_to_ptr(app_desc_ptr->cvmx_desc_vaddr);
589 if (octeon_bootinfo->major_version != 1) {
590 cvmx_safe_printf("Incompatible CVMX descriptor from bootloader: %d.%d %p\n",
591 (int) octeon_bootinfo->major_version,
592 (int) octeon_bootinfo->minor_version, octeon_bootinfo);
593 return (NULL);
594 }
595
596 cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr,
597 octeon_bootinfo->board_type,
598 octeon_bootinfo->board_rev_major,
599 octeon_bootinfo->board_rev_minor,
600 octeon_bootinfo->eclock_hz);
601 memcpy(cvmx_sysinfo_get()->mac_addr_base,
602 octeon_bootinfo->mac_addr_base, 6);
603 cvmx_sysinfo_get()->mac_addr_count = octeon_bootinfo->mac_addr_count;
604 cvmx_sysinfo_get()->compact_flash_common_base_addr =
605 octeon_bootinfo->compact_flash_common_base_addr;
606 cvmx_sysinfo_get()->compact_flash_attribute_base_addr =
607 octeon_bootinfo->compact_flash_attribute_base_addr;
608 cvmx_sysinfo_get()->core_mask = octeon_bootinfo->core_mask;
609 cvmx_sysinfo_get()->led_display_base_addr =
610 octeon_bootinfo->led_display_base_addr;
611 memcpy(cvmx_sysinfo_get()->board_serial_number,
612 octeon_bootinfo->board_serial_number,
613 sizeof cvmx_sysinfo_get()->board_serial_number);
614 return (octeon_bootinfo);
615 }
616
617 static void
618 octeon_boot_params_init(register_t ptr)
619 {
620 octeon_boot_descriptor_t *app_desc_ptr;
621 cvmx_bootinfo_t *octeon_bootinfo;
622
623 if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR) {
624 cvmx_safe_printf("app descriptor passed at invalid address %#jx\n",
625 (uintmax_t)ptr);
626 platform_reset();
627 }
628
629 app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr;
630 if (app_desc_ptr->desc_version < 6) {
631 cvmx_safe_printf("Your boot code is too old to be supported.\n");
632 platform_reset();
633 }
634 octeon_bootinfo = octeon_process_app_desc_ver_6(app_desc_ptr);
635 if (octeon_bootinfo == NULL) {
636 cvmx_safe_printf("Could not parse boot descriptor.\n");
637 platform_reset();
638 }
639
640 if (cvmx_sysinfo_get()->led_display_base_addr != 0) {
641 /*
642 * Revision 1.x of the EBT3000 only supports 4 characters, but
643 * other devices support 8.
644 */
645 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 &&
646 cvmx_sysinfo_get()->board_rev_major == 1)
647 ebt3000_str_write("FBSD");
648 else
649 ebt3000_str_write("FreeBSD!");
650 }
651
652 if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0) {
653 cvmx_safe_printf("Your boot loader did not supply a memory descriptor.\n");
654 platform_reset();
655 }
656 cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr);
657
658 octeon_feature_init();
659
660 __cvmx_helper_cfg_init();
661 }
662 /* impEND: This stuff should move back into the Cavium SDK */
Cache object: 4095423fbc638828037b7b291ff7f20e
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