Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/mips/cavium/octeon_machdep.c
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1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/boot.h> 35 #include <sys/conf.h> 36 #include <sys/kernel.h> 37 #include <sys/systm.h> 38 #include <sys/imgact.h> 39 #include <sys/bio.h> 40 #include <sys/buf.h> 41 #include <sys/bus.h> 42 #include <sys/cpu.h> 43 #include <sys/cons.h> 44 #include <sys/exec.h> 45 #include <sys/ucontext.h> 46 #include <sys/proc.h> 47 #include <sys/kdb.h> 48 #include <sys/ptrace.h> 49 #include <sys/reboot.h> 50 #include <sys/signalvar.h> 51 #include <sys/sysctl.h> 52 #include <sys/sysent.h> 53 #include <sys/sysproto.h> 54 #include <sys/time.h> 55 #include <sys/timetc.h> 56 #include <sys/user.h> 57 58 #include <vm/vm.h> 59 #include <vm/vm_param.h> 60 #include <vm/vm_object.h> 61 #include <vm/vm_page.h> 62 #include <vm/vm_phys.h> 63 #include <vm/vm_dumpset.h> 64 65 #include <machine/atomic.h> 66 #include <machine/cache.h> 67 #include <machine/clock.h> 68 #include <machine/cpu.h> 69 #include <machine/cpuregs.h> 70 #include <machine/cpufunc.h> 71 #include <mips/cavium/octeon_pcmap_regs.h> 72 #include <machine/hwfunc.h> 73 #include <machine/intr_machdep.h> 74 #include <machine/locore.h> 75 #include <machine/md_var.h> 76 #include <machine/pcpu.h> 77 #include <machine/pte.h> 78 #include <machine/trap.h> 79 80 #include <contrib/octeon-sdk/cvmx.h> 81 #include <contrib/octeon-sdk/cvmx-bootmem.h> 82 #include <contrib/octeon-sdk/cvmx-ebt3000.h> 83 #include <contrib/octeon-sdk/cvmx-helper-cfg.h> 84 #include <contrib/octeon-sdk/cvmx-interrupt.h> 85 #include <contrib/octeon-sdk/cvmx-version.h> 86 87 #include <mips/cavium/octeon_irq.h> 88 89 #if defined(__mips_n64) 90 #define MAX_APP_DESC_ADDR 0xffffffffafffffff 91 #else 92 #define MAX_APP_DESC_ADDR 0xafffffff 93 #endif 94 95 struct octeon_feature_description { 96 octeon_feature_t ofd_feature; 97 const char *ofd_string; 98 }; 99 100 extern int *end; 101 static char octeon_kenv[0x2000]; 102 103 static const struct octeon_feature_description octeon_feature_descriptions[] = { 104 { OCTEON_FEATURE_SAAD, "SAAD" }, 105 { OCTEON_FEATURE_ZIP, "ZIP" }, 106 { OCTEON_FEATURE_CRYPTO, "CRYPTO" }, 107 { OCTEON_FEATURE_DORM_CRYPTO, "DORM_CRYPTO" }, 108 { OCTEON_FEATURE_PCIE, "PCIE" }, 109 { OCTEON_FEATURE_SRIO, "SRIO" }, 110 { OCTEON_FEATURE_KEY_MEMORY, "KEY_MEMORY" }, 111 { OCTEON_FEATURE_LED_CONTROLLER, "LED_CONTROLLER" }, 112 { OCTEON_FEATURE_TRA, "TRA" }, 113 { OCTEON_FEATURE_MGMT_PORT, "MGMT_PORT" }, 114 { OCTEON_FEATURE_RAID, "RAID" }, 115 { OCTEON_FEATURE_USB, "USB" }, 116 { OCTEON_FEATURE_NO_WPTR, "NO_WPTR" }, 117 { OCTEON_FEATURE_DFA, "DFA" }, 118 { OCTEON_FEATURE_MDIO_CLAUSE_45, "MDIO_CLAUSE_45" }, 119 { OCTEON_FEATURE_NPEI, "NPEI" }, 120 { OCTEON_FEATURE_ILK, "ILK" }, 121 { OCTEON_FEATURE_HFA, "HFA" }, 122 { OCTEON_FEATURE_DFM, "DFM" }, 123 { OCTEON_FEATURE_CIU2, "CIU2" }, 124 { OCTEON_FEATURE_DICI_MODE, "DICI_MODE" }, 125 { OCTEON_FEATURE_BIT_EXTRACTOR, "BIT_EXTRACTOR" }, 126 { OCTEON_FEATURE_NAND, "NAND" }, 127 { OCTEON_FEATURE_MMC, "MMC" }, 128 { OCTEON_FEATURE_PKND, "PKND" }, 129 { OCTEON_FEATURE_CN68XX_WQE, "CN68XX_WQE" }, 130 { 0, NULL } 131 }; 132 133 static uint64_t octeon_get_ticks(void); 134 static unsigned octeon_get_timecount(struct timecounter *tc); 135 136 static void octeon_boot_params_init(register_t ptr); 137 static void octeon_init_kenv(register_t ptr); 138 139 static struct timecounter octeon_timecounter = { 140 octeon_get_timecount, /* get_timecount */ 141 0, /* no poll_pps */ 142 0xffffffffu, /* octeon_mask */ 143 0, /* frequency */ 144 "Octeon", /* name */ 145 900, /* quality (adjusted in code) */ 146 }; 147 148 void 149 platform_cpu_init() 150 { 151 /* Nothing special yet */ 152 } 153 154 /* 155 * Perform a board-level soft-reset. 156 */ 157 void 158 platform_reset(void) 159 { 160 cvmx_write_csr(CVMX_CIU_SOFT_RST, 1); 161 } 162 163 /* 164 * octeon_debug_symbol 165 * 166 * Does nothing. 167 * Used to mark the point for simulator to begin tracing 168 */ 169 void 170 octeon_debug_symbol(void) 171 { 172 } 173 174 /* 175 * octeon_ciu_reset 176 * 177 * Shutdown all CIU to IP2, IP3 mappings 178 */ 179 void 180 octeon_ciu_reset(void) 181 { 182 uint64_t cvmctl; 183 184 /* Disable all CIU interrupts by default */ 185 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0); 186 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0); 187 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0); 188 cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0); 189 190 #ifdef SMP 191 /* Enable the MBOX interrupts. */ 192 cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 193 (1ull << (OCTEON_IRQ_MBOX0 - 8)) | 194 (1ull << (OCTEON_IRQ_MBOX1 - 8))); 195 #endif 196 197 /* 198 * Move the Performance Counter interrupt to OCTEON_PMC_IRQ 199 */ 200 cvmctl = mips_rd_cvmctl(); 201 cvmctl &= ~(7 << 7); 202 cvmctl |= (OCTEON_PMC_IRQ + 2) << 7; 203 mips_wr_cvmctl(cvmctl); 204 } 205 206 static void 207 octeon_memory_init(void) 208 { 209 vm_paddr_t phys_end; 210 int64_t addr; 211 unsigned i, j; 212 213 phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end)); 214 215 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_SIM) { 216 /* Simulator we limit to 96 meg */ 217 phys_avail[0] = phys_end; 218 phys_avail[1] = 96 << 20; 219 220 dump_avail[0] = phys_avail[0]; 221 dump_avail[1] = phys_avail[1]; 222 223 realmem = physmem = btoc(phys_avail[1] - phys_avail[0]); 224 return; 225 } 226 227 /* 228 * Allocate memory from bootmem 1MB at a time and merge 229 * adjacent entries. 230 */ 231 i = 0; 232 while (i < PHYS_AVAIL_ENTRIES) { 233 /* 234 * If there is less than 2MB of memory available in 128-byte 235 * blocks, do not steal any more memory. We need to leave some 236 * memory for the command queues to be allocated out of. 237 */ 238 if (cvmx_bootmem_available_mem(128) < 2 << 20) 239 break; 240 241 addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end, 242 ~(vm_paddr_t)0, PAGE_SIZE, 0); 243 if (addr == -1) 244 break; 245 246 /* 247 * The SDK needs to be able to easily map any memory that might 248 * come to it e.g. in the form of an mbuf. Because on !n64 we 249 * can't direct-map some addresses and we don't want to manage 250 * temporary mappings within the SDK, don't feed memory that 251 * can't be direct-mapped to the kernel. 252 */ 253 #if !defined(__mips_n64) 254 if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1)) 255 continue; 256 #endif 257 258 physmem += btoc(1 << 20); 259 260 if (i > 0 && phys_avail[i - 1] == addr) { 261 phys_avail[i - 1] += 1 << 20; 262 continue; 263 } 264 265 phys_avail[i + 0] = addr; 266 phys_avail[i + 1] = addr + (1 << 20); 267 268 i += 2; 269 } 270 271 for (j = 0; j < i; j++) 272 dump_avail[j] = phys_avail[j]; 273 274 realmem = physmem; 275 } 276 277 void 278 platform_start(__register_t a0, __register_t a1, __register_t a2 __unused, 279 __register_t a3) 280 { 281 const struct octeon_feature_description *ofd; 282 uint64_t platform_counter_freq; 283 int rv; 284 285 mips_postboot_fixup(); 286 287 /* 288 * Initialize boot parameters so that we can determine things like 289 * which console we shoud use, etc. 290 */ 291 octeon_boot_params_init(a3); 292 293 /* Initialize pcpu stuff */ 294 mips_pcpu0_init(); 295 mips_timer_early_init(cvmx_sysinfo_get()->cpu_clock_hz); 296 297 /* Initialize console. */ 298 cninit(); 299 300 /* 301 * Display information about the CPU. 302 */ 303 #if !defined(OCTEON_MODEL) 304 printf("Using runtime CPU model checks.\n"); 305 #else 306 printf("Compiled for CPU model: " __XSTRING(OCTEON_MODEL) "\n"); 307 #endif 308 strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id())); 309 printf("CPU Model: %s\n", cpu_model); 310 printf("CPU clock: %uMHz Core Mask: %#x\n", 311 cvmx_sysinfo_get()->cpu_clock_hz / 1000000, 312 cvmx_sysinfo_get()->core_mask); 313 rv = octeon_model_version_check(cvmx_get_proc_id()); 314 if (rv == -1) 315 panic("%s: kernel not compatible with this processor.", __func__); 316 317 /* 318 * Display information about the board. 319 */ 320 #if defined(OCTEON_BOARD_CAPK_0100ND) 321 strcpy(cpu_board, "CAPK-0100ND"); 322 if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) { 323 panic("Compiled for %s, but board type is %s.", cpu_board, 324 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 325 } 326 #else 327 strcpy(cpu_board, 328 cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type)); 329 #endif 330 printf("Board: %s\n", cpu_board); 331 printf("Board Type: %u Revision: %u/%u\n", 332 cvmx_sysinfo_get()->board_type, 333 cvmx_sysinfo_get()->board_rev_major, 334 cvmx_sysinfo_get()->board_rev_minor); 335 printf("Serial number: %s\n", cvmx_sysinfo_get()->board_serial_number); 336 337 /* 338 * Additional on-chip hardware/settings. 339 * 340 * XXX Display PCI host/target? What else? 341 */ 342 printf("MAC address base: %6D (%u configured)\n", 343 cvmx_sysinfo_get()->mac_addr_base, ":", 344 cvmx_sysinfo_get()->mac_addr_count); 345 346 octeon_ciu_reset(); 347 /* 348 * Convert U-Boot 'bootoctlinux' loader command line arguments into 349 * boot flags and kernel environment variables. 350 */ 351 bootverbose = 1; 352 octeon_init_kenv(a3); 353 354 /* 355 * For some reason on the cn38xx simulator ebase register is set to 356 * 0x80001000 at bootup time. Move it back to the default, but 357 * when we move to having support for multiple executives, we need 358 * to rethink this. 359 */ 360 mips_wr_ebase(0x80000000); 361 362 octeon_memory_init(); 363 init_param1(); 364 init_param2(physmem); 365 mips_cpu_init(); 366 pmap_bootstrap(); 367 mips_proc0_init(); 368 mutex_init(); 369 kdb_init(); 370 #ifdef KDB 371 if (boothowto & RB_KDB) 372 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger"); 373 #endif 374 cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz; 375 platform_counter_freq = cpu_clock; 376 octeon_timecounter.tc_frequency = cpu_clock; 377 platform_timecounter = &octeon_timecounter; 378 mips_timer_init_params(platform_counter_freq, 0); 379 set_cputicker(octeon_get_ticks, cpu_clock, 0); 380 381 #ifdef SMP 382 /* 383 * Clear any pending IPIs. 384 */ 385 cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff); 386 #endif 387 388 printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING); 389 printf("Available Octeon features:"); 390 for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++) 391 if (octeon_has_feature(ofd->ofd_feature)) 392 printf(" %s", ofd->ofd_string); 393 printf("\n"); 394 } 395 396 static uint64_t 397 octeon_get_ticks(void) 398 { 399 uint64_t cvmcount; 400 401 CVMX_MF_CYCLE(cvmcount); 402 return (cvmcount); 403 } 404 405 static unsigned 406 octeon_get_timecount(struct timecounter *tc) 407 { 408 return ((unsigned)octeon_get_ticks()); 409 } 410 411 static int 412 sysctl_machdep_led_display(SYSCTL_HANDLER_ARGS) 413 { 414 size_t buflen; 415 char buf[9]; 416 int error; 417 418 if (req->newptr == NULL) 419 return (EINVAL); 420 421 if (cvmx_sysinfo_get()->led_display_base_addr == 0) 422 return (ENODEV); 423 424 /* 425 * Revision 1.x of the EBT3000 only supports 4 characters, but 426 * other devices support 8. 427 */ 428 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 && 429 cvmx_sysinfo_get()->board_rev_major == 1) 430 buflen = 4; 431 else 432 buflen = 8; 433 434 if (req->newlen > buflen) 435 return (E2BIG); 436 437 error = SYSCTL_IN(req, buf, req->newlen); 438 if (error != 0) 439 return (error); 440 441 buf[req->newlen] = '\0'; 442 ebt3000_str_write(buf); 443 444 return (0); 445 } 446 447 SYSCTL_PROC(_machdep, OID_AUTO, led_display, 448 CTLTYPE_STRING | CTLFLAG_WR | CTLFLAG_NEEDGIANT, NULL, 0, 449 sysctl_machdep_led_display, "A", 450 "String to display on LED display"); 451 452 void 453 cvmx_dvprintf(const char *fmt, va_list ap) 454 { 455 if (!bootverbose) 456 return; 457 vprintf(fmt, ap); 458 } 459 460 void 461 cvmx_dprintf(const char *fmt, ...) 462 { 463 va_list ap; 464 465 va_start(ap, fmt); 466 cvmx_dvprintf(fmt, ap); 467 va_end(ap); 468 } 469 470 /** 471 * version of printf that works better in exception context. 472 * 473 * @param format 474 * 475 * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version. 476 */ 477 void cvmx_safe_printf(const char *format, ...) 478 { 479 char buffer[256]; 480 char *ptr = buffer; 481 int count; 482 va_list args; 483 484 va_start(args, format); 485 #ifndef __U_BOOT__ 486 count = vsnprintf(buffer, sizeof(buffer), format, args); 487 #else 488 count = vsprintf(buffer, format, args); 489 #endif 490 va_end(args); 491 492 while (count-- > 0) 493 { 494 cvmx_uart_lsr_t lsrval; 495 496 /* Spin until there is room */ 497 do 498 { 499 lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0)); 500 #if !defined(CONFIG_OCTEON_SIM_SPEED) 501 if (lsrval.s.temt == 0) 502 cvmx_wait(10000); /* Just to reduce the load on the system */ 503 #endif 504 } 505 while (lsrval.s.temt == 0); 506 507 if (*ptr == '\n') 508 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r'); 509 cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++); 510 } 511 } 512 513 /* impSTART: This stuff should move back into the Cavium SDK */ 514 /* 515 **************************************************************************************** 516 * 517 * APP/BOOT DESCRIPTOR STUFF 518 * 519 **************************************************************************************** 520 */ 521 522 /* Define the struct that is initialized by the bootloader used by the 523 * startup code. 524 * 525 * Copyright (c) 2004, 2005, 2006 Cavium Networks. 526 * 527 * The authors hereby grant permission to use, copy, modify, distribute, 528 * and license this software and its documentation for any purpose, provided 529 * that existing copyright notices are retained in all copies and that this 530 * notice is included verbatim in any distributions. No written agreement, 531 * license, or royalty fee is required for any of the authorized uses. 532 * Modifications to this software may be copyrighted by their authors 533 * and need not follow the licensing terms described here, provided that 534 * the new terms are clearly indicated on the first page of each file where 535 * they apply. 536 */ 537 538 #define OCTEON_CURRENT_DESC_VERSION 6 539 #define OCTEON_ARGV_MAX_ARGS (64) 540 #define OCTOEN_SERIAL_LEN 20 541 542 typedef struct { 543 /* Start of block referenced by assembly code - do not change! */ 544 uint32_t desc_version; 545 uint32_t desc_size; 546 547 uint64_t stack_top; 548 uint64_t heap_base; 549 uint64_t heap_end; 550 uint64_t entry_point; /* Only used by bootloader */ 551 uint64_t desc_vaddr; 552 /* End of This block referenced by assembly code - do not change! */ 553 554 uint32_t exception_base_addr; 555 uint32_t stack_size; 556 uint32_t heap_size; 557 uint32_t argc; /* Argc count for application */ 558 uint32_t argv[OCTEON_ARGV_MAX_ARGS]; 559 uint32_t flags; 560 uint32_t core_mask; 561 uint32_t dram_size; /**< DRAM size in megabyes */ 562 uint32_t phy_mem_desc_addr; /**< physical address of free memory descriptor block*/ 563 uint32_t debugger_flags_base_addr; /**< used to pass flags from app to debugger */ 564 uint32_t eclock_hz; /**< CPU clock speed, in hz */ 565 uint32_t dclock_hz; /**< DRAM clock speed, in hz */ 566 uint32_t spi_clock_hz; /**< SPI4 clock in hz */ 567 uint16_t board_type; 568 uint8_t board_rev_major; 569 uint8_t board_rev_minor; 570 uint16_t chip_type; 571 uint8_t chip_rev_major; 572 uint8_t chip_rev_minor; 573 char board_serial_number[OCTOEN_SERIAL_LEN]; 574 uint8_t mac_addr_base[6]; 575 uint8_t mac_addr_count; 576 uint64_t cvmx_desc_vaddr; 577 } octeon_boot_descriptor_t; 578 579 static cvmx_bootinfo_t * 580 octeon_process_app_desc_ver_6(octeon_boot_descriptor_t *app_desc_ptr) 581 { 582 cvmx_bootinfo_t *octeon_bootinfo; 583 584 /* XXX Why is 0x00000000ffffffffULL a bad value? */ 585 if (app_desc_ptr->cvmx_desc_vaddr == 0 || 586 app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful) { 587 cvmx_safe_printf("Bad octeon_bootinfo %#jx\n", 588 (uintmax_t)app_desc_ptr->cvmx_desc_vaddr); 589 return (NULL); 590 } 591 592 octeon_bootinfo = cvmx_phys_to_ptr(app_desc_ptr->cvmx_desc_vaddr); 593 if (octeon_bootinfo->major_version != 1) { 594 cvmx_safe_printf("Incompatible CVMX descriptor from bootloader: %d.%d %p\n", 595 (int) octeon_bootinfo->major_version, 596 (int) octeon_bootinfo->minor_version, octeon_bootinfo); 597 return (NULL); 598 } 599 600 cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr, 601 octeon_bootinfo->board_type, 602 octeon_bootinfo->board_rev_major, 603 octeon_bootinfo->board_rev_minor, 604 octeon_bootinfo->eclock_hz); 605 memcpy(cvmx_sysinfo_get()->mac_addr_base, 606 octeon_bootinfo->mac_addr_base, 6); 607 cvmx_sysinfo_get()->mac_addr_count = octeon_bootinfo->mac_addr_count; 608 cvmx_sysinfo_get()->compact_flash_common_base_addr = 609 octeon_bootinfo->compact_flash_common_base_addr; 610 cvmx_sysinfo_get()->compact_flash_attribute_base_addr = 611 octeon_bootinfo->compact_flash_attribute_base_addr; 612 cvmx_sysinfo_get()->core_mask = octeon_bootinfo->core_mask; 613 cvmx_sysinfo_get()->led_display_base_addr = 614 octeon_bootinfo->led_display_base_addr; 615 memcpy(cvmx_sysinfo_get()->board_serial_number, 616 octeon_bootinfo->board_serial_number, 617 sizeof cvmx_sysinfo_get()->board_serial_number); 618 return (octeon_bootinfo); 619 } 620 621 static void 622 octeon_boot_params_init(register_t ptr) 623 { 624 octeon_boot_descriptor_t *app_desc_ptr; 625 cvmx_bootinfo_t *octeon_bootinfo; 626 627 if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR) { 628 cvmx_safe_printf("app descriptor passed at invalid address %#jx\n", 629 (uintmax_t)ptr); 630 platform_reset(); 631 } 632 633 app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr; 634 if (app_desc_ptr->desc_version < 6) { 635 cvmx_safe_printf("Your boot code is too old to be supported.\n"); 636 platform_reset(); 637 } 638 octeon_bootinfo = octeon_process_app_desc_ver_6(app_desc_ptr); 639 if (octeon_bootinfo == NULL) { 640 cvmx_safe_printf("Could not parse boot descriptor.\n"); 641 platform_reset(); 642 } 643 644 if (cvmx_sysinfo_get()->led_display_base_addr != 0) { 645 /* 646 * Revision 1.x of the EBT3000 only supports 4 characters, but 647 * other devices support 8. 648 */ 649 if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBT3000 && 650 cvmx_sysinfo_get()->board_rev_major == 1) 651 ebt3000_str_write("FBSD"); 652 else 653 ebt3000_str_write("FreeBSD!"); 654 } 655 656 if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0) { 657 cvmx_safe_printf("Your boot loader did not supply a memory descriptor.\n"); 658 platform_reset(); 659 } 660 cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr); 661 662 octeon_feature_init(); 663 664 __cvmx_helper_cfg_init(); 665 } 666 /* impEND: This stuff should move back into the Cavium SDK */ 667 668 /* 669 * The boot loader command line may specify kernel environment variables or 670 * applicable boot flags of boot(8). 671 */ 672 static void 673 octeon_init_kenv(register_t ptr) 674 { 675 int i; 676 char *n; 677 char *v; 678 octeon_boot_descriptor_t *app_desc_ptr; 679 680 app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr; 681 memset(octeon_kenv, 0, sizeof(octeon_kenv)); 682 init_static_kenv(octeon_kenv, sizeof(octeon_kenv)); 683 684 for (i = 0; i < app_desc_ptr->argc; i++) { 685 v = cvmx_phys_to_ptr(app_desc_ptr->argv[i]); 686 if (v == NULL) 687 continue; 688 if (*v == '-') { 689 boothowto |= boot_parse_arg(v); 690 continue; 691 } 692 n = strsep(&v, "="); 693 if (v == NULL) 694 kern_setenv(n, "1"); 695 else 696 kern_setenv(n, v); 697 } 698 }
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