The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/mips/cavium/octeon_machdep.c

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    1 /*-
    2  * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: stable/8/sys/mips/cavium/octeon_machdep.c 215938 2010-11-27 12:26:40Z jchandra $
   27  */
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: stable/8/sys/mips/cavium/octeon_machdep.c 215938 2010-11-27 12:26:40Z jchandra $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/conf.h>
   33 #include <sys/kernel.h>
   34 #include <sys/systm.h>
   35 #include <sys/imgact.h>
   36 #include <sys/bio.h>
   37 #include <sys/buf.h>
   38 #include <sys/bus.h>
   39 #include <sys/cpu.h>
   40 #include <sys/cons.h>
   41 #include <sys/exec.h>
   42 #include <sys/ucontext.h>
   43 #include <sys/proc.h>
   44 #include <sys/kdb.h>
   45 #include <sys/ptrace.h>
   46 #include <sys/reboot.h>
   47 #include <sys/signalvar.h>
   48 #include <sys/sysent.h>
   49 #include <sys/sysproto.h>
   50 #include <sys/time.h>
   51 #include <sys/timetc.h>
   52 #include <sys/user.h>
   53 
   54 #include <vm/vm.h>
   55 #include <vm/vm_object.h>
   56 #include <vm/vm_page.h>
   57 #include <vm/vm_pager.h>
   58 
   59 #include <machine/atomic.h>
   60 #include <machine/cache.h>
   61 #include <machine/clock.h>
   62 #include <machine/cpu.h>
   63 #include <machine/cpuregs.h>
   64 #include <machine/cpufunc.h>
   65 #include <mips/cavium/octeon_pcmap_regs.h>
   66 #include <machine/hwfunc.h>
   67 #include <machine/intr_machdep.h>
   68 #include <machine/locore.h>
   69 #include <machine/md_var.h>
   70 #include <machine/pcpu.h>
   71 #include <machine/pte.h>
   72 #include <machine/trap.h>
   73 #include <machine/vmparam.h>
   74 
   75 #include <contrib/octeon-sdk/cvmx.h>
   76 #include <contrib/octeon-sdk/cvmx-bootmem.h>
   77 #include <contrib/octeon-sdk/cvmx-interrupt.h>
   78 #include <contrib/octeon-sdk/cvmx-version.h>
   79 
   80 #if defined(__mips_n64) 
   81 #define MAX_APP_DESC_ADDR     0xffffffffafffffff
   82 #else
   83 #define MAX_APP_DESC_ADDR     0xafffffff
   84 #endif
   85 
   86 #define OCTEON_CLOCK_DEFAULT (500 * 1000 * 1000)
   87 
   88 struct octeon_feature_description {
   89         octeon_feature_t ofd_feature;
   90         const char *ofd_string;
   91 };
   92 
   93 extern int      *edata;
   94 extern int      *end;
   95 
   96 static const struct octeon_feature_description octeon_feature_descriptions[] = {
   97         { OCTEON_FEATURE_SAAD,                  "SAAD" },
   98         { OCTEON_FEATURE_ZIP,                   "ZIP" },
   99         { OCTEON_FEATURE_CRYPTO,                "CRYPTO" },
  100         { OCTEON_FEATURE_PCIE,                  "PCIE" },
  101         { OCTEON_FEATURE_KEY_MEMORY,            "KEY_MEMORY" },
  102         { OCTEON_FEATURE_LED_CONTROLLER,        "LED_CONTROLLER" },
  103         { OCTEON_FEATURE_TRA,                   "TRA" },
  104         { OCTEON_FEATURE_MGMT_PORT,             "MGMT_PORT" },
  105         { OCTEON_FEATURE_RAID,                  "RAID" },
  106         { OCTEON_FEATURE_USB,                   "USB" },
  107         { OCTEON_FEATURE_NO_WPTR,               "NO_WPTR" },
  108         { OCTEON_FEATURE_DFA,                   "DFA" },
  109         { OCTEON_FEATURE_MDIO_CLAUSE_45,        "MDIO_CLAUSE_45" },
  110         { 0,                                    NULL }
  111 };
  112 
  113 uint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip);
  114 void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip);
  115 
  116 static uint64_t octeon_get_ticks(void);
  117 static unsigned octeon_get_timecount(struct timecounter *tc);
  118 
  119 static void octeon_boot_params_init(register_t ptr);
  120 
  121 static struct timecounter octeon_timecounter = {
  122         octeon_get_timecount,   /* get_timecount */
  123         0,                      /* no poll_pps */
  124         0xffffffffu,            /* octeon_mask */
  125         0,                      /* frequency */
  126         "Octeon",               /* name */
  127         900,                    /* quality (adjusted in code) */
  128 };
  129 
  130 void
  131 platform_cpu_init()
  132 {
  133         /* Nothing special yet */
  134 }
  135 
  136 /*
  137  * Perform a board-level soft-reset.
  138  */
  139 void
  140 platform_reset(void)
  141 {
  142         cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
  143 }
  144 
  145 void
  146 octeon_led_write_char(int char_position, char val)
  147 {
  148         uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
  149 
  150         if (octeon_is_simulation())
  151                 return;
  152 
  153         char_position &= 0x7;  /* only 8 chars */
  154         ptr += char_position;
  155         oct_write8_x8(ptr, val);
  156 }
  157 
  158 void
  159 octeon_led_write_char0(char val)
  160 {
  161         uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
  162 
  163         if (octeon_is_simulation())
  164                 return;
  165         oct_write8_x8(ptr, val);
  166 }
  167 
  168 void
  169 octeon_led_write_hexchar(int char_position, char hexval)
  170 {
  171         uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
  172         char char1, char2;
  173 
  174         if (octeon_is_simulation())
  175                 return;
  176 
  177         char1 = (hexval >> 4) & 0x0f; char1 = (char1 < 10)?char1+'':char1+'7';
  178         char2 = (hexval  & 0x0f); char2 = (char2 < 10)?char2+'':char2+'7';
  179         char_position &= 0x7;  /* only 8 chars */
  180         if (char_position > 6)
  181                 char_position = 6;
  182         ptr += char_position;
  183         oct_write8_x8(ptr, char1);
  184         ptr++;
  185         oct_write8_x8(ptr, char2);
  186 }
  187 
  188 void
  189 octeon_led_write_string(const char *str)
  190 {
  191         uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
  192         int i;
  193 
  194         if (octeon_is_simulation())
  195                 return;
  196 
  197         for (i=0; i<8; i++, ptr++) {
  198                 if (str && *str)
  199                         oct_write8_x8(ptr, *str++);
  200                 else
  201                         oct_write8_x8(ptr, ' ');
  202                 (void)cvmx_read_csr(CVMX_MIO_BOOT_BIST_STAT);
  203         }
  204 }
  205 
  206 static char progress[8] = { '-', '/', '|', '\\', '-', '/', '|', '\\'};
  207 
  208 void
  209 octeon_led_run_wheel(int *prog_count, int led_position)
  210 {
  211         if (octeon_is_simulation())
  212                 return;
  213         octeon_led_write_char(led_position, progress[*prog_count]);
  214         *prog_count += 1;
  215         *prog_count &= 0x7;
  216 }
  217 
  218 void
  219 octeon_led_write_hex(uint32_t wl)
  220 {
  221         char nbuf[80];
  222 
  223         sprintf(nbuf, "%X", wl);
  224         octeon_led_write_string(nbuf);
  225 }
  226 
  227 /*
  228  * octeon_debug_symbol
  229  *
  230  * Does nothing.
  231  * Used to mark the point for simulator to begin tracing
  232  */
  233 void
  234 octeon_debug_symbol(void)
  235 {
  236 }
  237 
  238 /*
  239  * octeon_ciu_reset
  240  *
  241  * Shutdown all CIU to IP2, IP3 mappings
  242  */
  243 void
  244 octeon_ciu_reset(void)
  245 {
  246         /* Disable all CIU interrupts by default */
  247         cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
  248         cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
  249         cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
  250         cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
  251 
  252 #ifdef SMP
  253         /* Enable the MBOX interrupts.  */
  254         cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1),
  255                        (1ull << (CVMX_IRQ_MBOX0 - 8)) |
  256                        (1ull << (CVMX_IRQ_MBOX1 - 8)));
  257 #endif
  258 }
  259 
  260 static void
  261 octeon_memory_init(void)
  262 {
  263         vm_paddr_t phys_end;
  264         int64_t addr;
  265         unsigned i;
  266 
  267         phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end));
  268 
  269         if (octeon_is_simulation()) {
  270                 /* Simulator we limit to 96 meg */
  271                 phys_avail[0] = phys_end;
  272                 phys_avail[1] = 96 << 20;
  273 
  274                 realmem = physmem = btoc(phys_avail[1] - phys_avail[0]);
  275                 return;
  276         }
  277 
  278         /*
  279          * Allocate memory from bootmem 1MB at a time and merge
  280          * adjacent entries.
  281          */
  282         i = 0;
  283         while (i < PHYS_AVAIL_ENTRIES) {
  284                 addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end,
  285                                               ~(vm_paddr_t)0, PAGE_SIZE, 0);
  286                 if (addr == -1)
  287                         break;
  288 
  289                 /*
  290                  * The SDK needs to be able to easily map any memory that might
  291                  * come to it e.g. in the form of an mbuf.  Because on !n64 we
  292                  * can't direct-map some addresses and we don't want to manage
  293                  * temporary mappings within the SDK, don't feed memory that
  294                  * can't be direct-mapped to the kernel.
  295                  */
  296 #if !defined(__mips_n64)
  297                 if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1))
  298                         continue;
  299 #endif
  300 
  301                 physmem += btoc(1 << 20);
  302 
  303                 if (i > 0 && phys_avail[i - 1] == addr) {
  304                         phys_avail[i - 1] += 1 << 20;
  305                         continue;
  306                 }
  307 
  308                 phys_avail[i + 0] = addr;
  309                 phys_avail[i + 1] = addr + (1 << 20);
  310 
  311                 i += 2;
  312         }
  313 
  314         realmem = physmem;
  315 }
  316 
  317 void
  318 platform_start(__register_t a0, __register_t a1, __register_t a2 __unused,
  319     __register_t a3)
  320 {
  321         const struct octeon_feature_description *ofd;
  322         uint64_t platform_counter_freq;
  323 
  324         /*
  325          * XXX
  326          * octeon_boot_params_init() should be called before anything else,
  327          * certainly before any output; we may find out from the boot
  328          * descriptor's flags that we're supposed to use the PCI or UART1
  329          * consoles rather than UART0.  No point doing that reorganization
  330          * until we actually intercept UART_DEV_CONSOLE for the UART1 case
  331          * and somehow handle the PCI console, which we lack code for
  332          * entirely.
  333          */
  334 
  335         /* Initialize pcpu stuff */
  336         mips_pcpu0_init();
  337         mips_timer_early_init(OCTEON_CLOCK_DEFAULT);
  338         cninit();
  339 
  340         octeon_ciu_reset();
  341         octeon_boot_params_init(a3);
  342         /*
  343          * XXX
  344          * We can certainly parse command line arguments or U-Boot environment
  345          * to determine whether to bootverbose / single user / ...  I think
  346          * stass has patches to add support for loader things to U-Boot even.
  347          */
  348         bootverbose = 1;
  349 
  350         /*
  351          * For some reason on the cn38xx simulator ebase register is set to
  352          * 0x80001000 at bootup time.  Move it back to the default, but
  353          * when we move to having support for multiple executives, we need
  354          * to rethink this.
  355          */
  356         mips_wr_ebase(0x80000000);
  357 
  358         octeon_memory_init();
  359         init_param1();
  360         init_param2(physmem);
  361         mips_cpu_init();
  362         pmap_bootstrap();
  363         mips_proc0_init();
  364         mutex_init();
  365         kdb_init();
  366 #ifdef KDB
  367         if (boothowto & RB_KDB)
  368                 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
  369 #endif
  370         platform_counter_freq = cvmx_sysinfo_get()->cpu_clock_hz;
  371 
  372         octeon_timecounter.tc_frequency = cvmx_sysinfo_get()->cpu_clock_hz;
  373         platform_timecounter = &octeon_timecounter;
  374 
  375         mips_timer_init_params(platform_counter_freq, 0);
  376 
  377         set_cputicker(octeon_get_ticks, cvmx_sysinfo_get()->cpu_clock_hz, 0);
  378 
  379 #ifdef SMP
  380         /*
  381          * Clear any pending IPIs.
  382          */
  383         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff);
  384 #endif
  385 
  386         printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING);
  387         printf("Available Octeon features:");
  388         for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++)
  389                 if (octeon_has_feature(ofd->ofd_feature))
  390                         printf(" %s", ofd->ofd_string);
  391         printf("\n");
  392 }
  393 
  394 static uint64_t
  395 octeon_get_ticks(void)
  396 {
  397         uint64_t cvmcount;
  398 
  399         CVMX_MF_CYCLE(cvmcount);
  400         return (cvmcount);
  401 }
  402 
  403 static unsigned
  404 octeon_get_timecount(struct timecounter *tc)
  405 {
  406         return ((unsigned)octeon_get_ticks());
  407 }
  408 
  409 /* impSTART: This stuff should move back into the Cavium SDK */
  410 /*
  411  ****************************************************************************************
  412  *
  413  * APP/BOOT  DESCRIPTOR  STUFF
  414  *
  415  ****************************************************************************************
  416  */
  417 
  418 /* Define the struct that is initialized by the bootloader used by the 
  419  * startup code.
  420  *
  421  * Copyright (c) 2004, 2005, 2006 Cavium Networks.
  422  *
  423  * The authors hereby grant permission to use, copy, modify, distribute,
  424  * and license this software and its documentation for any purpose, provided
  425  * that existing copyright notices are retained in all copies and that this
  426  * notice is included verbatim in any distributions. No written agreement,
  427  * license, or royalty fee is required for any of the authorized uses.
  428  * Modifications to this software may be copyrighted by their authors
  429  * and need not follow the licensing terms described here, provided that
  430  * the new terms are clearly indicated on the first page of each file where
  431  * they apply.
  432  */
  433 
  434 #define OCTEON_CURRENT_DESC_VERSION     6
  435 #define OCTEON_ARGV_MAX_ARGS            (64)
  436 #define OCTOEN_SERIAL_LEN 20
  437 
  438 typedef struct {
  439         /* Start of block referenced by assembly code - do not change! */
  440         uint32_t desc_version;
  441         uint32_t desc_size;
  442 
  443         uint64_t stack_top;
  444         uint64_t heap_base;
  445         uint64_t heap_end;
  446         uint64_t entry_point;   /* Only used by bootloader */
  447         uint64_t desc_vaddr;
  448         /* End of This block referenced by assembly code - do not change! */
  449 
  450         uint32_t exception_base_addr;
  451         uint32_t stack_size;
  452         uint32_t heap_size;
  453         uint32_t argc;  /* Argc count for application */
  454         uint32_t argv[OCTEON_ARGV_MAX_ARGS];
  455         uint32_t flags;
  456         uint32_t core_mask;
  457         uint32_t dram_size;  /**< DRAM size in megabyes */
  458         uint32_t phy_mem_desc_addr;  /**< physical address of free memory descriptor block*/
  459         uint32_t debugger_flags_base_addr;  /**< used to pass flags from app to debugger */
  460         uint32_t eclock_hz;  /**< CPU clock speed, in hz */
  461         uint32_t dclock_hz;  /**< DRAM clock speed, in hz */
  462         uint32_t spi_clock_hz;  /**< SPI4 clock in hz */
  463         uint16_t board_type;
  464         uint8_t board_rev_major;
  465         uint8_t board_rev_minor;
  466         uint16_t chip_type;
  467         uint8_t chip_rev_major;
  468         uint8_t chip_rev_minor;
  469         char board_serial_number[OCTOEN_SERIAL_LEN];
  470         uint8_t mac_addr_base[6];
  471         uint8_t mac_addr_count;
  472         uint64_t cvmx_desc_vaddr;
  473 } octeon_boot_descriptor_t;
  474 
  475 cvmx_bootinfo_t *octeon_bootinfo;
  476 
  477 static octeon_boot_descriptor_t *app_desc_ptr;
  478 
  479 int
  480 octeon_is_simulation(void)
  481 {
  482         switch (cvmx_sysinfo_get()->board_type) {
  483         case CVMX_BOARD_TYPE_SIM:
  484                 return 1;
  485         default:
  486                 return 0;
  487         }
  488 }
  489 
  490 static void
  491 octeon_process_app_desc_ver_6(void)
  492 {
  493         void *phy_mem_desc_ptr;
  494 
  495         /* XXX Why is 0x00000000ffffffffULL a bad value?  */
  496         if (app_desc_ptr->cvmx_desc_vaddr == 0 ||
  497             app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful)
  498                 panic("Bad octeon_bootinfo %p", octeon_bootinfo);
  499 
  500         octeon_bootinfo =
  501             (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr;
  502         octeon_bootinfo =
  503             (cvmx_bootinfo_t *) ((intptr_t)octeon_bootinfo | MIPS_KSEG0_START);
  504         if (octeon_bootinfo->major_version != 1)
  505                 panic("Incompatible CVMX descriptor from bootloader: %d.%d %p",
  506                        (int) octeon_bootinfo->major_version,
  507                        (int) octeon_bootinfo->minor_version, octeon_bootinfo);
  508 
  509         phy_mem_desc_ptr =
  510             (void *)MIPS_PHYS_TO_KSEG0(octeon_bootinfo->phy_mem_desc_addr);
  511         cvmx_sysinfo_minimal_initialize(phy_mem_desc_ptr,
  512                                         octeon_bootinfo->board_type,
  513                                         octeon_bootinfo->board_rev_major,
  514                                         octeon_bootinfo->board_rev_minor,
  515                                         octeon_bootinfo->eclock_hz);
  516 }
  517 
  518 static void
  519 octeon_boot_params_init(register_t ptr)
  520 {
  521         if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR)
  522                 panic("app descriptor passed at invalid address %#jx",
  523                     (uintmax_t)ptr);
  524 
  525         app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr;
  526         if (app_desc_ptr->desc_version < 6)
  527                 panic("Your boot code is too old to be supported.");
  528         octeon_process_app_desc_ver_6();
  529 
  530         KASSERT(octeon_bootinfo != NULL, ("octeon_bootinfo should be set"));
  531 
  532         if (cvmx_sysinfo_get()->phy_mem_desc_ptr == NULL)
  533                 panic("Your boot loader did not supply a memory descriptor.");
  534         cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_ptr);
  535 
  536         printf("Boot Descriptor Ver: %u -> %u/%u",
  537                app_desc_ptr->desc_version, octeon_bootinfo->major_version,
  538                octeon_bootinfo->minor_version);
  539         printf("  CPU clock: %uMHz  Core Mask: %#x\n",
  540                cvmx_sysinfo_get()->cpu_clock_hz / 1000000,
  541                cvmx_sysinfo_get()->core_mask);
  542         printf("  Board Type: %u  Revision: %u/%u\n",
  543                cvmx_sysinfo_get()->board_type,
  544                cvmx_sysinfo_get()->board_rev_major,
  545                cvmx_sysinfo_get()->board_rev_minor);
  546 
  547         printf("  Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n",
  548             octeon_bootinfo->mac_addr_base[0],
  549             octeon_bootinfo->mac_addr_base[1],
  550             octeon_bootinfo->mac_addr_base[2],
  551             octeon_bootinfo->mac_addr_base[3],
  552             octeon_bootinfo->mac_addr_base[4],
  553             octeon_bootinfo->mac_addr_base[5],
  554             octeon_bootinfo->mac_addr_count);
  555 
  556 #if defined(OCTEON_BOARD_CAPK_0100ND)
  557         if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5)
  558                 printf("Compiled for CAPK-0100ND, but board type is %s\n",
  559                     cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
  560 #else
  561         printf("Board: %s\n",
  562             cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
  563 #endif
  564         printf("Model: %s\n", octeon_model_get_string(cvmx_get_proc_id()));
  565 }
  566 /* impEND: This stuff should move back into the Cavium SDK */

Cache object: b73b48b51a6c3bd7f14f4699c6d9a748


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