The Design and Implementation of the FreeBSD Operating System, Second Edition
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sys/mips/cavium/octeon_machdep.c

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    1 /*-
    2  * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: stable/9/sys/mips/cavium/octeon_machdep.c 217518 2011-01-17 23:03:09Z imp $
   27  */
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: stable/9/sys/mips/cavium/octeon_machdep.c 217518 2011-01-17 23:03:09Z imp $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/conf.h>
   33 #include <sys/kernel.h>
   34 #include <sys/systm.h>
   35 #include <sys/imgact.h>
   36 #include <sys/bio.h>
   37 #include <sys/buf.h>
   38 #include <sys/bus.h>
   39 #include <sys/cpu.h>
   40 #include <sys/cons.h>
   41 #include <sys/exec.h>
   42 #include <sys/ucontext.h>
   43 #include <sys/proc.h>
   44 #include <sys/kdb.h>
   45 #include <sys/ptrace.h>
   46 #include <sys/reboot.h>
   47 #include <sys/signalvar.h>
   48 #include <sys/sysent.h>
   49 #include <sys/sysproto.h>
   50 #include <sys/time.h>
   51 #include <sys/timetc.h>
   52 #include <sys/user.h>
   53 
   54 #include <vm/vm.h>
   55 #include <vm/vm_object.h>
   56 #include <vm/vm_page.h>
   57 #include <vm/vm_pager.h>
   58 
   59 #include <machine/atomic.h>
   60 #include <machine/cache.h>
   61 #include <machine/clock.h>
   62 #include <machine/cpu.h>
   63 #include <machine/cpuregs.h>
   64 #include <machine/cpufunc.h>
   65 #include <mips/cavium/octeon_pcmap_regs.h>
   66 #include <machine/hwfunc.h>
   67 #include <machine/intr_machdep.h>
   68 #include <machine/locore.h>
   69 #include <machine/md_var.h>
   70 #include <machine/pcpu.h>
   71 #include <machine/pte.h>
   72 #include <machine/trap.h>
   73 #include <machine/vmparam.h>
   74 
   75 #include <contrib/octeon-sdk/cvmx.h>
   76 #include <contrib/octeon-sdk/cvmx-bootmem.h>
   77 #include <contrib/octeon-sdk/cvmx-interrupt.h>
   78 #include <contrib/octeon-sdk/cvmx-version.h>
   79 
   80 #if defined(__mips_n64) 
   81 #define MAX_APP_DESC_ADDR     0xffffffffafffffff
   82 #else
   83 #define MAX_APP_DESC_ADDR     0xafffffff
   84 #endif
   85 
   86 #define OCTEON_CLOCK_DEFAULT (500 * 1000 * 1000)
   87 
   88 struct octeon_feature_description {
   89         octeon_feature_t ofd_feature;
   90         const char *ofd_string;
   91 };
   92 
   93 extern int      *edata;
   94 extern int      *end;
   95 extern char cpu_model[];
   96 extern char cpu_board[];
   97 
   98 static const struct octeon_feature_description octeon_feature_descriptions[] = {
   99         { OCTEON_FEATURE_SAAD,                  "SAAD" },
  100         { OCTEON_FEATURE_ZIP,                   "ZIP" },
  101         { OCTEON_FEATURE_CRYPTO,                "CRYPTO" },
  102         { OCTEON_FEATURE_DORM_CRYPTO,           "DORM_CRYPTO" },
  103         { OCTEON_FEATURE_PCIE,                  "PCIE" },
  104         { OCTEON_FEATURE_SRIO,                  "SRIO" },
  105         { OCTEON_FEATURE_KEY_MEMORY,            "KEY_MEMORY" },
  106         { OCTEON_FEATURE_LED_CONTROLLER,        "LED_CONTROLLER" },
  107         { OCTEON_FEATURE_TRA,                   "TRA" },
  108         { OCTEON_FEATURE_MGMT_PORT,             "MGMT_PORT" },
  109         { OCTEON_FEATURE_RAID,                  "RAID" },
  110         { OCTEON_FEATURE_USB,                   "USB" },
  111         { OCTEON_FEATURE_NO_WPTR,               "NO_WPTR" },
  112         { OCTEON_FEATURE_DFA,                   "DFA" },
  113         { OCTEON_FEATURE_MDIO_CLAUSE_45,        "MDIO_CLAUSE_45" },
  114         { OCTEON_FEATURE_NPEI,                  "NPEI" },
  115         { 0,                                    NULL }
  116 };
  117 
  118 uint64_t ciu_get_en_reg_addr_new(int corenum, int intx, int enx, int ciu_ip);
  119 void ciu_dump_interrutps_enabled(int core_num, int intx, int enx, int ciu_ip);
  120 
  121 static uint64_t octeon_get_ticks(void);
  122 static unsigned octeon_get_timecount(struct timecounter *tc);
  123 
  124 static void octeon_boot_params_init(register_t ptr);
  125 
  126 static struct timecounter octeon_timecounter = {
  127         octeon_get_timecount,   /* get_timecount */
  128         0,                      /* no poll_pps */
  129         0xffffffffu,            /* octeon_mask */
  130         0,                      /* frequency */
  131         "Octeon",               /* name */
  132         900,                    /* quality (adjusted in code) */
  133 };
  134 
  135 void
  136 platform_cpu_init()
  137 {
  138         /* Nothing special yet */
  139 }
  140 
  141 /*
  142  * Perform a board-level soft-reset.
  143  */
  144 void
  145 platform_reset(void)
  146 {
  147         cvmx_write_csr(CVMX_CIU_SOFT_RST, 1);
  148 }
  149 
  150 void
  151 octeon_led_write_char(int char_position, char val)
  152 {
  153         uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
  154 
  155         if (octeon_is_simulation())
  156                 return;
  157 
  158         char_position &= 0x7;  /* only 8 chars */
  159         ptr += char_position;
  160         oct_write8_x8(ptr, val);
  161 }
  162 
  163 void
  164 octeon_led_write_char0(char val)
  165 {
  166         uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
  167 
  168         if (octeon_is_simulation())
  169                 return;
  170         oct_write8_x8(ptr, val);
  171 }
  172 
  173 void
  174 octeon_led_write_hexchar(int char_position, char hexval)
  175 {
  176         uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
  177         char char1, char2;
  178 
  179         if (octeon_is_simulation())
  180                 return;
  181 
  182         char1 = (hexval >> 4) & 0x0f; char1 = (char1 < 10)?char1+'':char1+'7';
  183         char2 = (hexval  & 0x0f); char2 = (char2 < 10)?char2+'':char2+'7';
  184         char_position &= 0x7;  /* only 8 chars */
  185         if (char_position > 6)
  186                 char_position = 6;
  187         ptr += char_position;
  188         oct_write8_x8(ptr, char1);
  189         ptr++;
  190         oct_write8_x8(ptr, char2);
  191 }
  192 
  193 void
  194 octeon_led_write_string(const char *str)
  195 {
  196         uint64_t ptr = (OCTEON_CHAR_LED_BASE_ADDR | 0xf8);
  197         int i;
  198 
  199         if (octeon_is_simulation())
  200                 return;
  201 
  202         for (i=0; i<8; i++, ptr++) {
  203                 if (str && *str)
  204                         oct_write8_x8(ptr, *str++);
  205                 else
  206                         oct_write8_x8(ptr, ' ');
  207                 (void)cvmx_read_csr(CVMX_MIO_BOOT_BIST_STAT);
  208         }
  209 }
  210 
  211 static char progress[8] = { '-', '/', '|', '\\', '-', '/', '|', '\\'};
  212 
  213 void
  214 octeon_led_run_wheel(int *prog_count, int led_position)
  215 {
  216         if (octeon_is_simulation())
  217                 return;
  218         octeon_led_write_char(led_position, progress[*prog_count]);
  219         *prog_count += 1;
  220         *prog_count &= 0x7;
  221 }
  222 
  223 void
  224 octeon_led_write_hex(uint32_t wl)
  225 {
  226         char nbuf[80];
  227 
  228         sprintf(nbuf, "%X", wl);
  229         octeon_led_write_string(nbuf);
  230 }
  231 
  232 /*
  233  * octeon_debug_symbol
  234  *
  235  * Does nothing.
  236  * Used to mark the point for simulator to begin tracing
  237  */
  238 void
  239 octeon_debug_symbol(void)
  240 {
  241 }
  242 
  243 /*
  244  * octeon_ciu_reset
  245  *
  246  * Shutdown all CIU to IP2, IP3 mappings
  247  */
  248 void
  249 octeon_ciu_reset(void)
  250 {
  251         /* Disable all CIU interrupts by default */
  252         cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2), 0);
  253         cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1), 0);
  254         cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2), 0);
  255         cvmx_write_csr(CVMX_CIU_INTX_EN1(cvmx_get_core_num()*2+1), 0);
  256 
  257 #ifdef SMP
  258         /* Enable the MBOX interrupts.  */
  259         cvmx_write_csr(CVMX_CIU_INTX_EN0(cvmx_get_core_num()*2+1),
  260                        (1ull << (CVMX_IRQ_MBOX0 - 8)) |
  261                        (1ull << (CVMX_IRQ_MBOX1 - 8)));
  262 #endif
  263 }
  264 
  265 static void
  266 octeon_memory_init(void)
  267 {
  268         vm_paddr_t phys_end;
  269         int64_t addr;
  270         unsigned i, j;
  271 
  272         phys_end = round_page(MIPS_KSEG0_TO_PHYS((vm_offset_t)&end));
  273 
  274         if (octeon_is_simulation()) {
  275                 /* Simulator we limit to 96 meg */
  276                 phys_avail[0] = phys_end;
  277                 phys_avail[1] = 96 << 20;
  278 
  279                 dump_avail[0] = phys_avail[0];
  280                 dump_avail[1] = phys_avail[1];
  281 
  282                 realmem = physmem = btoc(phys_avail[1] - phys_avail[0]);
  283                 return;
  284         }
  285 
  286         /*
  287          * Allocate memory from bootmem 1MB at a time and merge
  288          * adjacent entries.
  289          */
  290         i = 0;
  291         while (i < PHYS_AVAIL_ENTRIES) {
  292                 /*
  293                  * If there is less than 2MB of memory available in 128-byte
  294                  * blocks, do not steal any more memory.  We need to leave some
  295                  * memory for the command queues to be allocated out of.
  296                  */
  297                 if (cvmx_bootmem_available_mem(128) < 2 << 20)
  298                         break;
  299 
  300                 addr = cvmx_bootmem_phy_alloc(1 << 20, phys_end,
  301                                               ~(vm_paddr_t)0, PAGE_SIZE, 0);
  302                 if (addr == -1)
  303                         break;
  304 
  305                 /*
  306                  * The SDK needs to be able to easily map any memory that might
  307                  * come to it e.g. in the form of an mbuf.  Because on !n64 we
  308                  * can't direct-map some addresses and we don't want to manage
  309                  * temporary mappings within the SDK, don't feed memory that
  310                  * can't be direct-mapped to the kernel.
  311                  */
  312 #if !defined(__mips_n64)
  313                 if (!MIPS_DIRECT_MAPPABLE(addr + (1 << 20) - 1))
  314                         continue;
  315 #endif
  316 
  317                 physmem += btoc(1 << 20);
  318 
  319                 if (i > 0 && phys_avail[i - 1] == addr) {
  320                         phys_avail[i - 1] += 1 << 20;
  321                         continue;
  322                 }
  323 
  324                 phys_avail[i + 0] = addr;
  325                 phys_avail[i + 1] = addr + (1 << 20);
  326 
  327                 i += 2;
  328         }
  329 
  330         for (j = 0; j < i; j++)
  331                 dump_avail[j] = phys_avail[j];
  332 
  333         realmem = physmem;
  334 }
  335 
  336 void
  337 platform_start(__register_t a0, __register_t a1, __register_t a2 __unused,
  338     __register_t a3)
  339 {
  340         const struct octeon_feature_description *ofd;
  341         uint64_t platform_counter_freq;
  342 
  343         /*
  344          * XXX
  345          * octeon_boot_params_init() should be called before anything else,
  346          * certainly before any output; we may find out from the boot
  347          * descriptor's flags that we're supposed to use the PCI or UART1
  348          * consoles rather than UART0.  No point doing that reorganization
  349          * until we actually intercept UART_DEV_CONSOLE for the UART1 case
  350          * and somehow handle the PCI console, which we lack code for
  351          * entirely.
  352          */
  353 
  354         /* Initialize pcpu stuff */
  355         mips_pcpu0_init();
  356         mips_timer_early_init(OCTEON_CLOCK_DEFAULT);
  357         cninit();
  358 
  359         octeon_ciu_reset();
  360         octeon_boot_params_init(a3);
  361         /*
  362          * XXX
  363          * We can certainly parse command line arguments or U-Boot environment
  364          * to determine whether to bootverbose / single user / ...  I think
  365          * stass has patches to add support for loader things to U-Boot even.
  366          */
  367         bootverbose = 1;
  368 
  369         /*
  370          * For some reason on the cn38xx simulator ebase register is set to
  371          * 0x80001000 at bootup time.  Move it back to the default, but
  372          * when we move to having support for multiple executives, we need
  373          * to rethink this.
  374          */
  375         mips_wr_ebase(0x80000000);
  376 
  377         octeon_memory_init();
  378         init_param1();
  379         init_param2(physmem);
  380         mips_cpu_init();
  381         pmap_bootstrap();
  382         mips_proc0_init();
  383         mutex_init();
  384         kdb_init();
  385 #ifdef KDB
  386         if (boothowto & RB_KDB)
  387                 kdb_enter(KDB_WHY_BOOTFLAGS, "Boot flags requested debugger");
  388 #endif
  389         cpu_clock = cvmx_sysinfo_get()->cpu_clock_hz;
  390         platform_counter_freq = cpu_clock;
  391         octeon_timecounter.tc_frequency = cpu_clock;
  392         platform_timecounter = &octeon_timecounter;
  393         mips_timer_init_params(platform_counter_freq, 0);
  394         set_cputicker(octeon_get_ticks, cpu_clock, 0);
  395 
  396 #ifdef SMP
  397         /*
  398          * Clear any pending IPIs.
  399          */
  400         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(0), 0xffffffff);
  401 #endif
  402 
  403         printf("Octeon SDK: %s\n", OCTEON_SDK_VERSION_STRING);
  404         printf("Available Octeon features:");
  405         for (ofd = octeon_feature_descriptions; ofd->ofd_string != NULL; ofd++)
  406                 if (octeon_has_feature(ofd->ofd_feature))
  407                         printf(" %s", ofd->ofd_string);
  408         printf("\n");
  409 }
  410 
  411 static uint64_t
  412 octeon_get_ticks(void)
  413 {
  414         uint64_t cvmcount;
  415 
  416         CVMX_MF_CYCLE(cvmcount);
  417         return (cvmcount);
  418 }
  419 
  420 static unsigned
  421 octeon_get_timecount(struct timecounter *tc)
  422 {
  423         return ((unsigned)octeon_get_ticks());
  424 }
  425 
  426 /**
  427  * version of printf that works better in exception context.
  428  *
  429  * @param format
  430  *
  431  * XXX If this function weren't in cvmx-interrupt.c, we'd use the SDK version.
  432  */
  433 void cvmx_safe_printf(const char *format, ...)
  434 {
  435     char buffer[256];
  436     char *ptr = buffer;
  437     int count;
  438     va_list args;
  439 
  440     va_start(args, format);
  441 #ifndef __U_BOOT__
  442     count = vsnprintf(buffer, sizeof(buffer), format, args);
  443 #else
  444     count = vsprintf(buffer, format, args);
  445 #endif
  446     va_end(args);
  447 
  448     while (count-- > 0)
  449     {
  450         cvmx_uart_lsr_t lsrval;
  451 
  452         /* Spin until there is room */
  453         do
  454         {
  455             lsrval.u64 = cvmx_read_csr(CVMX_MIO_UARTX_LSR(0));
  456 #if !defined(CONFIG_OCTEON_SIM_SPEED)
  457             if (lsrval.s.temt == 0)
  458                 cvmx_wait(10000);   /* Just to reduce the load on the system */
  459 #endif
  460         }
  461         while (lsrval.s.temt == 0);
  462 
  463         if (*ptr == '\n')
  464             cvmx_write_csr(CVMX_MIO_UARTX_THR(0), '\r');
  465         cvmx_write_csr(CVMX_MIO_UARTX_THR(0), *ptr++);
  466     }
  467 }
  468 
  469 /* impSTART: This stuff should move back into the Cavium SDK */
  470 /*
  471  ****************************************************************************************
  472  *
  473  * APP/BOOT  DESCRIPTOR  STUFF
  474  *
  475  ****************************************************************************************
  476  */
  477 
  478 /* Define the struct that is initialized by the bootloader used by the 
  479  * startup code.
  480  *
  481  * Copyright (c) 2004, 2005, 2006 Cavium Networks.
  482  *
  483  * The authors hereby grant permission to use, copy, modify, distribute,
  484  * and license this software and its documentation for any purpose, provided
  485  * that existing copyright notices are retained in all copies and that this
  486  * notice is included verbatim in any distributions. No written agreement,
  487  * license, or royalty fee is required for any of the authorized uses.
  488  * Modifications to this software may be copyrighted by their authors
  489  * and need not follow the licensing terms described here, provided that
  490  * the new terms are clearly indicated on the first page of each file where
  491  * they apply.
  492  */
  493 
  494 #define OCTEON_CURRENT_DESC_VERSION     6
  495 #define OCTEON_ARGV_MAX_ARGS            (64)
  496 #define OCTOEN_SERIAL_LEN 20
  497 
  498 typedef struct {
  499         /* Start of block referenced by assembly code - do not change! */
  500         uint32_t desc_version;
  501         uint32_t desc_size;
  502 
  503         uint64_t stack_top;
  504         uint64_t heap_base;
  505         uint64_t heap_end;
  506         uint64_t entry_point;   /* Only used by bootloader */
  507         uint64_t desc_vaddr;
  508         /* End of This block referenced by assembly code - do not change! */
  509 
  510         uint32_t exception_base_addr;
  511         uint32_t stack_size;
  512         uint32_t heap_size;
  513         uint32_t argc;  /* Argc count for application */
  514         uint32_t argv[OCTEON_ARGV_MAX_ARGS];
  515         uint32_t flags;
  516         uint32_t core_mask;
  517         uint32_t dram_size;  /**< DRAM size in megabyes */
  518         uint32_t phy_mem_desc_addr;  /**< physical address of free memory descriptor block*/
  519         uint32_t debugger_flags_base_addr;  /**< used to pass flags from app to debugger */
  520         uint32_t eclock_hz;  /**< CPU clock speed, in hz */
  521         uint32_t dclock_hz;  /**< DRAM clock speed, in hz */
  522         uint32_t spi_clock_hz;  /**< SPI4 clock in hz */
  523         uint16_t board_type;
  524         uint8_t board_rev_major;
  525         uint8_t board_rev_minor;
  526         uint16_t chip_type;
  527         uint8_t chip_rev_major;
  528         uint8_t chip_rev_minor;
  529         char board_serial_number[OCTOEN_SERIAL_LEN];
  530         uint8_t mac_addr_base[6];
  531         uint8_t mac_addr_count;
  532         uint64_t cvmx_desc_vaddr;
  533 } octeon_boot_descriptor_t;
  534 
  535 cvmx_bootinfo_t *octeon_bootinfo;
  536 
  537 static octeon_boot_descriptor_t *app_desc_ptr;
  538 
  539 int
  540 octeon_is_simulation(void)
  541 {
  542         switch (cvmx_sysinfo_get()->board_type) {
  543         case CVMX_BOARD_TYPE_SIM:
  544                 return 1;
  545         default:
  546                 return 0;
  547         }
  548 }
  549 
  550 static void
  551 octeon_process_app_desc_ver_6(void)
  552 {
  553         /* XXX Why is 0x00000000ffffffffULL a bad value?  */
  554         if (app_desc_ptr->cvmx_desc_vaddr == 0 ||
  555             app_desc_ptr->cvmx_desc_vaddr == 0xfffffffful)
  556                 panic("Bad octeon_bootinfo %p", octeon_bootinfo);
  557 
  558         octeon_bootinfo =
  559             (cvmx_bootinfo_t *)(intptr_t)app_desc_ptr->cvmx_desc_vaddr;
  560         octeon_bootinfo =
  561             (cvmx_bootinfo_t *) ((intptr_t)octeon_bootinfo | MIPS_KSEG0_START);
  562         if (octeon_bootinfo->major_version != 1)
  563                 panic("Incompatible CVMX descriptor from bootloader: %d.%d %p",
  564                        (int) octeon_bootinfo->major_version,
  565                        (int) octeon_bootinfo->minor_version, octeon_bootinfo);
  566 
  567         cvmx_sysinfo_minimal_initialize(octeon_bootinfo->phy_mem_desc_addr,
  568                                         octeon_bootinfo->board_type,
  569                                         octeon_bootinfo->board_rev_major,
  570                                         octeon_bootinfo->board_rev_minor,
  571                                         octeon_bootinfo->eclock_hz);
  572 }
  573 
  574 static void
  575 octeon_boot_params_init(register_t ptr)
  576 {
  577         if (ptr == 0 || ptr >= MAX_APP_DESC_ADDR)
  578                 panic("app descriptor passed at invalid address %#jx",
  579                     (uintmax_t)ptr);
  580 
  581         app_desc_ptr = (octeon_boot_descriptor_t *)(intptr_t)ptr;
  582         if (app_desc_ptr->desc_version < 6)
  583                 panic("Your boot code is too old to be supported.");
  584         octeon_process_app_desc_ver_6();
  585 
  586         KASSERT(octeon_bootinfo != NULL, ("octeon_bootinfo should be set"));
  587 
  588         if (cvmx_sysinfo_get()->phy_mem_desc_addr == (uint64_t)0)
  589                 panic("Your boot loader did not supply a memory descriptor.");
  590         cvmx_bootmem_init(cvmx_sysinfo_get()->phy_mem_desc_addr);
  591 
  592         printf("Boot Descriptor Ver: %u -> %u/%u",
  593                app_desc_ptr->desc_version, octeon_bootinfo->major_version,
  594                octeon_bootinfo->minor_version);
  595         printf("  CPU clock: %uMHz  Core Mask: %#x\n",
  596                cvmx_sysinfo_get()->cpu_clock_hz / 1000000,
  597                cvmx_sysinfo_get()->core_mask);
  598         printf("  Board Type: %u  Revision: %u/%u\n",
  599                cvmx_sysinfo_get()->board_type,
  600                cvmx_sysinfo_get()->board_rev_major,
  601                cvmx_sysinfo_get()->board_rev_minor);
  602 
  603         printf("  Mac Address %02X.%02X.%02X.%02X.%02X.%02X (%d)\n",
  604             octeon_bootinfo->mac_addr_base[0],
  605             octeon_bootinfo->mac_addr_base[1],
  606             octeon_bootinfo->mac_addr_base[2],
  607             octeon_bootinfo->mac_addr_base[3],
  608             octeon_bootinfo->mac_addr_base[4],
  609             octeon_bootinfo->mac_addr_base[5],
  610             octeon_bootinfo->mac_addr_count);
  611 
  612 #if defined(OCTEON_BOARD_CAPK_0100ND)
  613         strcpy(cpu_board, "CAPK-0100ND");
  614         if (cvmx_sysinfo_get()->board_type != CVMX_BOARD_TYPE_CN3010_EVB_HS5) {
  615                 printf("Compiled for CAPK-0100ND, but board type is %s\n",
  616                     cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
  617                 strcat(cpu_board, " hardwired, but type is ");
  618                 strcat(cpu_board, 
  619                     cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
  620         }
  621 #else
  622         strcpy(cpu_board,
  623             cvmx_board_type_to_string(cvmx_sysinfo_get()->board_type));
  624         printf("Board: %s\n", cpu_board);
  625 #endif
  626         strcpy(cpu_model, octeon_model_get_string(cvmx_get_proc_id()));
  627         printf("Model: %s\n", cpu_model);
  628 }
  629 /* impEND: This stuff should move back into the Cavium SDK */

Cache object: 1e445a36170f81f26f7d55d887587dc8


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