The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/cavium/octeon_mp.c

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    1 /*-
    2  * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: releng/11.1/sys/mips/cavium/octeon_mp.c 232812 2012-03-11 06:17:49Z jmallett $
   27  */
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: releng/11.1/sys/mips/cavium/octeon_mp.c 232812 2012-03-11 06:17:49Z jmallett $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/conf.h>
   33 #include <sys/kernel.h>
   34 #include <sys/smp.h>
   35 #include <sys/systm.h>
   36 
   37 #include <machine/hwfunc.h>
   38 #include <machine/md_var.h>
   39 #include <machine/smp.h>
   40 
   41 #include <mips/cavium/octeon_pcmap_regs.h>
   42 
   43 #include <contrib/octeon-sdk/cvmx.h>
   44 #include <mips/cavium/octeon_irq.h>
   45 
   46 unsigned octeon_ap_boot = ~0;
   47 
   48 void
   49 platform_ipi_send(int cpuid)
   50 {
   51         cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1);
   52         mips_wbflush();
   53 }
   54 
   55 void
   56 platform_ipi_clear(void)
   57 {
   58         uint64_t action;
   59 
   60         action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)));
   61         KASSERT(action == 1, ("unexpected IPIs: %#jx", (uintmax_t)action));
   62         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action);
   63 }
   64 
   65 int
   66 platform_ipi_intrnum(void)
   67 {
   68         return (1);
   69 }
   70 
   71 void
   72 platform_init_ap(int cpuid)
   73 {
   74         unsigned ciu_int_mask, clock_int_mask, ipi_int_mask;
   75 
   76         /*
   77          * Set the exception base.
   78          */
   79         mips_wr_ebase(0x80000000);
   80 
   81         /*
   82          * Clear any pending IPIs.
   83          */
   84         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff);
   85 
   86         /*
   87          * Set up interrupts.
   88          */
   89         octeon_ciu_reset();
   90 
   91         /*
   92          * Unmask the clock, ipi and ciu interrupts.
   93          */
   94         ciu_int_mask = hard_int_mask(0);
   95         clock_int_mask = hard_int_mask(5);
   96         ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
   97         set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask);
   98 
   99         mips_wbflush();
  100 }
  101 
  102 void
  103 platform_cpu_mask(cpuset_t *mask)
  104 {
  105         uint64_t core_mask = cvmx_sysinfo_get()->core_mask;
  106         uint64_t i, m;
  107 
  108         CPU_ZERO(mask);
  109         for (i = 0, m = 1 ; i < MAXCPU; i++, m <<= 1)
  110                 if (core_mask & m)
  111                         CPU_SET(i, mask);
  112 }
  113 
  114 struct cpu_group *
  115 platform_smp_topo(void)
  116 {
  117         return (smp_topo_none());
  118 }
  119 
  120 int
  121 platform_start_ap(int cpuid)
  122 {
  123         uint64_t cores_in_reset;
  124 
  125         /* 
  126          * Release the core if it is in reset, and let it rev up a bit.
  127          * The real synchronization happens below via octeon_ap_boot.
  128          */
  129         cores_in_reset = cvmx_read_csr(CVMX_CIU_PP_RST);
  130         if (cores_in_reset & (1ULL << cpuid)) {
  131             if (bootverbose)
  132                 printf ("AP #%d still in reset\n", cpuid);
  133             cores_in_reset &= ~(1ULL << cpuid);
  134             cvmx_write_csr(CVMX_CIU_PP_RST, (uint64_t)(cores_in_reset));
  135             DELAY(2000);    /* Give it a moment to start */
  136         }
  137 
  138         if (atomic_cmpset_32(&octeon_ap_boot, ~0, cpuid) == 0)
  139                 return (-1);
  140         for (;;) {
  141                 DELAY(1000);
  142                 if (atomic_cmpset_32(&octeon_ap_boot, 0, ~0) != 0)
  143                         return (0);
  144                 printf("Waiting for cpu%d to start\n", cpuid);
  145         }
  146 }

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