The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/cavium/octeon_mp.c

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    1 /*-
    2  * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: stable/9/sys/mips/cavium/octeon_mp.c 224661 2011-08-05 22:54:42Z marcel $
   27  */
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: stable/9/sys/mips/cavium/octeon_mp.c 224661 2011-08-05 22:54:42Z marcel $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/conf.h>
   33 #include <sys/kernel.h>
   34 #include <sys/smp.h>
   35 #include <sys/systm.h>
   36 
   37 #include <machine/hwfunc.h>
   38 #include <machine/md_var.h>
   39 #include <machine/smp.h>
   40 
   41 #include <mips/cavium/octeon_pcmap_regs.h>
   42 
   43 #include <contrib/octeon-sdk/cvmx.h>
   44 #include <contrib/octeon-sdk/cvmx-interrupt.h>
   45 
   46 /* XXX */
   47 extern cvmx_bootinfo_t *octeon_bootinfo;
   48 
   49 /* NOTE: this 64-bit mask (and many others) limits MAXCPU to 64 */
   50 uint64_t octeon_ap_boot = ~0ULL;
   51 
   52 void
   53 platform_ipi_send(int cpuid)
   54 {
   55         cvmx_write_csr(CVMX_CIU_MBOX_SETX(cpuid), 1);
   56         mips_wbflush();
   57 }
   58 
   59 void
   60 platform_ipi_clear(void)
   61 {
   62         uint64_t action;
   63 
   64         action = cvmx_read_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)));
   65         KASSERT(action == 1, ("unexpected IPIs: %#jx", (uintmax_t)action));
   66         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(PCPU_GET(cpuid)), action);
   67 }
   68 
   69 int
   70 platform_ipi_intrnum(void)
   71 {
   72         return (1);
   73 }
   74 
   75 void
   76 platform_init_ap(int cpuid)
   77 {
   78         unsigned ciu_int_mask, clock_int_mask, ipi_int_mask;
   79 
   80         /*
   81          * Set the exception base.
   82          */
   83         mips_wr_ebase(0x80000000);
   84 
   85         /*
   86          * Clear any pending IPIs.
   87          */
   88         cvmx_write_csr(CVMX_CIU_MBOX_CLRX(cpuid), 0xffffffff);
   89 
   90         /*
   91          * Set up interrupts.
   92          */
   93         octeon_ciu_reset();
   94 
   95         /*
   96          * Unmask the clock, ipi and ciu interrupts.
   97          */
   98         ciu_int_mask = hard_int_mask(0);
   99         clock_int_mask = hard_int_mask(5);
  100         ipi_int_mask = hard_int_mask(platform_ipi_intrnum());
  101         set_intr_mask(ciu_int_mask | clock_int_mask | ipi_int_mask);
  102 
  103         mips_wbflush();
  104 }
  105 
  106 void
  107 platform_cpu_mask(cpuset_t *mask)
  108 {
  109         uint64_t core_mask = octeon_bootinfo->core_mask;
  110         uint64_t i, m;
  111 
  112         CPU_ZERO(mask);
  113         for (i = 0, m = 1 ; i < MAXCPU; i++, m <<= 1)
  114                 if (core_mask & m)
  115                         CPU_SET(i, mask);
  116 }
  117 
  118 struct cpu_group *
  119 platform_smp_topo(void)
  120 {
  121         return (smp_topo_none());
  122 }
  123 
  124 int
  125 platform_start_ap(int cpuid)
  126 {
  127         uint64_t cores_in_reset;
  128 
  129         /* 
  130          * Release the core if it is in reset, and let it rev up a bit.
  131          * The real synchronization happens below via octeon_ap_boot.
  132          */
  133         cores_in_reset = cvmx_read_csr(CVMX_CIU_PP_RST);
  134         if (cores_in_reset & (1ULL << cpuid)) {
  135             if (bootverbose)
  136                 printf ("AP #%d still in reset\n", cpuid);
  137             cores_in_reset &= ~(1ULL << cpuid);
  138             cvmx_write_csr(CVMX_CIU_PP_RST, (uint64_t)(cores_in_reset));
  139             DELAY(2000);    /* Give it a moment to start */
  140         }
  141 
  142         if (atomic_cmpset_64(&octeon_ap_boot, ~0, cpuid) == 0)
  143                 return (-1);
  144         for (;;) {
  145                 DELAY(1000);
  146                 if (atomic_cmpset_64(&octeon_ap_boot, 0, ~0) != 0)
  147                         return (0);
  148                 printf("Waiting for cpu%d to start\n", cpuid);
  149         }
  150 }

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