1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 *
4 * Copyright (c) 2009, Oleksandr Tymoshenko <gonzo@FreeBSD.org>
5 * Copyright (c) 2010-2011, Juli Mallett <jmallett@FreeBSD.org>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice unmodified, this list of conditions, and the following
13 * disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * SUCH DAMAGE.
29 */
30
31 /*
32 * Watchdog driver for Cavium Octeon
33 */
34
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD: releng/12.0/sys/mips/cavium/octeon_wdog.c 326259 2017-11-27 15:07:26Z pfg $");
37
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/watchdog.h>
41 #include <sys/bus.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
44 #include <sys/sysctl.h>
45 #include <sys/rman.h>
46 #include <sys/smp.h>
47
48 #include <contrib/octeon-sdk/cvmx.h>
49 #include <mips/cavium/octeon_irq.h>
50
51 #define DEFAULT_TIMER_VAL 65535
52
53 struct octeon_wdog_softc {
54 device_t sc_dev;
55 struct octeon_wdog_core_softc {
56 int csc_core;
57 struct resource *csc_intr;
58 void *csc_intr_cookie;
59 } sc_cores[MAXCPU];
60 int sc_armed;
61 int sc_debug;
62 };
63
64 extern void octeon_wdog_nmi_handler(void);
65 void octeon_wdog_nmi(void);
66
67 static void octeon_watchdog_arm_core(int);
68 static void octeon_watchdog_disarm_core(int);
69 static int octeon_wdog_attach(device_t);
70 static void octeon_wdog_identify(driver_t *, device_t);
71 static int octeon_wdog_intr(void *);
72 static int octeon_wdog_probe(device_t);
73 static void octeon_wdog_setup(struct octeon_wdog_softc *, int);
74 static void octeon_wdog_sysctl(device_t);
75 static void octeon_wdog_watchdog_fn(void *, u_int, int *);
76
77 void
78 octeon_wdog_nmi(void)
79 {
80 int core;
81
82 core = cvmx_get_core_num();
83
84 printf("cpu%u: NMI detected\n", core);
85 printf("cpu%u: Exception PC: %p\n", core, (void *)mips_rd_excpc());
86 printf("cpu%u: status %#x cause %#x\n", core, mips_rd_status(), mips_rd_cause());
87
88 /*
89 * This is the end
90 * Beautiful friend
91 *
92 * Just wait for Soft Reset to come and take us
93 */
94 for (;;)
95 continue;
96 }
97
98 static void
99 octeon_watchdog_arm_core(int core)
100 {
101 cvmx_ciu_wdogx_t ciu_wdog;
102
103 /* Poke it! */
104 cvmx_write_csr(CVMX_CIU_PP_POKEX(core), 1);
105
106 /*
107 * XXX
108 * Perhaps if KDB is enabled, we should use mode=2 and drop into the
109 * debugger on NMI?
110 *
111 * XXX
112 * Timer should be calculated based on CPU frquency
113 */
114 ciu_wdog.u64 = 0;
115 ciu_wdog.s.len = DEFAULT_TIMER_VAL;
116 ciu_wdog.s.mode = 3;
117 cvmx_write_csr(CVMX_CIU_WDOGX(core), ciu_wdog.u64);
118 }
119
120 static void
121 octeon_watchdog_disarm_core(int core)
122 {
123
124 cvmx_write_csr(CVMX_CIU_WDOGX(core), 0);
125 }
126
127 static void
128 octeon_wdog_watchdog_fn(void *private, u_int cmd, int *error)
129 {
130 struct octeon_wdog_softc *sc = private;
131 int core;
132
133 cmd &= WD_INTERVAL;
134 if (sc->sc_debug)
135 device_printf(sc->sc_dev, "%s: cmd: %x\n", __func__, cmd);
136 if (cmd > 0) {
137 CPU_FOREACH(core)
138 octeon_watchdog_arm_core(core);
139 sc->sc_armed = 1;
140 *error = 0;
141 } else {
142 if (sc->sc_armed) {
143 CPU_FOREACH(core)
144 octeon_watchdog_disarm_core(core);
145 sc->sc_armed = 0;
146 }
147 }
148 }
149
150 static void
151 octeon_wdog_sysctl(device_t dev)
152 {
153 struct octeon_wdog_softc *sc = device_get_softc(dev);
154
155 struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(sc->sc_dev);
156 struct sysctl_oid *tree = device_get_sysctl_tree(sc->sc_dev);
157
158 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
159 "debug", CTLFLAG_RW, &sc->sc_debug, 0,
160 "enable watchdog debugging");
161 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
162 "armed", CTLFLAG_RD, &sc->sc_armed, 0,
163 "whether the watchdog is armed");
164 }
165
166 static void
167 octeon_wdog_setup(struct octeon_wdog_softc *sc, int core)
168 {
169 struct octeon_wdog_core_softc *csc;
170 int rid, error;
171
172 csc = &sc->sc_cores[core];
173
174 csc->csc_core = core;
175
176 /* Interrupt part */
177 rid = 0;
178 csc->csc_intr = bus_alloc_resource(sc->sc_dev, SYS_RES_IRQ, &rid,
179 OCTEON_IRQ_WDOG0 + core, OCTEON_IRQ_WDOG0 + core, 1, RF_ACTIVE);
180 if (csc->csc_intr == NULL)
181 panic("%s: bus_alloc_resource for core %u failed",
182 __func__, core);
183
184 error = bus_setup_intr(sc->sc_dev, csc->csc_intr, INTR_TYPE_MISC,
185 octeon_wdog_intr, NULL, csc, &csc->csc_intr_cookie);
186 if (error != 0)
187 panic("%s: bus_setup_intr for core %u: %d", __func__, core,
188 error);
189
190 bus_bind_intr(sc->sc_dev, csc->csc_intr, core);
191 bus_describe_intr(sc->sc_dev, csc->csc_intr, csc->csc_intr_cookie,
192 "cpu%u", core);
193
194 if (sc->sc_armed) {
195 /* Armed by default. */
196 octeon_watchdog_arm_core(core);
197 } else {
198 /* Disarmed by default. */
199 octeon_watchdog_disarm_core(core);
200 }
201 }
202
203 static int
204 octeon_wdog_intr(void *arg)
205 {
206 struct octeon_wdog_core_softc *csc = arg;
207
208 KASSERT(csc->csc_core == cvmx_get_core_num(),
209 ("got watchdog interrupt for core %u on core %u.",
210 csc->csc_core, cvmx_get_core_num()));
211
212 (void)csc;
213
214 /* Poke it! */
215 cvmx_write_csr(CVMX_CIU_PP_POKEX(cvmx_get_core_num()), 1);
216
217 return (FILTER_HANDLED);
218 }
219
220 static int
221 octeon_wdog_probe(device_t dev)
222 {
223
224 device_set_desc(dev, "Cavium Octeon watchdog timer");
225 return (0);
226 }
227
228 static int
229 octeon_wdog_attach(device_t dev)
230 {
231 struct octeon_wdog_softc *sc = device_get_softc(dev);
232 uint64_t *nmi_handler = (uint64_t*)octeon_wdog_nmi_handler;
233 int core, i;
234
235 /* Initialise */
236 sc->sc_armed = 0; /* XXX Ought to be a tunable / config option. */
237 sc->sc_debug = 0;
238
239 sc->sc_dev = dev;
240 EVENTHANDLER_REGISTER(watchdog_list, octeon_wdog_watchdog_fn, sc, 0);
241 octeon_wdog_sysctl(dev);
242
243 for (i = 0; i < 16; i++) {
244 cvmx_write_csr(CVMX_MIO_BOOT_LOC_ADR, i * 8);
245 cvmx_write_csr(CVMX_MIO_BOOT_LOC_DAT, nmi_handler[i]);
246 }
247
248 cvmx_write_csr(CVMX_MIO_BOOT_LOC_CFGX(0), 0x81fc0000);
249
250 CPU_FOREACH(core)
251 octeon_wdog_setup(sc, core);
252 return (0);
253 }
254
255 static void
256 octeon_wdog_identify(driver_t *drv, device_t parent)
257 {
258
259 BUS_ADD_CHILD(parent, 0, "owdog", 0);
260 }
261
262 static device_method_t octeon_wdog_methods[] = {
263 DEVMETHOD(device_identify, octeon_wdog_identify),
264
265 DEVMETHOD(device_probe, octeon_wdog_probe),
266 DEVMETHOD(device_attach, octeon_wdog_attach),
267 {0, 0},
268 };
269
270 static driver_t octeon_wdog_driver = {
271 "owdog",
272 octeon_wdog_methods,
273 sizeof(struct octeon_wdog_softc),
274 };
275 static devclass_t octeon_wdog_devclass;
276
277 DRIVER_MODULE(owdog, ciu, octeon_wdog_driver, octeon_wdog_devclass, 0, 0);
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