1 /* $NetBSD: octeonreg.h,v 1.1 2002/03/07 14:44:04 simonb Exp $ */
2
3 /*
4 * Copyright 2002 Wasabi Systems, Inc.
5 * All rights reserved.
6 *
7 * Written by Simon Burge for Wasabi Systems, Inc.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. All advertising materials mentioning features or use of this software
18 * must display the following acknowledgement:
19 * This product includes software developed for the NetBSD Project by
20 * Wasabi Systems, Inc.
21 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
22 * or promote products derived from this software without specific prior
23 * written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
27 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
28 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
29 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
30 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
31 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
32 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
33 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
35 * POSSIBILITY OF SUCH DAMAGE.
36 */
37
38 /*
39 Memory Map
40
41 0000.0000 * 128MB Typically SDRAM (on Core Board)
42 0800.0000 * 256MB Typically PCI
43 1800.0000 * 62MB Typically PCI
44 1be0.0000 * 2MB Typically System controller's internal registers
45 1c00.0000 * 32MB Typically not used
46 1e00.0000 4MB Monitor Flash
47 1e40.0000 12MB reserved
48 1f00.0000 12MB Switches
49 LEDs
50 ASCII display
51 Soft reset
52 FPGA revision number
53 CBUS UART (tty2)
54 General Purpose I/O
55 I2C controller
56 1f10.0000 * 11MB Typically System Controller specific
57 1fc0.0000 4MB Maps to Monitor Flash
58 1fd0.0000 * 3MB Typically System Controller specific
59
60 * depends on implementation of the Core Board and of software
61 */
62
63 /*
64 CPU interrupts
65
66 NMI South Bridge or NMI button
67 0 South Bridge INTR
68 1 South Bridge SMI
69 2 CBUS UART (tty2)
70 3 COREHI (Core Card)
71 4 CORELO (Core Card)
72 5 Not used, driven inactive (typically CPU internal timer interrupt
73
74 IRQ mapping (as used by YAMON)
75
76 0 Timer South Bridge
77 1 Keyboard SuperIO
78 2 Reserved by South Bridge (for cascading)
79 3 UART (tty1) SuperIO
80 4 UART (tty0) SuperIO
81 5 Not used
82 6 Floppy Disk SuperIO
83 7 Parallel Port SuperIO
84 8 Real Time Clock South Bridge
85 9 I2C bus South Bridge
86 10 PCI A,B,eth PCI slot 1..4, Ethernet
87 11 PCI C,audio PCI slot 1..4, Audio, USB (South Bridge)
88 PCI D,USB
89 12 Mouse SuperIO
90 13 Reserved by South Bridge
91 14 Primary IDE Primary IDE slot
92 15 Secondary IDE Secondary IDE slot/Compact flash connector
93 */
94
95 #define OCTEON_SYSTEMRAM_BASE 0x00000000 /* System RAM: */
96 #define OCTEON_SYSTEMRAM_SIZE 0x08000000 /* 128 MByte */
97
98 #define OCTEON_PCIMEM1_BASE 0x08000000 /* PCI 1 memory: */
99 #define OCTEON_PCIMEM1_SIZE 0x08000000 /* 128 MByte */
100
101 #define OCTEON_PCIMEM2_BASE 0x10000000 /* PCI 2 memory: */
102 #define OCTEON_PCIMEM2_SIZE 0x08000000 /* 128 MByte */
103
104 #define OCTEON_PCIMEM3_BASE 0x18000000 /* PCI 3 memory */
105 #define OCTEON_PCIMEM3_SIZE 0x03e00000 /* 62 MByte */
106
107 #define OCTEON_CORECTRL_BASE 0x1be00000 /* Core control: */
108 #define OCTEON_CORECTRL_SIZE 0x00200000 /* 2 MByte */
109
110 #define OCTEON_RESERVED_BASE1 0x1c000000 /* Reserved: */
111 #define OCTEON_RESERVED_SIZE1 0x02000000 /* 32 MByte */
112
113 #define OCTEON_MONITORFLASH_BASE 0x1e000000 /* Monitor Flash: */
114 #define OCTEON_MONITORFLASH_SIZE 0x003e0000 /* 4 MByte */
115 #define OCTEON_MONITORFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
116
117 #define OCTEON_FILEFLASH_BASE 0x1e3e0000 /* File Flash (for monitor): */
118 #define OCTEON_FILEFLASH_SIZE 0x00020000 /* 128 KByte */
119
120 #define OCTEON_FILEFLASH_SECTORSIZE 0x00010000 /* Sect. = 64 KB */
121
122 #define OCTEON_RESERVED_BASE2 0x1e400000 /* Reserved: */
123 #define OCTEON_RESERVED_SIZE2 0x00c00000 /* 12 MByte */
124
125 #define OCTEON_FPGA_BASE 0x1f000000 /* FPGA: */
126 #define OCTEON_FPGA_SIZE 0x00c00000 /* 12 MByte */
127
128 #define OCTEON_NMISTATUS (OCTEON_FPGA_BASE + 0x24)
129 #define OCTEON_NMI_SB 0x2 /* Pending NMI from the South Bridge */
130 #define OCTEON_NMI_ONNMI 0x1 /* Pending NMI from the ON/NMI push button */
131
132 #define OCTEON_NMIACK (OCTEON_FPGA_BASE + 0x104)
133 #define OCTEON_NMIACK_ONNMI 0x1 /* Write 1 to acknowledge ON/NMI */
134
135 #define OCTEON_SWITCH (OCTEON_FPGA_BASE + 0x200)
136 #define OCTEON_SWITCH_MASK 0xff /* settings of DIP switch S2 */
137
138 #define OCTEON_STATUS (OCTEON_FPGA_BASE + 0x208)
139 #define OCTEON_ST_MFWR 0x10 /* Monitor Flash is write protected (JP1) */
140 #define OCTEON_S54 0x08 /* switch S5-4 - set YAMON factory default mode */
141 #define OCTEON_S53 0x04 /* switch S5-3 */
142 #define OCTEON_BIGEND 0x02 /* switch S5-2 - big endian mode */
143
144 #define OCTEON_JMPRS (OCTEON_FPGA_BASE + 0x210)
145 #define OCTEON_JMPRS_PCICLK 0x1c /* PCI clock frequency */
146 #define OCTEON_JMPRS_EELOCK 0x02 /* I2C EEPROM is write protected */
147
148 #define OCTEON_LEDBAR (OCTEON_FPGA_BASE + 0x408)
149 #define OCTEON_ASCIIWORD (OCTEON_FPGA_BASE + 0x410)
150 #define OCTEON_ASCII_BASE (OCTEON_FPGA_BASE + 0x418)
151 #define OCTEON_ASCIIPOS0 0x00
152 #define OCTEON_ASCIIPOS1 0x08
153 #define OCTEON_ASCIIPOS2 0x10
154 #define OCTEON_ASCIIPOS3 0x18
155 #define OCTEON_ASCIIPOS4 0x20
156 #define OCTEON_ASCIIPOS5 0x28
157 #define OCTEON_ASCIIPOS6 0x30
158 #define OCTEON_ASCIIPOS7 0x38
159
160 #define OCTEON_SOFTRES (OCTEON_FPGA_BASE + 0x500)
161 #define OCTEON_GORESET 0x42 /* write this to OCTEON_SOFTRES for board reset */
162
163 /*
164 * BRKRES is the number of milliseconds before a "break" on tty will
165 * trigger a reset. A value of 0 will disable the reset.
166 */
167 #define OCTEON_BRKRES (OCTEON_FPGA_BASE + 0x508)
168 #define OCTEON_BRKRES_MASK 0xff
169
170 #define OCTEON_CBUSUART 0x8001180000000800ull
171 /* 16C550C UART, 8 bit registers on 8 byte boundaries */
172 /* RXTX 0x00 */
173 /* INTEN 0x08 */
174 /* IIFIFO 0x10 */
175 /* LCTRL 0x18 */
176 /* MCTRL 0x20 */
177 /* LSTAT 0x28 */
178 /* MSTAT 0x30 */
179 /* SCRATCH 0x38 */
180 #define OCTEON_CBUSUART_INTR 2
181
182 #define OCTEON_GPIO_BASE (OCTEON_FPGA_BASE + 0xa00)
183 #define OCTEON_GPOUT 0x0
184 #define OCTEON_GPINP 0x8
185
186 #define OCTEON_BOOTROM_BASE 0x1fc00000 /* Boot ROM: */
187 #define OCTEON_BOOTROM_SIZE 0x00400000 /* 4 MByte */
188
189 #define OCTEON_REVISION 0x1fc00010
190 #define OCTEON_REV_FPGRV 0xff0000 /* CBUS FPGA revision */
191 #define OCTEON_REV_CORID 0x00fc00 /* Core Board ID */
192 #define OCTEON_REV_CORRV 0x000300 /* Core Board Revision */
193 #define OCTEON_REV_PROID 0x0000f0 /* Product ID */
194 #define OCTEON_REV_PRORV 0x00000f /* Product Revision */
195
196 /* PCI definitions */
197
198 #define OCTEON_UART0ADR 0x8001180000000800ull
199 #define OCTEON_UART1ADR 0x8001180000000C00ull
200 #define OCTEON_UART_SIZE 0x400
201
202 #define OCTEON_MIO_BOOT_BIST_STAT 0x80011800000000F8ull
203
204
205
206 /**************************
207 * To Delete
208 */
209 #define OCTEON_SOUTHBRIDGE_INTR 0
210
211 #define OCTEON_PCI0_IO_BASE OCTEON_PCIMEM3_BASE
212 #define OCTEON_PCI0_ADDR( addr ) (OCTEON_PCI0_IO_BASE + (addr))
213
214 #define OCTEON_RTCADR 0x70 // OCTEON_PCI_IO_ADDR8(0x70)
215 #define OCTEON_RTCDAT 0x71 // OCTEON_PCI_IO_ADDR8(0x71)
216
217 #define OCTEON_SMSC_COM1_ADR 0x3f8
218 #define OCTEON_SMSC_COM2_ADR 0x2f8
219 #define OCTEON_UARTT0ADR OCTEON_PCI0_ADDR(OCTEON_SMSC_COM1_ADR)
220 #define OCTEON_UARTT1ADR OCTEON_SMSC_COM2_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_COM2_ADR)
221
222 #define OCTEON_SMSC_1284_ADR 0x378
223 #define OCTEON_1284ADR OCTEON_SMSC_1284_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_1284_ADR)
224
225 #define OCTEON_SMSC_FDD_ADR 0x3f0
226 #define OCTEON_FDDADR OCTEON_SMSC_FDD_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_FDD_ADR)
227
228 #define OCTEON_SMSC_KYBD_ADR 0x60 /* Fixed 0x60, 0x64 */
229 #define OCTEON_KYBDADR OCTEON_SMSC_KYBD_ADR // OCTEON_PCI0_ADDR(OCTEON_SMSC_KYBD_ADR)
230 #define OCTEON_SMSC_MOUSE_ADR OCTEON_SMSC_KYBD_ADR
231 #define OCTEON_MOUSEADR OCTEON_KYBDADR
232
233
234 #define OCTEON_DMA_PCI_PCIBASE 0x00000000UL
235 #define OCTEON_DMA_PCI_PHYSBASE 0x00000000UL
236 #define OCTEON_DMA_PCI_SIZE (256 * 1024 * 1024)
237
238 #define OCTEON_DMA_ISA_PCIBASE 0x00800000UL
239 #define OCTEON_DMA_ISA_PHYSBASE 0x00000000UL
240 #define OCTEON_DMA_ISA_SIZE (8 * 1024 * 1024)
241
242 #ifndef _LOCORE
243 void led_bar(uint8_t);
244 void led_display_word(uint32_t);
245 void led_display_str(const char *);
246 void led_display_char(int, uint8_t);
247 #endif
Cache object: 8742dc01fa772f8b882f3677f172ac90
|