1 /***********************license start************************************
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2005-2007 Cavium Networks (support@cavium.com). All rights
5 * reserved.
6 *
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met:
11 *
12 * * Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 *
15 * * Redistributions in binary form must reproduce the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer in the documentation and/or other materials provided
18 * with the distribution.
19 *
20 * * Neither the name of Cavium Networks nor the names of
21 * its contributors may be used to endorse or promote products
22 * derived from this software without specific prior written
23 * permission.
24 *
25 * TO THE MAXIMUM EXTENT PERMITTED BY LAW, THE SOFTWARE IS PROVIDED "AS IS"
26 * AND WITH ALL FAULTS AND CAVIUM NETWORKS MAKES NO PROMISES, REPRESENTATIONS
27 * OR WARRANTIES, EITHER EXPRESS, IMPLIED, STATUTORY, OR OTHERWISE, WITH
28 * RESPECT TO THE SOFTWARE, INCLUDING ITS CONDITION, ITS CONFORMITY TO ANY
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30 * DEFECTS, AND CAVIUM SPECIFICALLY DISCLAIMS ALL IMPLIED (IF ANY) WARRANTIES
31 * OF TITLE, MERCHANTABILITY, NONINFRINGEMENT, FITNESS FOR A PARTICULAR
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33 * POSSESSION OR CORRESPONDENCE TO DESCRIPTION. THE ENTIRE RISK ARISING OUT
34 * OF USE OR PERFORMANCE OF THE SOFTWARE LIES WITH YOU.
35 *
36 *
37 * For any questions regarding licensing please contact marketing@caviumnetworks.com
38 *
39 ***********************license end**************************************/
40 /* $FreeBSD: releng/12.0/sys/mips/cavium/octopcireg.h 326023 2017-11-20 19:43:44Z pfg $ */
41
42 #ifndef _CAVIUM_OCTOPCIREG_H_
43 #define _CAVIUM_OCTOPCIREG_H_
44
45 /**
46 * This is the bit decoding used for the Octeon PCI controller addresses for config space
47 */
48 typedef union
49 {
50 uint64_t u64;
51 uint64_t * u64_ptr;
52 uint32_t * u32_ptr;
53 uint16_t * u16_ptr;
54 uint8_t * u8_ptr;
55 struct
56 {
57 uint64_t upper : 2;
58 uint64_t reserved : 13;
59 uint64_t io : 1;
60 uint64_t did : 5;
61 uint64_t subdid : 3;
62 uint64_t reserved2 : 4;
63 uint64_t endian_swap : 2;
64 uint64_t reserved3 : 10;
65 uint64_t bus : 8;
66 uint64_t dev : 5;
67 uint64_t func : 3;
68 uint64_t reg : 8;
69 } s;
70 } octeon_pci_config_space_address_t;
71
72 typedef union
73 {
74 uint64_t u64;
75 uint32_t * u32_ptr;
76 uint16_t * u16_ptr;
77 uint8_t * u8_ptr;
78 struct
79 {
80 uint64_t upper : 2;
81 uint64_t reserved : 13;
82 uint64_t io : 1;
83 uint64_t did : 5;
84 uint64_t subdid : 3;
85 uint64_t reserved2 : 4;
86 uint64_t endian_swap : 2;
87 uint64_t res1 : 1;
88 uint64_t port : 1;
89 uint64_t addr : 32;
90 } s;
91 } octeon_pci_io_space_address_t;
92
93
94 #define CVMX_OCT_SUBDID_PCI_CFG 1
95 #define CVMX_OCT_SUBDID_PCI_IO 2
96 #define CVMX_OCT_SUBDID_PCI_MEM1 3
97 #define CVMX_OCT_SUBDID_PCI_MEM2 4
98 #define CVMX_OCT_SUBDID_PCI_MEM3 5
99 #define CVMX_OCT_SUBDID_PCI_MEM4 6
100
101 #define CVMX_OCT_PCI_IO_BASE 0x00004000
102 #define CVMX_OCT_PCI_IO_SIZE 0x08000000
103
104 #define CVMX_OCT_PCI_MEM1_BASE 0xf0000000
105 #define CVMX_OCT_PCI_MEM1_SIZE 0x0f000000
106
107 #endif /* !_CAVIUM_OCTOPCIREG_H_ */
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