The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/cavium/uart_bus_octeonusart.c

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    1 /*-
    2  * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * $Id$
   25  */
   26 /*
   27  * Skeleton of this file was based on respective code for ARM
   28  * code written by Olivier Houchard.
   29  */
   30 
   31 /*
   32  * XXXMIPS: This file is hacked from arm/... . XXXMIPS here means this file is
   33  * experimental and was written for MIPS32 port.
   34  */
   35 #include "opt_uart.h"
   36 
   37 #include <sys/cdefs.h>
   38 __FBSDID("$FreeBSD: stable/10/sys/mips/cavium/uart_bus_octeonusart.c 237687 2012-06-28 06:49:04Z imp $");
   39 
   40 #include <sys/param.h>
   41 #include <sys/systm.h>
   42 #include <sys/bus.h>
   43 #include <sys/conf.h>
   44 #include <sys/kernel.h>
   45 #include <sys/module.h>
   46 #include <machine/bus.h>
   47 #include <sys/rman.h>
   48 #include <machine/resource.h>
   49 
   50 #include <dev/pci/pcivar.h>
   51 
   52 #include <dev/uart/uart.h>
   53 #include <dev/uart/uart_bus.h>
   54 #include <dev/uart/uart_cpu.h>
   55 
   56 #include <mips/cavium/octeon_pcmap_regs.h>
   57 
   58 #include <contrib/octeon-sdk/cvmx.h>
   59 
   60 #include "uart_if.h"
   61 
   62 extern struct uart_class uart_oct16550_class;
   63 
   64 static int uart_octeon_probe(device_t dev);
   65 
   66 static device_method_t uart_octeon_methods[] = {
   67         /* Device interface */
   68         DEVMETHOD(device_probe, uart_octeon_probe),
   69         DEVMETHOD(device_attach, uart_bus_attach),
   70         DEVMETHOD(device_detach, uart_bus_detach),
   71         {0, 0}
   72 };
   73 
   74 static driver_t uart_octeon_driver = {
   75         uart_driver_name,
   76         uart_octeon_methods,
   77         sizeof(struct uart_softc),
   78 };
   79 
   80 extern 
   81 SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
   82 
   83 static int
   84 uart_octeon_probe(device_t dev)
   85 {
   86         struct uart_softc *sc;
   87         int unit;
   88 
   89         unit = device_get_unit(dev);
   90         sc = device_get_softc(dev);
   91         sc->sc_class = &uart_oct16550_class;
   92 
   93         /*
   94          * We inherit the settings from the systme console.  Note, the bst
   95          * bad bus_space_map are bogus here, but obio doesn't yet support
   96          * them, it seems.
   97          */
   98         sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
   99         bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
  100         sc->sc_bas.bst = uart_bus_space_mem;
  101         /*
  102          * XXX
  103          * RBR isn't really a great base address.
  104          */
  105         if (bus_space_map(sc->sc_bas.bst, CVMX_MIO_UARTX_RBR(0),
  106             uart_getrange(sc->sc_class), 0, &sc->sc_bas.bsh) != 0)
  107                 return (ENXIO);
  108         return (uart_bus_probe(dev, sc->sc_bas.regshft, 0, 0, unit));
  109 }
  110 
  111 DRIVER_MODULE(uart, obio, uart_octeon_driver, uart_devclass, 0, 0);

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