The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/mips/cavium/uart_dev_oct16550.c

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    1 /*-
    2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD AND BSD-2-Clause
    3  *
    4  * Copyright (c) 2003 Marcel Moolenaar
    5  * All rights reserved.
    6  *
    7  * Redistribution and use in source and binary forms, with or without
    8  * modification, are permitted provided that the following conditions
    9  * are met:
   10  *
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   19  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   20  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   22  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   26  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   27  */
   28 
   29 /*
   30  * uart_dev_oct16550.c
   31  *
   32  * Derived from uart_dev_ns8250.c
   33  *
   34  * Redistribution and use in source and binary forms, with or without
   35  * modification, are permitted provided that the following conditions
   36  * are met:
   37  *
   38  * 1. Redistributions of source code must retain the above copyright
   39  *    notice, this list of conditions and the following disclaimer.
   40  * 2. Redistributions in binary form must reproduce the above copyright
   41  *    notice, this list of conditions and the following disclaimer in the
   42  *    documentation and/or other materials provided with the distribution.
   43  *
   44  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   45  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   46  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   47  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   48  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   49  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   50  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   51  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   52  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   53  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   54  *
   55  *
   56  */
   57 
   58 
   59 #include <sys/cdefs.h>
   60 __FBSDID("$FreeBSD: stable/12/sys/mips/cavium/uart_dev_oct16550.c 326259 2017-11-27 15:07:26Z pfg $");
   61 
   62 #include <sys/param.h>
   63 #include <sys/systm.h>
   64 #include <sys/bus.h>
   65 #include <sys/conf.h>
   66 #include <machine/bus.h>
   67 #include <machine/pcpu.h>
   68 
   69 #include <dev/uart/uart.h>
   70 #include <dev/uart/uart_cpu.h>
   71 #include <dev/uart/uart_bus.h>
   72 
   73 #include <dev/ic/ns16550.h>
   74 
   75 #include <mips/cavium/octeon_pcmap_regs.h>
   76 
   77 #include <contrib/octeon-sdk/cvmx.h>
   78 
   79 #include "uart_if.h"
   80 
   81 /*
   82  * Clear pending interrupts. THRE is cleared by reading IIR. Data
   83  * that may have been received gets lost here.
   84  */
   85 static void
   86 oct16550_clrint (struct uart_bas *bas)
   87 {
   88         uint8_t iir;
   89 
   90         iir = uart_getreg(bas, REG_IIR);
   91         while ((iir & IIR_NOPEND) == 0) {
   92                 iir &= IIR_IMASK;
   93                 if (iir == IIR_RLS)
   94                         (void)uart_getreg(bas, REG_LSR);
   95                 else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
   96                         (void)uart_getreg(bas, REG_DATA);
   97                 else if (iir == IIR_MLSC)
   98                         (void)uart_getreg(bas, REG_MSR);
   99                 else if (iir == IIR_BUSY)
  100                         (void) uart_getreg(bas, REG_USR);
  101                 uart_barrier(bas);
  102                 iir = uart_getreg(bas, REG_IIR);
  103         }
  104 }
  105 
  106 static int delay_changed = 1;
  107 
  108 static int
  109 oct16550_delay (struct uart_bas *bas)
  110 {
  111         int divisor;
  112         u_char lcr;
  113         static int delay = 0;
  114 
  115         if (!delay_changed) return delay;
  116         delay_changed = 0;
  117         lcr = uart_getreg(bas, REG_LCR);
  118         uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
  119         uart_barrier(bas);
  120         divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
  121         uart_barrier(bas);
  122         uart_setreg(bas, REG_LCR, lcr);
  123         uart_barrier(bas);
  124         
  125         if(!bas->rclk)
  126                 return 10; /* return an approx delay value */
  127 
  128         /* 1/10th the time to transmit 1 character (estimate). */
  129         if (divisor <= 134)
  130                 return (16000000 * divisor / bas->rclk);
  131         return (16000 * divisor / (bas->rclk / 1000));
  132 
  133 }
  134 
  135 static int
  136 oct16550_divisor (int rclk, int baudrate)
  137 {
  138         int actual_baud, divisor;
  139         int error;
  140 
  141         if (baudrate == 0)
  142                 return (0);
  143 
  144         divisor = (rclk / (baudrate << 3) + 1) >> 1;
  145         if (divisor == 0 || divisor >= 65536)
  146                 return (0);
  147         actual_baud = rclk / (divisor << 4);
  148 
  149         /* 10 times error in percent: */
  150         error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
  151 
  152         /* 3.0% maximum error tolerance: */
  153         if (error < -30 || error > 30)
  154                 return (0);
  155 
  156         return (divisor);
  157 }
  158 
  159 static int
  160 oct16550_drain (struct uart_bas *bas, int what)
  161 {
  162         int delay, limit;
  163 
  164         delay = oct16550_delay(bas);
  165 
  166         if (what & UART_DRAIN_TRANSMITTER) {
  167                 /*
  168                  * Pick an arbitrary high limit to avoid getting stuck in
  169                  * an infinite loop when the hardware is broken. Make the
  170                  * limit high enough to handle large FIFOs.
  171                  */
  172                 limit = 10*10*10*1024;
  173                 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
  174                         DELAY(delay);
  175                 if (limit == 0) {
  176                         /* printf("oct16550: transmitter appears stuck... "); */
  177                         return (0);
  178                 }
  179         }
  180 
  181         if (what & UART_DRAIN_RECEIVER) {
  182                 /*
  183                  * Pick an arbitrary high limit to avoid getting stuck in
  184                  * an infinite loop when the hardware is broken. Make the
  185                  * limit high enough to handle large FIFOs and integrated
  186                  * UARTs. The HP rx2600 for example has 3 UARTs on the
  187                  * management board that tend to get a lot of data send
  188                  * to it when the UART is first activated.
  189                  */
  190                 limit=10*4096;
  191                 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
  192                         (void)uart_getreg(bas, REG_DATA);
  193                         uart_barrier(bas);
  194                         DELAY(delay << 2);
  195                 }
  196                 if (limit == 0) {
  197                         /* printf("oct16550: receiver appears broken... "); */
  198                         return (EIO);
  199                 }
  200         }
  201 
  202         return (0);
  203 }
  204 
  205 /*
  206  * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
  207  * drained. WARNING: this function clobbers the FIFO setting!
  208  */
  209 static void
  210 oct16550_flush (struct uart_bas *bas, int what)
  211 {
  212         uint8_t fcr;
  213 
  214         fcr = FCR_ENABLE;
  215         if (what & UART_FLUSH_TRANSMITTER)
  216                 fcr |= FCR_XMT_RST;
  217         if (what & UART_FLUSH_RECEIVER)
  218                 fcr |= FCR_RCV_RST;
  219         uart_setreg(bas, REG_FCR, fcr);
  220         uart_barrier(bas);
  221 }
  222 
  223 static int
  224 oct16550_param (struct uart_bas *bas, int baudrate, int databits, int stopbits,
  225     int parity)
  226 {
  227         int divisor;
  228         uint8_t lcr;
  229 
  230         lcr = 0;
  231         if (databits >= 8)
  232                 lcr |= LCR_8BITS;
  233         else if (databits == 7)
  234                 lcr |= LCR_7BITS;
  235         else if (databits == 6)
  236                 lcr |= LCR_6BITS;
  237         else
  238                 lcr |= LCR_5BITS;
  239         if (stopbits > 1)
  240                 lcr |= LCR_STOPB;
  241         lcr |= parity << 3;
  242 
  243         /* Set baudrate. */
  244         if (baudrate > 0) {
  245                 divisor = oct16550_divisor(bas->rclk, baudrate);
  246                 if (divisor == 0)
  247                         return (EINVAL);
  248                 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
  249                 uart_barrier(bas);
  250                 uart_setreg(bas, REG_DLL, divisor & 0xff);
  251                 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
  252                 uart_barrier(bas);
  253                 delay_changed = 1;
  254         }
  255 
  256         /* Set LCR and clear DLAB. */
  257         uart_setreg(bas, REG_LCR, lcr);
  258         uart_barrier(bas);
  259         return (0);
  260 }
  261 
  262 /*
  263  * Low-level UART interface.
  264  */
  265 static int oct16550_probe(struct uart_bas *bas);
  266 static void oct16550_init(struct uart_bas *bas, int, int, int, int);
  267 static void oct16550_term(struct uart_bas *bas);
  268 static void oct16550_putc(struct uart_bas *bas, int);
  269 static int oct16550_rxready(struct uart_bas *bas);
  270 static int oct16550_getc(struct uart_bas *bas, struct mtx *);
  271 
  272 struct uart_ops uart_oct16550_ops = {
  273         .probe = oct16550_probe,
  274         .init = oct16550_init,
  275         .term = oct16550_term,
  276         .putc = oct16550_putc,
  277         .rxready = oct16550_rxready,
  278         .getc = oct16550_getc,
  279 };
  280 
  281 static int
  282 oct16550_probe (struct uart_bas *bas)
  283 {
  284         u_char val;
  285 
  286         /* Check known 0 bits that don't depend on DLAB. */
  287         val = uart_getreg(bas, REG_IIR);
  288         if (val & 0x30)
  289                 return (ENXIO);
  290         val = uart_getreg(bas, REG_MCR);
  291         if (val & 0xc0)
  292                 return (ENXIO);
  293         val = uart_getreg(bas, REG_USR);
  294         if (val & 0xe0)
  295                 return (ENXIO);
  296         return (0);
  297 }
  298 
  299 static void
  300 oct16550_init (struct uart_bas *bas, int baudrate, int databits, int stopbits,
  301     int parity)
  302 {
  303         u_char  ier;
  304 
  305         oct16550_param(bas, baudrate, databits, stopbits, parity);
  306 
  307         /* Disable all interrupt sources. */
  308         ier = uart_getreg(bas, REG_IER) & 0x0;
  309         uart_setreg(bas, REG_IER, ier);
  310         uart_barrier(bas);
  311 
  312         /* Disable the FIFO (if present). */
  313 //      uart_setreg(bas, REG_FCR, 0);
  314         uart_barrier(bas);
  315 
  316         /* Set RTS & DTR. */
  317         uart_setreg(bas, REG_MCR, MCR_RTS | MCR_DTR);
  318         uart_barrier(bas);
  319 
  320         oct16550_clrint(bas);
  321 }
  322 
  323 static void
  324 oct16550_term (struct uart_bas *bas)
  325 {
  326 
  327         /* Clear RTS & DTR. */
  328         uart_setreg(bas, REG_MCR, 0);
  329         uart_barrier(bas);
  330 }
  331 
  332 static inline void oct16550_wait_txhr_empty (struct uart_bas *bas, int limit, int delay)
  333 {
  334     while (((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) &&
  335            ((uart_getreg(bas, REG_USR) & USR_TXFIFO_NOTFULL) == 0))
  336         DELAY(delay);
  337 }
  338 
  339 static void
  340 oct16550_putc (struct uart_bas *bas, int c)
  341 {
  342         int delay;
  343 
  344         /* 1/10th the time to transmit 1 character (estimate). */
  345         delay = oct16550_delay(bas);
  346         oct16550_wait_txhr_empty(bas, 100, delay);
  347         uart_setreg(bas, REG_DATA, c);
  348         uart_barrier(bas);
  349         oct16550_wait_txhr_empty(bas, 100, delay);
  350 }
  351 
  352 static int
  353 oct16550_rxready (struct uart_bas *bas)
  354 {
  355 
  356         return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
  357 }
  358 
  359 static int
  360 oct16550_getc (struct uart_bas *bas, struct mtx *hwmtx)
  361 {
  362         int c, delay;
  363 
  364         uart_lock(hwmtx);
  365 
  366         /* 1/10th the time to transmit 1 character (estimate). */
  367         delay = oct16550_delay(bas);
  368 
  369         while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
  370                 uart_unlock(hwmtx);
  371                 DELAY(delay);
  372                 uart_lock(hwmtx);
  373         }
  374 
  375         c = uart_getreg(bas, REG_DATA);
  376 
  377         uart_unlock(hwmtx);
  378 
  379         return (c);
  380 }
  381 
  382 /*
  383  * High-level UART interface.
  384  */
  385 struct oct16550_softc {
  386         struct uart_softc base;
  387         uint8_t         fcr;
  388         uint8_t         ier;
  389         uint8_t         mcr;
  390 };
  391 
  392 static int oct16550_bus_attach(struct uart_softc *);
  393 static int oct16550_bus_detach(struct uart_softc *);
  394 static int oct16550_bus_flush(struct uart_softc *, int);
  395 static int oct16550_bus_getsig(struct uart_softc *);
  396 static int oct16550_bus_ioctl(struct uart_softc *, int, intptr_t);
  397 static int oct16550_bus_ipend(struct uart_softc *);
  398 static int oct16550_bus_param(struct uart_softc *, int, int, int, int);
  399 static int oct16550_bus_probe(struct uart_softc *);
  400 static int oct16550_bus_receive(struct uart_softc *);
  401 static int oct16550_bus_setsig(struct uart_softc *, int);
  402 static int oct16550_bus_transmit(struct uart_softc *);
  403 static void oct16550_bus_grab(struct uart_softc *);
  404 static void oct16550_bus_ungrab(struct uart_softc *);
  405 
  406 static kobj_method_t oct16550_methods[] = {
  407         KOBJMETHOD(uart_attach,         oct16550_bus_attach),
  408         KOBJMETHOD(uart_detach,         oct16550_bus_detach),
  409         KOBJMETHOD(uart_flush,          oct16550_bus_flush),
  410         KOBJMETHOD(uart_getsig,         oct16550_bus_getsig),
  411         KOBJMETHOD(uart_ioctl,          oct16550_bus_ioctl),
  412         KOBJMETHOD(uart_ipend,          oct16550_bus_ipend),
  413         KOBJMETHOD(uart_param,          oct16550_bus_param),
  414         KOBJMETHOD(uart_probe,          oct16550_bus_probe),
  415         KOBJMETHOD(uart_receive,        oct16550_bus_receive),
  416         KOBJMETHOD(uart_setsig,         oct16550_bus_setsig),
  417         KOBJMETHOD(uart_transmit,       oct16550_bus_transmit),
  418         KOBJMETHOD(uart_grab,           oct16550_bus_grab),
  419         KOBJMETHOD(uart_ungrab,         oct16550_bus_ungrab),
  420         { 0, 0 }
  421 };
  422 
  423 struct uart_class uart_oct16550_class = {
  424         "oct16550 class",
  425         oct16550_methods,
  426         sizeof(struct oct16550_softc),
  427         .uc_ops = &uart_oct16550_ops,
  428         .uc_range = 8 << 3,
  429         .uc_rclk = 0,
  430         .uc_rshift = 0
  431 };
  432 
  433 #define SIGCHG(c, i, s, d)                              \
  434         if (c) {                                        \
  435                 i |= (i & s) ? s : s | d;               \
  436         } else {                                        \
  437                 i = (i & s) ? (i & ~s) | d : i;         \
  438         }
  439 
  440 static int
  441 oct16550_bus_attach (struct uart_softc *sc)
  442 {
  443         struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
  444         struct uart_bas *bas;
  445         int unit;
  446 
  447         unit = device_get_unit(sc->sc_dev);
  448         bas = &sc->sc_bas;
  449 
  450         oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
  451         oct16550->mcr = uart_getreg(bas, REG_MCR);
  452         oct16550->fcr = FCR_ENABLE | FCR_RX_HIGH;
  453         uart_setreg(bas, REG_FCR, oct16550->fcr);
  454         uart_barrier(bas);
  455         oct16550_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
  456 
  457         if (oct16550->mcr & MCR_DTR)
  458                 sc->sc_hwsig |= SER_DTR;
  459         if (oct16550->mcr & MCR_RTS)
  460                 sc->sc_hwsig |= SER_RTS;
  461         oct16550_bus_getsig(sc);
  462 
  463         oct16550_clrint(bas);
  464         oct16550->ier = uart_getreg(bas, REG_IER) & 0xf0;
  465         oct16550->ier |= IER_EMSC | IER_ERLS | IER_ERXRDY;
  466         uart_setreg(bas, REG_IER, oct16550->ier);
  467         uart_barrier(bas);
  468 
  469         return (0);
  470 }
  471 
  472 static int
  473 oct16550_bus_detach (struct uart_softc *sc)
  474 {
  475         struct uart_bas *bas;
  476         u_char ier;
  477 
  478         bas = &sc->sc_bas;
  479         ier = uart_getreg(bas, REG_IER) & 0xf0;
  480         uart_setreg(bas, REG_IER, ier);
  481         uart_barrier(bas);
  482         oct16550_clrint(bas);
  483         return (0);
  484 }
  485 
  486 static int
  487 oct16550_bus_flush (struct uart_softc *sc, int what)
  488 {
  489         struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
  490         struct uart_bas *bas;
  491         int error;
  492 
  493         bas = &sc->sc_bas;
  494         uart_lock(sc->sc_hwmtx);
  495         if (sc->sc_rxfifosz > 1) {
  496                 oct16550_flush(bas, what);
  497                 uart_setreg(bas, REG_FCR, oct16550->fcr);
  498                 uart_barrier(bas);
  499                 error = 0;
  500         } else
  501                 error = oct16550_drain(bas, what);
  502         uart_unlock(sc->sc_hwmtx);
  503         return (error);
  504 }
  505 
  506 static int
  507 oct16550_bus_getsig (struct uart_softc *sc)
  508 {
  509         uint32_t new, old, sig;
  510         uint8_t msr;
  511 
  512         do {
  513                 old = sc->sc_hwsig;
  514                 sig = old;
  515                 uart_lock(sc->sc_hwmtx);
  516                 msr = uart_getreg(&sc->sc_bas, REG_MSR);
  517                 uart_unlock(sc->sc_hwmtx);
  518                 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR);
  519                 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS);
  520                 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD);
  521                 SIGCHG(msr & MSR_RI,  sig, SER_RI,  SER_DRI);
  522                 new = sig & ~SER_MASK_DELTA;
  523         } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
  524         return (sig);
  525 }
  526 
  527 static int
  528 oct16550_bus_ioctl (struct uart_softc *sc, int request, intptr_t data)
  529 {
  530         struct uart_bas *bas;
  531         int baudrate, divisor, error;
  532         uint8_t efr, lcr;
  533 
  534         bas = &sc->sc_bas;
  535         error = 0;
  536         uart_lock(sc->sc_hwmtx);
  537         switch (request) {
  538         case UART_IOCTL_BREAK:
  539                 lcr = uart_getreg(bas, REG_LCR);
  540                 if (data)
  541                         lcr |= LCR_SBREAK;
  542                 else
  543                         lcr &= ~LCR_SBREAK;
  544                 uart_setreg(bas, REG_LCR, lcr);
  545                 uart_barrier(bas);
  546                 break;
  547         case UART_IOCTL_IFLOW:
  548                 lcr = uart_getreg(bas, REG_LCR);
  549                 uart_barrier(bas);
  550                 uart_setreg(bas, REG_LCR, 0xbf);
  551                 uart_barrier(bas);
  552                 efr = uart_getreg(bas, REG_EFR);
  553                 if (data)
  554                         efr |= EFR_RTS;
  555                 else
  556                         efr &= ~EFR_RTS;
  557                 uart_setreg(bas, REG_EFR, efr);
  558                 uart_barrier(bas);
  559                 uart_setreg(bas, REG_LCR, lcr);
  560                 uart_barrier(bas);
  561                 break;
  562         case UART_IOCTL_OFLOW:
  563                 lcr = uart_getreg(bas, REG_LCR);
  564                 uart_barrier(bas);
  565                 uart_setreg(bas, REG_LCR, 0xbf);
  566                 uart_barrier(bas);
  567                 efr = uart_getreg(bas, REG_EFR);
  568                 if (data)
  569                         efr |= EFR_CTS;
  570                 else
  571                         efr &= ~EFR_CTS;
  572                 uart_setreg(bas, REG_EFR, efr);
  573                 uart_barrier(bas);
  574                 uart_setreg(bas, REG_LCR, lcr);
  575                 uart_barrier(bas);
  576                 break;
  577         case UART_IOCTL_BAUD:
  578                 lcr = uart_getreg(bas, REG_LCR);
  579                 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
  580                 uart_barrier(bas);
  581                 divisor = uart_getreg(bas, REG_DLL) |
  582                     (uart_getreg(bas, REG_DLH) << 8);
  583                 uart_barrier(bas);
  584                 uart_setreg(bas, REG_LCR, lcr);
  585                 uart_barrier(bas);
  586                 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
  587                 delay_changed = 1;
  588                 if (baudrate > 0)
  589                         *(int*)data = baudrate;
  590                 else
  591                         error = ENXIO;
  592                 break;
  593         default:
  594                 error = EINVAL;
  595                 break;
  596         }
  597         uart_unlock(sc->sc_hwmtx);
  598         return (error);
  599 }
  600 
  601 
  602 static int
  603 oct16550_bus_ipend(struct uart_softc *sc)
  604 {
  605         struct uart_bas *bas;
  606         int ipend = 0;
  607         uint8_t iir, lsr;
  608 
  609         bas = &sc->sc_bas;
  610         uart_lock(sc->sc_hwmtx);
  611 
  612         iir = uart_getreg(bas, REG_IIR) & IIR_IMASK;
  613         if (iir != IIR_NOPEND) {
  614 
  615                 if (iir == IIR_RLS) {
  616                         lsr = uart_getreg(bas, REG_LSR);
  617                         if (lsr & LSR_OE)
  618                                 ipend |= SER_INT_OVERRUN;
  619                         if (lsr & LSR_BI)
  620                                 ipend |= SER_INT_BREAK;
  621                         if (lsr & LSR_RXRDY)
  622                                 ipend |= SER_INT_RXREADY;
  623 
  624                 } else if (iir == IIR_RXRDY) {
  625                         ipend |= SER_INT_RXREADY;
  626 
  627                 } else if (iir == IIR_RXTOUT) {
  628                         ipend |= SER_INT_RXREADY;
  629 
  630                 } else if (iir == IIR_TXRDY) {
  631                         ipend |= SER_INT_TXIDLE;
  632 
  633                 } else if (iir == IIR_MLSC) {
  634                         ipend |= SER_INT_SIGCHG;
  635 
  636                 } else if (iir == IIR_BUSY) {
  637                         (void) uart_getreg(bas, REG_USR);
  638                 }
  639         }
  640         uart_unlock(sc->sc_hwmtx);
  641 
  642         return (ipend);
  643 }
  644 
  645 static int
  646 oct16550_bus_param (struct uart_softc *sc, int baudrate, int databits,
  647     int stopbits, int parity)
  648 {
  649         struct uart_bas *bas;
  650         int error;
  651 
  652         bas = &sc->sc_bas;
  653         uart_lock(sc->sc_hwmtx);
  654         error = oct16550_param(bas, baudrate, databits, stopbits, parity);
  655         uart_unlock(sc->sc_hwmtx);
  656         return (error);
  657 }
  658 
  659 static int
  660 oct16550_bus_probe (struct uart_softc *sc)
  661 {
  662         struct uart_bas *bas;
  663         int error;
  664 
  665         bas = &sc->sc_bas;
  666         bas->rclk = uart_oct16550_class.uc_rclk = cvmx_clock_get_rate(CVMX_CLOCK_SCLK);
  667 
  668         error = oct16550_probe(bas);
  669         if (error) {
  670                 return (error);
  671         }
  672 
  673         uart_setreg(bas, REG_MCR, (MCR_DTR | MCR_RTS));
  674 
  675         /*
  676          * Enable FIFOs. And check that the UART has them. If not, we're
  677          * done. Since this is the first time we enable the FIFOs, we reset
  678          * them.
  679          */
  680         oct16550_drain(bas, UART_DRAIN_TRANSMITTER);
  681 #define ENABLE_OCTEON_FIFO 1
  682 #ifdef ENABLE_OCTEON_FIFO
  683         uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST);
  684 #endif
  685         uart_barrier(bas);
  686 
  687         oct16550_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
  688 
  689         if (device_get_unit(sc->sc_dev)) {
  690                 device_set_desc(sc->sc_dev, "Octeon-16550 channel 1");
  691         } else {
  692                 device_set_desc(sc->sc_dev, "Octeon-16550 channel 0");
  693         }
  694 #ifdef ENABLE_OCTEON_FIFO
  695         sc->sc_rxfifosz = 64;
  696         sc->sc_txfifosz = 64;
  697 #else
  698         sc->sc_rxfifosz = 1;
  699         sc->sc_txfifosz = 1;
  700 #endif
  701 
  702 
  703 #if 0
  704         /*
  705          * XXX there are some issues related to hardware flow control and
  706          * it's likely that uart(4) is the cause. This basicly needs more
  707          * investigation, but we avoid using for hardware flow control
  708          * until then.
  709          */
  710         /* 16650s or higher have automatic flow control. */
  711         if (sc->sc_rxfifosz > 16) {
  712                 sc->sc_hwiflow = 1;
  713                 sc->sc_hwoflow = 1;
  714         }
  715 #endif
  716 
  717         return (0);
  718 }
  719 
  720 static int
  721 oct16550_bus_receive (struct uart_softc *sc)
  722 {
  723         struct uart_bas *bas;
  724         int xc;
  725         uint8_t lsr;
  726 
  727         bas = &sc->sc_bas;
  728         uart_lock(sc->sc_hwmtx);
  729         lsr = uart_getreg(bas, REG_LSR);
  730 
  731         while (lsr & LSR_RXRDY) {
  732                 if (uart_rx_full(sc)) {
  733                         sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
  734                         break;
  735                 }
  736                 xc = uart_getreg(bas, REG_DATA);
  737                 if (lsr & LSR_FE)
  738                         xc |= UART_STAT_FRAMERR;
  739                 if (lsr & LSR_PE)
  740                         xc |= UART_STAT_PARERR;
  741                 uart_rx_put(sc, xc);
  742                 lsr = uart_getreg(bas, REG_LSR);
  743         }
  744         /* Discard everything left in the Rx FIFO. */
  745         /*
  746          * First do a dummy read/discard anyway, in case the UART was lying to us.
  747          * This problem was seen on board, when IIR said RBR, but LSR said no RXRDY
  748          * Results in a stuck ipend loop.
  749          */
  750         (void)uart_getreg(bas, REG_DATA);
  751         while (lsr & LSR_RXRDY) {
  752                 (void)uart_getreg(bas, REG_DATA);
  753                 uart_barrier(bas);
  754                 lsr = uart_getreg(bas, REG_LSR);
  755         }
  756         uart_unlock(sc->sc_hwmtx);
  757         return (0);
  758 }
  759 
  760 static int
  761 oct16550_bus_setsig (struct uart_softc *sc, int sig)
  762 {
  763         struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
  764         struct uart_bas *bas;
  765         uint32_t new, old;
  766 
  767         bas = &sc->sc_bas;
  768         do {
  769                 old = sc->sc_hwsig;
  770                 new = old;
  771                 if (sig & SER_DDTR) {
  772                         SIGCHG(sig & SER_DTR, new, SER_DTR,
  773                             SER_DDTR);
  774                 }
  775                 if (sig & SER_DRTS) {
  776                         SIGCHG(sig & SER_RTS, new, SER_RTS,
  777                             SER_DRTS);
  778                 }
  779         } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
  780         uart_lock(sc->sc_hwmtx);
  781         oct16550->mcr &= ~(MCR_DTR|MCR_RTS);
  782         if (new & SER_DTR)
  783                 oct16550->mcr |= MCR_DTR;
  784         if (new & SER_RTS)
  785                 oct16550->mcr |= MCR_RTS;
  786         uart_setreg(bas, REG_MCR, oct16550->mcr);
  787         uart_barrier(bas);
  788         uart_unlock(sc->sc_hwmtx);
  789         return (0);
  790 }
  791 
  792 static int
  793 oct16550_bus_transmit (struct uart_softc *sc)
  794 {
  795         struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
  796         struct uart_bas *bas;
  797         int i;
  798 
  799         bas = &sc->sc_bas;
  800         uart_lock(sc->sc_hwmtx);
  801 #ifdef NO_UART_INTERRUPTS
  802         for (i = 0; i < sc->sc_txdatasz; i++) {
  803             oct16550_putc(bas, sc->sc_txbuf[i]);
  804         }
  805 #else
  806 
  807         oct16550_wait_txhr_empty(bas, 100, oct16550_delay(bas));
  808         uart_setreg(bas, REG_IER, oct16550->ier | IER_ETXRDY);
  809         uart_barrier(bas);
  810 
  811         for (i = 0; i < sc->sc_txdatasz; i++) {
  812                 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
  813                 uart_barrier(bas);
  814         }
  815         sc->sc_txbusy = 1;
  816 #endif
  817         uart_unlock(sc->sc_hwmtx);
  818         return (0);
  819 }
  820 
  821 static void
  822 oct16550_bus_grab(struct uart_softc *sc)
  823 {
  824         struct uart_bas *bas = &sc->sc_bas;
  825 
  826         /*
  827          * turn off all interrupts to enter polling mode. Leave the
  828          * saved mask alone. We'll restore whatever it was in ungrab.
  829          * All pending interupt signals are reset when IER is set to 0.
  830          */
  831         uart_lock(sc->sc_hwmtx);
  832         uart_setreg(bas, REG_IER, 0);
  833         uart_barrier(bas);
  834         uart_unlock(sc->sc_hwmtx);
  835 }
  836 
  837 static void
  838 oct16550_bus_ungrab(struct uart_softc *sc)
  839 {
  840         struct oct16550_softc *oct16550 = (struct oct16550_softc*)sc;
  841         struct uart_bas *bas = &sc->sc_bas;
  842 
  843         /*
  844          * Restore previous interrupt mask
  845          */
  846         uart_lock(sc->sc_hwmtx);
  847         uart_setreg(bas, REG_IER, oct16550->ier);
  848         uart_barrier(bas);
  849         uart_unlock(sc->sc_hwmtx);
  850 }

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