The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/conf/AP135.hints

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    1 # This is a placeholder until the hardware support is complete.
    2 
    3 # I'm assuming this is an AP135-020. The AP136-010 in openwrt has
    4 # the ethernet ports wired up to the switch in the reverse way.
    5 
    6 # $FreeBSD: head/sys/mips/conf/AP135.hints 328756 2018-02-01 22:00:38Z adrian $
    7 
    8 # QCA955X_ETH_CFG_RGMII_EN (1 << 0)
    9 hint.qca955x_gmac.0.gmac_cfg=0x1
   10 
   11 # mdiobus0 on arge0
   12 hint.argemdio.0.at="nexus0"
   13 hint.argemdio.0.maddr=0x19000000
   14 hint.argemdio.0.msize=0x1000
   15 hint.argemdio.0.order=0
   16 
   17 # mdiobus1 on arge1 - required to bring up arge1?
   18 hint.argemdio.1.at="nexus0"
   19 hint.argemdio.1.maddr=0x1a000000
   20 hint.argemdio.1.msize=0x1000
   21 hint.argemdio.1.order=0
   22 
   23 # AR8327 - connected via mdiobus0 on arge0
   24 hint.arswitch.0.at="mdio0"
   25 hint.arswitch.0.is_7240=0       # definitely not the internal switch!
   26 hint.arswitch.0.is_9340=0       # not the internal switch!
   27 hint.arswitch.0.numphys=5       # all ports are PHYs
   28 hint.arswitch.0.phy4cpu=0
   29 hint.arswitch.0.is_rgmii=0      # not needed
   30 hint.arswitch.0.is_gmii=0       # not needed
   31 
   32 # This is where it gets a bit odd. port 0 and port 6 are CPU ports.
   33 # The current code only supports one CPU port.  So hm, what should
   34 # we do to hook PAD6 up to be RGMII but a PHY, not a MAC?
   35 
   36 # The other trick - how do we get arge1 (hooked up to GMAC0) to work?
   37 # That's currently supposed to be hooked up to CPU port 0.
   38 
   39 # Other AR8327 configuration parameters
   40 
   41 # AP136-020 parameters
   42 
   43 # GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII
   44 
   45 # AR8327_PAD_MAC_SGMII
   46 hint.arswitch.0.pad.0.mode=3
   47 #hint.arswitch.0.pad.0.rxclk_delay_sel=0
   48 hint.arswitch.0.pad.0.sgmii_delay_en=1
   49 
   50 # GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII
   51 
   52 # AR8327_PAD_MAC_RGMII
   53 # XXX I think this hooks it up to the internal MAC6
   54 hint.arswitch.0.pad.6.mode=6
   55 hint.arswitch.0.pad.6.txclk_delay_en=1
   56 hint.arswitch.0.pad.6.rxclk_delay_en=1
   57 # AR8327_CLK_DELAY_SEL1
   58 hint.arswitch.0.pad.6.txclk_delay_sel=1
   59 # AR8327_CLK_DELAY_SEL2
   60 hint.arswitch.0.pad.6.rxclk_delay_sel=2
   61 
   62 # XXX there's no LED management just yet!
   63 hint.arswitch.0.led.ctrl0=0x00000000
   64 hint.arswitch.0.led.ctrl1=0xc737c737
   65 hint.arswitch.0.led.ctrl2=0x00000000
   66 hint.arswitch.0.led.ctrl3=0x00c30c00
   67 hint.arswitch.0.led.open_drain=1
   68 
   69 # force_link=1 is required for the rest of the parameters
   70 # to be configured.
   71 hint.arswitch.0.port.0.force_link=1
   72 hint.arswitch.0.port.0.speed=1000
   73 hint.arswitch.0.port.0.duplex=1
   74 hint.arswitch.0.port.0.txpause=1
   75 hint.arswitch.0.port.0.rxpause=1
   76 
   77 # force_link=1 is required for the rest of the parameters
   78 # to be configured.
   79 hint.arswitch.0.port.6.force_link=1
   80 hint.arswitch.0.port.6.speed=1000
   81 hint.arswitch.0.port.6.duplex=1
   82 hint.arswitch.0.port.6.txpause=1
   83 hint.arswitch.0.port.6.rxpause=1
   84 
   85 # arge0 - hooked up to AR8327 GMAC6, RGMII
   86 # set at 1000/full to the switch.
   87 # so, lock both sides of this connect up to 1000/full;
   88 # if_arge thus wont change the PLL configuration
   89 # upon a link status change.
   90 hint.arge.0.phymask=0x0
   91 hint.arge.0.miimode=3           # RGMII
   92 hint.arge.0.media=1000
   93 hint.arge.0.fduplex=1
   94 hint.arge.0.pll_1000=0x56000000
   95 
   96 # MAC for arge0 is the first 6 bytes of the ART
   97 hint.arge.0.eeprommac=0x1fff0000
   98 
   99 # arge1 - lock up to 1000/full
  100 hint.arge.1.phymask=0x0
  101 hint.arge.1.media=1000
  102 hint.arge.1.fduplex=1
  103 hint.arge.1.miimode=5           # SGMII
  104 hint.arge.1.pll_1000=0x03000101
  105 
  106 # MAC for arge1 is the second 6 bytes of the ART
  107 hint.arge.1.eeprommac=0x1fff0006
  108 
  109 # Where the ART is - last 64k in the first 8MB of flash
  110 hint.ar71xx_caldata.0.map.0.ath_fixup_addr=0x1fff0000
  111 hint.ar71xx_caldata.0.map.0.ath_fixup_size=16384
  112 
  113 # And now tell the ath(4) driver where to look!
  114 hint.ath.0.eeprom_firmware="ar71xx_caldata.0.map.0.eeprom_firmware"
  115 
  116 # flash layout:
  117 #
  118 # bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),8256k(mib0),64k(ART)
  119 
  120 # The default flash layout isn't enough to fit a freebsd kernel
  121 # now, so the layout has been shuffled around.
  122 #
  123 # By default it's set to:
  124 # 256KB uboot, 64KB uboot-env, 6336KB rootfs, 1344KB kernel, 64KB cfg, 8256MB mib0, 64KB ART
  125 # With 'bootcmd=bootm 0x9f680000' in the environment.
  126 #
  127 # Instead, now let's make it:
  128 # 256KB uboot, 64KB uboot-env, 2048MB kernel, 6144MB rootfs, 7644KB mib0, 64KB cfg, 64KB ART
  129 # .. and then you change the boot env to be:
  130 # 'bootcmd=bootm 0x9f050000'
  131 
  132 # 256KiB u-boot
  133 hint.map.0.at="flash/spi0"
  134 hint.map.0.start=0x00000000
  135 hint.map.0.end=0x00040000       # 256k u-boot
  136 hint.map.0.name="u-boot"
  137 hint.map.0.readonly=1
  138 
  139 # 64KiB u-boot-env
  140 hint.map.1.at="flash/spi0"
  141 hint.map.1.start=0x00040000
  142 hint.map.1.end=0x00050000       # 64k u-boot-env
  143 hint.map.1.name="u-boot-env"
  144 hint.map.1.readonly=1
  145 
  146 # 2048KiB kernel
  147 hint.map.2.at="flash/spi0"
  148 hint.map.2.start=0x00050000
  149 hint.map.2.end=0x00250000       # 2048k rootfs
  150 hint.map.2.name="kernel"
  151 hint.map.2.readonly=1
  152 
  153 # 6144KiB rootfs
  154 hint.map.3.at="flash/spi0"
  155 hint.map.3.start=0x00250000
  156 hint.map.3.end=0x00850000
  157 hint.map.3.name="rootfs"
  158 hint.map.3.readonly=1
  159 
  160 # 7644KiB mib0
  161 hint.map.4.at="flash/spi0"
  162 hint.map.4.start=0x00850000
  163 hint.map.4.end=0x00fe0000
  164 hint.map.4.name="mib0"
  165 hint.map.4.readonly=0
  166 
  167 # 64KiB cfg
  168 hint.map.5.at="flash/spi0"
  169 hint.map.5.start=0x00fe0000
  170 hint.map.5.end=0x00ff0000
  171 hint.map.5.name="cfg"
  172 hint.map.5.readonly=0
  173 
  174 # 64KiB ART
  175 hint.map.6.at="flash/spi0"
  176 hint.map.6.start=0x00ff0000
  177 hint.map.6.end=0x01000000       # 64k ART
  178 hint.map.6.name="ART"
  179 hint.map.6.readonly=1

Cache object: a501218c87332dc4862f197ba0c086b2


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