The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/conf/DB120.hints

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    1 # $FreeBSD: releng/11.2/sys/mips/conf/DB120.hints 263223 2014-03-16 02:34:33Z adrian $
    2 
    3 # This is a placeholder until the hardware support is complete.
    4 
    5 # mdiobus0 on arge0
    6 hint.argemdio.0.at="nexus0"
    7 hint.argemdio.0.maddr=0x19000000
    8 hint.argemdio.0.msize=0x1000
    9 hint.argemdio.0.order=0
   10 
   11 # DB120 GMAC configuration
   12 # + AR934X_ETH_CFG_RGMII_GMAC0              (1 << 0)
   13 # + AR934X_ETH_CFG_SW_ONLY_MODE             (1 << 6)
   14 hint.ar934x_gmac.0.gmac_cfg=0x41
   15 
   16 # GMAC0 here - connected to an AR8327
   17 hint.arswitch.0.at="mdio0"
   18 hint.arswitch.0.is_7240=0
   19 hint.arswitch.0.is_9340=0       # not the internal switch!
   20 hint.arswitch.0.numphys=5
   21 hint.arswitch.0.phy4cpu=0
   22 hint.arswitch.0.is_rgmii=1
   23 hint.arswitch.0.is_gmii=0
   24 
   25 # Other AR8327 configuration parameters
   26 
   27 # AR8327_PAD_MAC_RGMII
   28 hint.arswitch.0.pad.0.mode=6
   29 hint.arswitch.0.pad.0.txclk_delay_en=1
   30 hint.arswitch.0.pad.0.rxclk_delay_en=1
   31 # AR8327_CLK_DELAY_SEL1
   32 hint.arswitch.0.pad.0.txclk_delay_sel=1
   33 # AR8327_CLK_DELAY_SEL2
   34 hint.arswitch.0.pad.0.rxclk_delay_sel=2
   35 
   36 # XXX there's no LED management just yet!
   37 hint.arswitch.0.led.ctrl0=0x00000000
   38 hint.arswitch.0.led.ctrl1=0xc737c737
   39 hint.arswitch.0.led.ctrl2=0x00000000
   40 hint.arswitch.0.led.ctrl3=0x00c30c00
   41 hint.arswitch.0.led.open_drain=1
   42 
   43 # force_link=1 is required for the rest of the parameters
   44 # to be configured.
   45 hint.arswitch.0.port.0.force_link=1
   46 hint.arswitch.0.port.0.speed=1000
   47 hint.arswitch.0.port.0.duplex=1
   48 hint.arswitch.0.port.0.txpause=1
   49 hint.arswitch.0.port.0.rxpause=1
   50 
   51 # XXX OpenWRT DB120 BSP doesn't have media/duplex set?
   52 hint.arge.0.phymask=0x0
   53 hint.arge.0.media=1000
   54 hint.arge.0.fduplex=1
   55 hint.arge.0.miimode=3           # RGMII
   56 hint.arge.0.pll_1000=0x06000000
   57 
   58 # MAC for arge0 is the first 6 bytes of the ART
   59 hint.arge.0.eeprommac=0x1f7f0000
   60 
   61 # mdiobus1 on arge1
   62 hint.argemdio.1.at="nexus0"
   63 hint.argemdio.1.maddr=0x1a000000
   64 hint.argemdio.1.msize=0x1000
   65 hint.argemdio.1.order=0
   66 
   67 # Embedded switch on the AR9344
   68 # mdio1 is actually created as the AR8327 internal bus; so
   69 # this pops up as mdio2.
   70 hint.arswitch.1.at="mdio2"
   71 hint.arswitch.1.is_7240=0
   72 hint.arswitch.1.is_9340=1
   73 hint.arswitch.1.numphys=5
   74 hint.arswitch.1.phy4cpu=0       # phy 4 is not a "CPU port" PHY here
   75 hint.arswitch.1.is_rgmii=0
   76 hint.arswitch.1.is_gmii=1       # arge1 <-> switch PHY is GMII
   77 
   78 # arge1 - lock up to 1000/full
   79 hint.arge.1.phymask=0x0         # Nothing attached here (XXX?)
   80 hint.arge.1.media=1000
   81 hint.arge.1.fduplex=1
   82 hint.arge.1.miimode=1           # GMII
   83 
   84 # MAC for arge1 is the second 6 bytes of the ART
   85 hint.arge.1.eeprommac=0x1f7f0006
   86 
   87 # ath0: Where the ART is - last 64k in the flash
   88 hint.ath.0.eepromaddr=0x1fff0000
   89 hint.ath.0.eepromsize=16384
   90 
   91 # ath1: it's different; it's a PCIe attached device, so
   92 # we instead need to teach the PCIe bridge code about it
   93 # (ie, the 'early pci fixup' stuff that programs the PCIe
   94 # host registers on the NIC) and then we teach ath where
   95 # to find it.
   96 
   97 # ath1 hint - pcie slot 0
   98 hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
   99 hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
  100 
  101 # ath0 - eeprom comes from here
  102 hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
  103 
  104 # flash layout:
  105 #
  106 # bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)
  107 
  108 # 256KiB u-boot
  109 hint.map.0.at="flash/spi0"
  110 hint.map.0.start=0x00000000
  111 hint.map.0.end=0x00040000       # 256k u-boot
  112 hint.map.0.name="u-boot"
  113 hint.map.0.readonly=1
  114 
  115 # 64KiB u-boot-env
  116 hint.map.1.at="flash/spi0"
  117 hint.map.1.start=0x00040000
  118 hint.map.1.end=0x00050000       # 64k u-boot-env
  119 hint.map.1.name="u-boot-env"
  120 hint.map.1.readonly=1
  121 
  122 # 6336KiB rootfs
  123 hint.map.2.at="flash/spi0"
  124 hint.map.2.start=0x00050000
  125 hint.map.2.end=0x00680000       # 6336k rootfs
  126 hint.map.2.name="rootfs"
  127 hint.map.2.readonly=1
  128 
  129 # 1344KiB uImage
  130 hint.map.3.at="flash/spi0"
  131 hint.map.3.start=0x00680000
  132 hint.map.3.end=0x007d0000       # 1408k uImage, 64k off the end..
  133 hint.map.3.name="uImage"
  134 hint.map.3.readonly=1
  135 
  136 # 64KiB cfg
  137 hint.map.4.at="flash/spi0"
  138 hint.map.4.start=0x007d0000
  139 hint.map.4.end=0x007e0000
  140 hint.map.4.name="cfg"
  141 hint.map.4.readonly=0
  142 
  143 # 64KiB mib0
  144 hint.map.5.at="flash/spi0"
  145 hint.map.5.start=0x007e0000
  146 hint.map.5.end=0x007f0000       # 64k mib0
  147 hint.map.5.name="mib0"
  148 hint.map.5.readonly=1
  149 
  150 # 64KiB ART
  151 hint.map.6.at="flash/spi0"
  152 hint.map.6.start=0x007f0000
  153 hint.map.6.end=0x00800000       # 64k ART
  154 hint.map.6.name="ART"
  155 hint.map.6.readonly=1

Cache object: cf38079a4682283c146e2ab445f30124


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