The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/mips/conf/TL-ARCHERC7V2.hints

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 # The Archer C7 v2 is based on the AP135-020 board, with
    2 # TP-Link specific bits (eg flash layout, MAC address, etc.)
    3 
    4 # $FreeBSD: head/sys/mips/conf/TL-ARCHERC7V2.hints 285079 2015-07-03 06:09:56Z adrian $
    5 
    6 # QCA955X_ETH_CFG_RGMII_EN (1 << 0)
    7 hint.qca955x_gmac.0.gmac_cfg=0x1
    8 
    9 # Use base mac address for wifi; +1 and +2 for arge0/arge1.
   10 hint.ar71xx.0.eeprom_mac_addr=0x1f01fc00
   11 hint.ar71xx.0.eeprom_mac_isascii=0
   12 
   13 hint.ar71xx_mac_map.0.devid=ath
   14 hint.ar71xx_mac_map.0.unitid=0
   15 hint.ar71xx_mac_map.0.offset=0
   16 hint.ar71xx_mac_map.0.is_local=0
   17 
   18 hint.ar71xx_mac_map.1.devid=arge
   19 hint.ar71xx_mac_map.1.unitid=0
   20 hint.ar71xx_mac_map.1.offset=1
   21 hint.ar71xx_mac_map.1.is_local=0
   22 
   23 hint.ar71xx_mac_map.2.devid=arge
   24 hint.ar71xx_mac_map.2.unitid=1
   25 hint.ar71xx_mac_map.2.offset=2
   26 hint.ar71xx_mac_map.2.is_local=0
   27 
   28 # mdiobus0 on arge0
   29 hint.argemdio.0.at="nexus0"
   30 hint.argemdio.0.maddr=0x19000000
   31 hint.argemdio.0.msize=0x1000
   32 hint.argemdio.0.order=0
   33 
   34 # mdiobus1 on arge1 - required to bring up arge1?
   35 hint.argemdio.1.at="nexus0"
   36 hint.argemdio.1.maddr=0x1a000000
   37 hint.argemdio.1.msize=0x1000
   38 hint.argemdio.1.order=0
   39 
   40 # AR8327 - connected via mdiobus0 on arge0
   41 hint.arswitch.0.at="mdio0"
   42 hint.arswitch.0.is_7240=0       # definitely not the internal switch!
   43 hint.arswitch.0.is_9340=0       # not the internal switch!
   44 hint.arswitch.0.numphys=5       # all ports are PHYs
   45 hint.arswitch.0.phy4cpu=0
   46 hint.arswitch.0.is_rgmii=0      # not needed
   47 hint.arswitch.0.is_gmii=0       # not needed
   48 
   49 # This is where it gets a bit odd. port 0 and port 6 are CPU ports.
   50 # The current code only supports one CPU port.  So hm, what should
   51 # we do to hook PAD6 up to be RGMII but a PHY, not a MAC?
   52 
   53 # The other trick - how do we get arge1 (hooked up to GMAC0) to work?
   54 # That's currently supposed to be hooked up to CPU port 0.
   55 
   56 # Other AR8327 configuration parameters
   57 
   58 # AP136-020 parameters
   59 
   60 # GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII
   61 
   62 # AR8327_PAD_MAC_SGMII
   63 hint.arswitch.0.pad.0.mode=3
   64 #hint.arswitch.0.pad.0.rxclk_delay_sel=0
   65 hint.arswitch.0.pad.0.sgmii_delay_en=1
   66 
   67 # GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII
   68 
   69 # AR8327_PAD_MAC_RGMII
   70 # XXX I think this hooks it up to the internal MAC6
   71 hint.arswitch.0.pad.6.mode=6
   72 hint.arswitch.0.pad.6.txclk_delay_en=1
   73 hint.arswitch.0.pad.6.rxclk_delay_en=1
   74 # AR8327_CLK_DELAY_SEL1
   75 hint.arswitch.0.pad.6.txclk_delay_sel=1
   76 # AR8327_CLK_DELAY_SEL2
   77 hint.arswitch.0.pad.6.rxclk_delay_sel=2
   78 
   79 # XXX there's no LED management just yet!
   80 hint.arswitch.0.led.ctrl0=0xc737c737
   81 hint.arswitch.0.led.ctrl1=0x00000000
   82 hint.arswitch.0.led.ctrl2=0x00000000
   83 hint.arswitch.0.led.ctrl3=0x00c30c00
   84 hint.arswitch.0.led.open_drain=0
   85 
   86 # force_link=1 is required for the rest of the parameters
   87 # to be configured.
   88 hint.arswitch.0.port.0.force_link=1
   89 hint.arswitch.0.port.0.speed=1000
   90 hint.arswitch.0.port.0.duplex=1
   91 hint.arswitch.0.port.0.txpause=1
   92 hint.arswitch.0.port.0.rxpause=1
   93 
   94 # force_link=1 is required for the rest of the parameters
   95 # to be configured.
   96 hint.arswitch.0.port.6.force_link=1
   97 hint.arswitch.0.port.6.speed=1000
   98 hint.arswitch.0.port.6.duplex=1
   99 hint.arswitch.0.port.6.txpause=1
  100 hint.arswitch.0.port.6.rxpause=1
  101 
  102 # arge0 - hooked up to AR8327 GMAC6, RGMII
  103 # set at 1000/full to the switch.
  104 # so, lock both sides of this connect up to 1000/full;
  105 # if_arge thus wont change the PLL configuration
  106 # upon a link status change.
  107 hint.arge.0.phymask=0x0
  108 hint.arge.0.miimode=3           # RGMII
  109 hint.arge.0.media=1000
  110 hint.arge.0.fduplex=1
  111 hint.arge.0.pll_1000=0x56000000
  112 
  113 # MAC for arge0 is the first 6 bytes of the ART
  114 hint.arge.0.eeprommac=0x1fff0000
  115 
  116 # arge1 - lock up to 1000/full
  117 hint.arge.1.phymask=0x0
  118 hint.arge.1.media=1000
  119 hint.arge.1.fduplex=1
  120 hint.arge.1.miimode=5           # SGMII
  121 hint.arge.1.pll_1000=0x03000101
  122 
  123 # MAC for arge1 is the second 6 bytes of the ART
  124 hint.arge.1.eeprommac=0x1fff0006
  125 
  126 # ath0: Where the ART is - last 64k in the flash
  127 hint.ath.0.eepromaddr=0x1fff0000
  128 hint.ath.0.eepromsize=16384
  129 
  130 # ath1: it's different; it's a PCIe attached device, so
  131 # we instead need to teach the PCIe bridge code about it
  132 # (ie, the 'early pci fixup' stuff that programs the PCIe
  133 # host registers on the NIC) and then we teach ath where
  134 # to find it.
  135 
  136 # ath1 hint - pcie slot 0
  137 # hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
  138 # hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
  139 
  140 # ath0 - eeprom comes from here
  141 # hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
  142 
  143 # Flash layout - the tplink layout differs to what's passed
  144 # in via the kernel environment.  What's passed in is based on
  145 # the AP135, but.. well, TP-Link.
  146 
  147 # 128 KiB u-boot
  148 hint.map.0.at="flash/spi0"
  149 hint.map.0.start=0x00000000
  150 hint.map.0.end=0x00020000       # 128k u-boot
  151 hint.map.0.name="u-boot"
  152 hint.map.0.readonly=1
  153 
  154 # Kernel
  155 hint.map.1.at="flash/spi0"
  156 hint.map.1.start=0x00020000
  157 hint.map.1.end="search:0x00020000:0x10000:.!/bin/sh"
  158 hint.map.1.name="kernel"
  159 hint.map.1.readonly=1
  160 
  161 # Root
  162 hint.map.2.at="flash/spi0"
  163 hint.map.2.start="search:0x00020000:0x10000:.!/bin/sh"
  164 hint.map.2.end=0x007d0000
  165 hint.map.2.name="rootfs"
  166 hint.map.2.readonly=1
  167 
  168 # 64KiB cfg
  169 hint.map.4.at="flash/spi0"
  170 hint.map.4.start=0x00fe0000
  171 hint.map.4.end=0x00ff0000
  172 hint.map.4.name="cfg"
  173 hint.map.4.readonly=0
  174 
  175 # 64KiB ART
  176 hint.map.6.at="flash/spi0"
  177 hint.map.6.start=0x00ff0000
  178 hint.map.6.end=0x01000000       # 64k ART
  179 hint.map.6.name="ART"
  180 hint.map.6.readonly=1
  181 
  182 # TODO: GPIO config
  183 # These are the GPIO LEDs and buttons which can be software controlled.
  184 hint.gpio.0.pinmask=0x00600000
  185 
  186 # Enable GPIO21, GPIO22 output and high - for USB power
  187 hint.gpio.0.pinon=0x00600000
  188 
  189 # TODO: GPIO pin config:
  190 # LED_WLAN2G       12
  191 # BTN_RFKILL       13
  192 # LED_SYSTEM       14
  193 # LED_QSS          15
  194 # BTN_RESET        16
  195 # LED_WLAN5G       17
  196 # LED_USB1         18
  197 # LED_USB2         19
  198 # USB2_POWER       21
  199 # USB1_POWER       22
  200 
  201 # TODO: PCIe isn't showing link; maybe uboot isn't initialising

Cache object: 8913743ffcf73bbfb6af16552761d284


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.