The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)

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FreeBSD/Linux Kernel Cross Reference
sys/mips/conf/TL-WDR4300.hints

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    1 # $FreeBSD: releng/11.0/sys/mips/conf/TL-WDR4300.hints 280800 2015-03-28 23:42:59Z adrian $
    2 
    3 # MAC/ART ? - they're 00:02:03:04:05:06 :(
    4 
    5 # ath0 chain0 EXTERNAL_LNA0: 18
    6 # ath0 chain1 EXTERNAL_LNA1: 19
    7 # These are configured as GPIO output, init low, then
    8 # set the GPIO 'type' AR934X_GPIO_OUT_EXT_LNA0/AR934X_GPIO_OUT_EXT_LNA1.
    9 
   10 # XXX There's no arge1 on this!
   11 
   12 # XXX RFKILL?
   13 
   14 # mdiobus0 on arge0
   15 hint.argemdio.0.at="nexus0"
   16 hint.argemdio.0.maddr=0x19000000
   17 hint.argemdio.0.msize=0x1000
   18 hint.argemdio.0.order=0
   19 
   20 # DB120 GMAC configuration
   21 # + AR934X_ETH_CFG_RGMII_GMAC0              (1 << 0)
   22 hint.ar934x_gmac.0.gmac_cfg=0x1
   23 
   24 # Board mac address is at 0x1f01fc00.
   25 # ath0: offset 0
   26 # ath1: offset -1
   27 # arge0: offset -2
   28 # arge1: not hooked up; doesn't matter
   29 hint.ar71xx.0.eeprom_mac_addr=0x1f01fc00
   30 hint.ar71xx.0.eeprom_mac_isascii=0
   31 
   32 hint.ar71xx_mac_map.0.devid=ath
   33 hint.ar71xx_mac_map.0.unitid=0
   34 hint.ar71xx_mac_map.0.offset=0
   35 hint.ar71xx_mac_map.0.is_local=0
   36 
   37 hint.ar71xx_mac_map.1.devid=ath
   38 hint.ar71xx_mac_map.1.unitid=1
   39 hint.ar71xx_mac_map.1.offset=-1
   40 hint.ar71xx_mac_map.1.is_local=0
   41 
   42 hint.ar71xx_mac_map.2.devid=arge
   43 hint.ar71xx_mac_map.2.unitid=0
   44 hint.ar71xx_mac_map.2.offset=-2
   45 hint.ar71xx_mac_map.2.is_local=0
   46 
   47 # GMAC0 here - connected to an AR8327
   48 hint.arswitch.0.at="mdio0"
   49 hint.arswitch.0.is_7240=0
   50 hint.arswitch.0.is_9340=0       # not the internal switch!
   51 hint.arswitch.0.numphys=5
   52 hint.arswitch.0.phy4cpu=0
   53 hint.arswitch.0.is_rgmii=0
   54 hint.arswitch.0.is_gmii=0
   55 
   56 # Other AR8327 configuration parameters
   57 
   58 # AR8327_PAD_MAC_RGMII
   59 hint.arswitch.0.pad.0.mode=6
   60 hint.arswitch.0.pad.0.txclk_delay_en=1
   61 hint.arswitch.0.pad.0.rxclk_delay_en=1
   62 # AR8327_CLK_DELAY_SEL1
   63 hint.arswitch.0.pad.0.txclk_delay_sel=1
   64 # AR8327_CLK_DELAY_SEL2
   65 hint.arswitch.0.pad.0.rxclk_delay_sel=2
   66 
   67 # XXX there's no LED management just yet!
   68 hint.arswitch.0.led.ctrl0=0xc737c737
   69 hint.arswitch.0.led.ctrl1=0x00000000
   70 hint.arswitch.0.led.ctrl2=0x00000000
   71 hint.arswitch.0.led.ctrl3=0x0030c300
   72 hint.arswitch.0.led.open_drain=0
   73 
   74 # force_link=1 is required for the rest of the parameters
   75 # to be configured.
   76 hint.arswitch.0.port.0.force_link=1
   77 hint.arswitch.0.port.0.speed=1000
   78 hint.arswitch.0.port.0.duplex=1
   79 hint.arswitch.0.port.0.txpause=1
   80 hint.arswitch.0.port.0.rxpause=1
   81 
   82 # XXX OpenWRT DB120 BSP doesn't have media/duplex set?
   83 hint.arge.0.phymask=0x0
   84 hint.arge.0.media=1000
   85 hint.arge.0.fduplex=1
   86 hint.arge.0.miimode=3           # RGMII
   87 hint.arge.0.pll_1000=0x06000000
   88 
   89 # mdiobus1 on arge1
   90 hint.argemdio.1.at="nexus0"
   91 hint.argemdio.1.maddr=0x1a000000
   92 hint.argemdio.1.msize=0x1000
   93 hint.argemdio.1.order=0
   94 
   95 # Embedded switch on the AR9344
   96 # mdio1 is actually created as the AR8327 internal bus; so
   97 # this pops up as mdio2.
   98 #
   99 # XXX TODO: there's no need for AR9344 internal switch; it isn't exposed
  100 hint.arswitch.1.at="mdio2"
  101 hint.arswitch.1.is_7240=0
  102 hint.arswitch.1.is_9340=1
  103 hint.arswitch.1.numphys=5
  104 hint.arswitch.1.phy4cpu=0       # phy 4 is not a "CPU port" PHY here
  105 hint.arswitch.1.is_rgmii=0
  106 hint.arswitch.1.is_gmii=1       # arge1 <-> switch PHY is GMII
  107 
  108 # arge1 - lock up to 1000/full
  109 hint.arge.1.phymask=0x0         # Nothing attached here (XXX?)
  110 hint.arge.1.media=1000
  111 hint.arge.1.fduplex=1
  112 hint.arge.1.miimode=1           # GMII
  113 
  114 # MAC for arge1 is the second 6 bytes of the ART
  115 # hint.arge.1.eeprommac=0x1f7f0006
  116 
  117 # ath0: Where the ART is - last 64k in the flash
  118 hint.ath.0.eepromaddr=0x1fff0000
  119 hint.ath.0.eepromsize=16384
  120 
  121 # ath1: it's different; it's a PCIe attached device, so
  122 # we instead need to teach the PCIe bridge code about it
  123 # (ie, the 'early pci fixup' stuff that programs the PCIe
  124 # host registers on the NIC) and then we teach ath where
  125 # to find it.
  126 
  127 # ath1 hint - pcie slot 0
  128 hint.pcib.0.bus.0.0.0.ath_fixup_addr=0x1fff4000
  129 hint.pcib.0.bus.0.0.0.ath_fixup_size=16384
  130 
  131 # ath0 - eeprom comes from here
  132 hint.ath.1.eeprom_firmware="pcib.0.bus.0.0.0.eeprom_firmware"
  133 
  134 # flash layout:
  135 #
  136 # bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init mtdparts=ath-nor0:256k(u-boot),64k(u-boot-env),6336k(rootfs),1408k(uImage),64k(mib0),64k(ART)
  137 
  138 # 128KiB uboot
  139 hint.map.0.at="flash/spi0"
  140 hint.map.0.start=0x00000000
  141 hint.map.0.end=0x00020000       # 128k u-boot
  142 hint.map.0.name="u-boot"
  143 hint.map.0.readonly=1
  144 
  145 # kernel
  146 hint.map.2.at="flash/spi0"
  147 hint.map.2.start=0x00020000
  148 hint.map.2.end="search:0x00020000:0x10000:.!/bin/sh"
  149 hint.map.2.name="kernel"
  150 hint.map.2.readonly=1
  151 
  152 # 1344KiB uImage
  153 hint.map.3.at="flash/spi0"
  154 hint.map.3.start="search:0x00020000:0x10000:.!/bin/sh"
  155 hint.map.3.end=0x007d0000
  156 hint.map.3.name="rootfs"
  157 hint.map.3.readonly=1
  158 
  159 # 64KiB cfg
  160 hint.map.4.at="flash/spi0"
  161 hint.map.4.start=0x007d0000
  162 hint.map.4.end=0x007e0000
  163 hint.map.4.name="cfg"
  164 hint.map.4.readonly=0
  165 
  166 # 64KiB mib0
  167 hint.map.5.at="flash/spi0"
  168 hint.map.5.start=0x007e0000
  169 hint.map.5.end=0x007f0000       # 64k mib0
  170 hint.map.5.name="mib0"
  171 hint.map.5.readonly=1
  172 
  173 # 64KiB ART
  174 hint.map.6.at="flash/spi0"
  175 hint.map.6.start=0x007f0000
  176 hint.map.6.end=0x00800000       # 64k ART
  177 hint.map.6.name="ART"
  178 hint.map.6.readonly=1
  179 
  180 # GPIO configuration
  181 # GPIO21 and GPIO22 - USB1 and USB2 power
  182 # ath0 chain0 EXTERNAL_LNA0: 18, output
  183 # ath0 chain1 EXTERNAL_LNA1: 19, output
  184 
  185 # These are the GPIO LEDs and buttons which can be software controlled.
  186 hint.gpio.0.pinmask=0x0063f800
  187 
  188 # Enable GPIO21, GPIO22 output and high - for USB power
  189 hint.gpio.0.pinon=0x00600000
  190 
  191 hint.gpio.0.func.18.gpiofunc=46
  192 hint.gpio.0.func.18.gpiomode=1  # output, default low
  193 
  194 hint.gpio.0.func.19.gpiofunc=47
  195 hint.gpio.0.func.19.gpiomode=1  # output, default low
  196 
  197 # LED QSS - 15
  198 # LED SYSTEM - 14
  199 # LED USB1 - 11
  200 # LED USB2 - 12
  201 # LED WLAN2G - 13
  202 
  203 # SWITCH WPS - 16
  204 # SWITCH RFKILL - 17
  205 
  206 hint.gpioled.0.at="gpiobus0"
  207 hint.gpioled.0.name="USB1"
  208 hint.gpioled.0.pins=0x0800
  209 
  210 hint.gpioled.1.at="gpiobus0"
  211 hint.gpioled.1.name="USB2"
  212 hint.gpioled.1.pins=0x1000
  213 
  214 hint.gpioled.2.at="gpiobus0"
  215 hint.gpioled.2.name="WLAN2G"
  216 hint.gpioled.2.pins=0x2000
  217 
  218 hint.gpioled.3.at="gpiobus0"
  219 hint.gpioled.3.name="SYSTEM"
  220 hint.gpioled.3.pins=0x4000
  221 
  222 hint.gpioled.4.at="gpiobus0"
  223 hint.gpioled.4.name="QSS"
  224 hint.gpioled.4.pins=0x8000
  225 
  226 # XXX TODO: WPS/RFKILL switch

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