The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/conf/TL-WR1043NDv2.hints

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    1 # The TP-Link 1043NDv2 is based on the AP135 with a couple of minor
    2 # differences - well, besides having no 11ac.
    3 
    4 # $FreeBSD: head/sys/mips/conf/TL-WR1043NDv2.hints 280948 2015-04-01 06:44:39Z adrian $
    5 
    6 # QCA955X_ETH_CFG_RGMII_EN (1 << 0)
    7 hint.qca955x_gmac.0.gmac_cfg=0x1
    8 
    9 # Use base mac address for wifi; +1 and +2 for arge0/arge1.
   10 hint.ar71xx.0.eeprom_mac_addr=0x1f01fc00
   11 hint.ar71xx.0.eeprom_mac_isascii=0
   12 
   13 hint.ar71xx_mac_map.0.devid=ath
   14 hint.ar71xx_mac_map.0.unitid=0
   15 hint.ar71xx_mac_map.0.offset=0
   16 hint.ar71xx_mac_map.0.is_local=0
   17 
   18 hint.ar71xx_mac_map.1.devid=arge
   19 hint.ar71xx_mac_map.1.unitid=0
   20 hint.ar71xx_mac_map.1.offset=1
   21 hint.ar71xx_mac_map.1.is_local=0
   22 
   23 hint.ar71xx_mac_map.2.devid=arge
   24 hint.ar71xx_mac_map.2.unitid=1
   25 hint.ar71xx_mac_map.2.offset=2
   26 hint.ar71xx_mac_map.2.is_local=0
   27 
   28 # mdiobus0 on arge0
   29 hint.argemdio.0.at="nexus0"
   30 hint.argemdio.0.maddr=0x19000000
   31 hint.argemdio.0.msize=0x1000
   32 hint.argemdio.0.order=0
   33 
   34 # mdiobus1 on arge1 - required to bring up arge1?
   35 hint.argemdio.1.at="nexus0"
   36 hint.argemdio.1.maddr=0x1a000000
   37 hint.argemdio.1.msize=0x1000
   38 hint.argemdio.1.order=0
   39 
   40 # AR8327 - connected via mdiobus0 on arge0
   41 hint.arswitch.0.at="mdio0"
   42 hint.arswitch.0.is_7240=0       # definitely not the internal switch!
   43 hint.arswitch.0.is_9340=0       # not the internal switch!
   44 hint.arswitch.0.numphys=5       # all ports are PHYs
   45 hint.arswitch.0.phy4cpu=0
   46 hint.arswitch.0.is_rgmii=0      # not needed
   47 hint.arswitch.0.is_gmii=0       # not needed
   48 
   49 # This is where it gets a bit odd. port 0 and port 6 are CPU ports.
   50 # The current code only supports one CPU port.  So hm, what should
   51 # we do to hook PAD6 up to be RGMII but a PHY, not a MAC?
   52 
   53 # The other trick - how do we get arge1 (hooked up to GMAC0) to work?
   54 # That's currently supposed to be hooked up to CPU port 0.
   55 
   56 # Other AR8327 configuration parameters
   57 
   58 # AP136-020 parameters
   59 
   60 # GMAC0 AR8327 -> GMAC1 (arge1) SoC, SGMII
   61 
   62 # AR8327_PAD_MAC_SGMII
   63 hint.arswitch.0.pad.0.mode=3
   64 #hint.arswitch.0.pad.0.rxclk_delay_sel=0
   65 hint.arswitch.0.pad.0.sgmii_delay_en=1
   66 
   67 # GMAC6 AR8327 -> GMAC0 (arge0) SoC, RGMII
   68 
   69 # AR8327_PAD_MAC_RGMII
   70 hint.arswitch.0.pad.6.mode=6
   71 hint.arswitch.0.pad.6.txclk_delay_en=1
   72 hint.arswitch.0.pad.6.rxclk_delay_en=1
   73 # AR8327_CLK_DELAY_SEL1
   74 hint.arswitch.0.pad.6.txclk_delay_sel=1
   75 # AR8327_CLK_DELAY_SEL2
   76 hint.arswitch.0.pad.6.rxclk_delay_sel=2
   77 
   78 hint.arswitch.0.led.ctrl0=0xcc35cc35
   79 hint.arswitch.0.led.ctrl1=0xca35ca35
   80 hint.arswitch.0.led.ctrl2=0xc935c935
   81 hint.arswitch.0.led.ctrl3=0x03ffff00
   82 int.arswitch.0.led.open_drain=1
   83 
   84 # force_link=1 is required for the rest of the parameters
   85 # to be configured.
   86 hint.arswitch.0.port.0.force_link=1
   87 hint.arswitch.0.port.0.speed=1000
   88 hint.arswitch.0.port.0.duplex=1
   89 hint.arswitch.0.port.0.txpause=1
   90 hint.arswitch.0.port.0.rxpause=1
   91 
   92 # force_link=1 is required for the rest of the parameters
   93 # to be configured.
   94 hint.arswitch.0.port.6.force_link=1
   95 hint.arswitch.0.port.6.speed=1000
   96 hint.arswitch.0.port.6.duplex=1
   97 hint.arswitch.0.port.6.txpause=1
   98 hint.arswitch.0.port.6.rxpause=1
   99 
  100 # arge0 - hooked up to AR8327 GMAC6, RGMII
  101 # set at 1000/full to the switch.
  102 # so, lock both sides of this connect up to 1000/full;
  103 # if_arge thus wont change the PLL configuration
  104 # upon a link status change.
  105 hint.arge.0.phymask=0x0
  106 hint.arge.0.miimode=3           # RGMII
  107 hint.arge.0.media=1000
  108 hint.arge.0.fduplex=1
  109 hint.arge.0.pll_1000=0x56000000
  110 
  111 # arge1 - lock up to 1000/full
  112 hint.arge.1.phymask=0x0
  113 hint.arge.1.media=1000
  114 hint.arge.1.fduplex=1
  115 hint.arge.1.miimode=5           # SGMII
  116 hint.arge.1.pll_1000=0x03000101
  117 
  118 # hint.arge.1.eeprommac=0x1f01fc06
  119 
  120 # ath0: Where the ART is - last 64k in the flash
  121 hint.ath.0.eepromaddr=0x1fff0000
  122 hint.ath.0.eepromsize=16384
  123 
  124 # 128 KiB u-boot
  125 hint.map.0.at="flash/spi0"
  126 hint.map.0.start=0x00000000
  127 hint.map.0.end=0x00020000       # 128k u-boot
  128 hint.map.0.name="u-boot"
  129 hint.map.0.readonly=1
  130 
  131 # The TP-Link firmware will put the kernel first (variable size);
  132 # then the rootfs will be placed hopefully at a 64KiB alignment
  133 # by whatever calls mktplinkfw.
  134 
  135 hint.map.1.at="flash/spi0"
  136 hint.map.1.start=0x00020000
  137 hint.map.1.end="search:0x00020000:0x10000:.!/bin/sh"
  138 hint.map.1.name="kernel"
  139 hint.map.1.readonly=1
  140 
  141 hint.map.2.at="flash/spi0"
  142 hint.map.2.start="search:0x00020000:0x10000:.!/bin/sh"
  143 hint.map.2.end=0x007d0000
  144 hint.map.2.name="rootfs"
  145 hint.map.2.readonly=1
  146 
  147 # 64KiB cfg
  148 hint.map.3.at="flash/spi0"
  149 hint.map.3.start=0x007d0000
  150 hint.map.3.end=0x007e0000
  151 hint.map.3.name="cfg"
  152 hint.map.3.readonly=0
  153 
  154 # 64KiB mib0
  155 hint.map.4.at="flash/spi0"
  156 hint.map.4.start=0x007e0000
  157 hint.map.4.end=0x007f0000
  158 hint.map.4.name="mib0"
  159 hint.map.4.readonly=1
  160 
  161 # 64KiB ART
  162 hint.map.5.at="flash/spi0"
  163 hint.map.5.start=0x007f0000
  164 hint.map.5.end=0x00800000       # 64k ART
  165 hint.map.5.name="ART"
  166 hint.map.5.readonly=1

Cache object: 85f723920e839065589b1b30539b1a16


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