The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/conf/TL-WR740Nv4.hints

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    1 #
    2 # This file adds to the values in AR933X_BASE.hints
    3 #
    4 # $FreeBSD: head/sys/mips/conf/TL-WR740Nv4.hints 289745 2015-10-22 08:08:06Z adrian $
    5 
    6 # mdiobus on arge1
    7 hint.argemdio.0.at="nexus0"
    8 hint.argemdio.0.maddr=0x1a000000
    9 hint.argemdio.0.msize=0x1000
   10 hint.argemdio.0.order=0
   11 
   12 # Embedded Atheros Switch
   13 hint.arswitch.0.at="mdio0"
   14 
   15 # XXX this should really say it's an AR933x switch, as there
   16 # are some vlan specific differences here!
   17 hint.arswitch.0.is_7240=1
   18 hint.arswitch.0.numphys=4
   19 hint.arswitch.0.phy4cpu=1       # phy 4 is a "CPU" separate PHY
   20 hint.arswitch.0.is_rgmii=0
   21 hint.arswitch.0.is_gmii=1       # arge1 <-> switch PHY is GMII
   22 
   23 # arge0 - MII, autoneg, phy(4)
   24 hint.arge.0.phymask=0x10        # PHY4
   25 hint.arge.0.mdio=mdioproxy1     # .. off of the switch mdiobus
   26 hint.arge.0.eeprommac=0x1fff0000
   27 
   28 # arge1 - GMII, 1000/full
   29 hint.arge.1.phymask=0x0         # No directly mapped PHYs
   30 hint.arge.1.media=1000
   31 hint.arge.1.fduplex=1
   32 hint.arge.1.eeprommac=0x1fff0006
   33 
   34 # Where the ART is - last 64k in the flash
   35 # 0x9fff1000 ?
   36 hint.ath.0.eepromaddr=0x1fff0000
   37 hint.ath.0.eepromsize=16384
   38 
   39 # The TL-WR740N v4 is a default AP121 - it comes with 4MB flash.
   40 #
   41 # The boot parameters:
   42 # bootargs=console=ttyS0,115200 root=31:02 rootfstype=squashfs init=/sbin/init
   43 #    mtdparts=ar7240-nor0:256k(u-boot),64k(u-boot-env),2752k(rootfs),
   44 #    896k(uImage),64k(NVRAM),64k(ART)
   45 # bootcmd=bootm 0x9f020000
   46 #
   47 # .. so uboot is 128K, there's no ubootenv, and the runtime image starts
   48 # at 0x9f020000.
   49 
   50 hint.map.0.at="flash/spi0"
   51 hint.map.0.start=0x00000000
   52 hint.map.0.end=0x000020000
   53 hint.map.0.name="uboot"
   54 hint.map.0.readonly=1
   55 
   56 hint.map.1.at="flash/spi0"
   57 hint.map.1.start=0x00020000
   58 hint.map.1.end=0x003e0000
   59 hint.map.1.name="kernel"
   60 hint.map.1.readonly=0
   61 
   62 hint.map.2.at="flash/spi0"
   63 hint.map.2.start=0x003e0000
   64 hint.map.2.end=0x003f0000
   65 hint.map.2.name="cfg"
   66 hint.map.2.readonly=0
   67 
   68 # This is radio calibration section.  It is (or should be!) unique
   69 # for each board, to take into account thermal and electrical differences
   70 # as well as the regulatory compliance data.
   71 #
   72 hint.map.3.at="flash/spi0"
   73 hint.map.3.start=0x003f0000
   74 hint.map.3.end=0x0x400000
   75 hint.map.3.name="art"
   76 hint.map.3.readonly=1
   77 
   78 # GPIO specific configuration block
   79 
   80 # Don't flip on anything that isn't already enabled.
   81 # This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're
   82 # not used here.
   83 hint.gpio.0.function_set=0x00000000
   84 hint.gpio.0.function_clear=0x00000000
   85 
   86 # These are the GPIO LEDs and buttons which can be software controlled.
   87 # hint.gpio.0.pinmask=0x00fc1803

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