The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/conf/TP-WN1043ND.hints

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    1 #
    2 # This file adds to the values in AR91XX_BASE.hints.
    3 #
    4 # $FreeBSD: releng/10.3/sys/mips/conf/TP-WN1043ND.hints 235345 2012-05-12 17:41:42Z adrian $
    5 
    6 # Hard-code the PHY for now, until there's switch phy support.
    7 # hint.arge.0.phymask=0x000c
    8 hint.arge.0.phymask=0x0000
    9 hint.arge.0.media=1000
   10 hint.arge.0.fduplex=1
   11 # Where is the MAC address stored in flash for this particular unit.
   12 hint.arge.0.eeprommac=0x1f01fc00
   13 
   14 # This isn't used, but configure it anyway.
   15 # This should eventually just not be configured, but the if then
   16 # needs to be properly disabled or spurious interrupts occur.
   17 hint.arge.1.phymask=0x0
   18 
   19 # Where the ART is
   20 hint.ath.0.eepromaddr=0x1fff1000
   21 
   22 #
   23 # Define a slightly custom flash layout.
   24 
   25 # The default flash layout:
   26 #
   27 # 128k: uboot
   28 # 1024k: kernel
   29 # 4096k: rootfs
   30 # 2816: unknown
   31 # 64k: board config?
   32 # 64k: ART
   33 #
   34 # from printenv:
   35 # bootargs=console=ttyS0,115200 root=31:02 rootfstype=jffs2 init=/sbin/init
   36 #    mtdparts=ar9100-nor0:128k(u-boot),1024k(kernel),4096k(rootfs),64k(art)
   37 
   38 # This isn't a lot of space!
   39 # So:
   40 # 128k: uboot
   41 # 2048k: kernel
   42 # 5888k: rootfs
   43 # 64k: config
   44 # 64k: ART
   45 
   46 hint.map.0.at="flash/spi0"
   47 hint.map.0.start=0x00000000
   48 hint.map.0.end=0x000200000
   49 hint.map.0.name="uboot"
   50 hint.map.0.readonly=1
   51 
   52 hint.map.1.at="flash/spi0"
   53 hint.map.1.start=0x00020000
   54 hint.map.1.end=0x00220000
   55 hint.map.1.name="kernel"
   56 hint.map.1.readonly=1
   57 
   58 hint.map.2.at="flash/spi0"
   59 hint.map.2.start=0x00220000
   60 hint.map.2.end=0x007e0000
   61 hint.map.2.name="rootfs"
   62 hint.map.2.readonly=1
   63 
   64 hint.map.3.at="flash/spi0"
   65 hint.map.3.start=0x007e0000
   66 hint.map.3.end=0x007f0000
   67 hint.map.3.name="cfg"
   68 hint.map.3.readonly=0
   69 
   70 # This is radio calibration section.  It is (or should be!) unique
   71 # for each board, to take into account thermal and electrical differences
   72 # as well as the regulatory compliance data.
   73 #
   74 hint.map.4.at="flash/spi0"
   75 hint.map.4.start=0x007f0000
   76 hint.map.4.end=0x00800000
   77 hint.map.4.name="art"
   78 hint.map.4.readonly=1
   79 
   80 # GPIO specific configuration block
   81 
   82 # Don't flip on anything that isn't already enabled.
   83 # This includes leaving the SPI CS1/CS2 pins as GPIO pins as they're
   84 # not used here.
   85 hint.gpio.0.function_set=0x00002000
   86 hint.gpio.0.function_clear=0x00000000
   87 
   88 # These are the GPIO LEDs and buttons which can be software controlled.
   89 hint.gpio.0.pinmask=0x001c02ae
   90 
   91 # pin 1 - USB (LED)
   92 # pin 2 - System (LED)
   93 # Pin 3 - Reset (input)
   94 # Pin 5 - QSS (LED)
   95 # Pin 7 - QSS Button (input)
   96 # Pin 8 - wired into the chip reset line
   97 # Pin 9 - WLAN
   98 # Pin 10 - UART TX (not GPIO)
   99 # Pin 13 - UART RX (not GPIO)
  100 # Pin 18 - RTL8366RB switch data line
  101 # Pin 19 - RTL8366RB switch clock line
  102 # Pin 20 - "GPIO20"
  103 
  104 # LEDs are configured separately and driven by the LED device
  105 #hint.gpioled.0.at="gpiobus0"
  106 #hint.gpioled.0.name="usb"
  107 #hint.gpioled.0.pins=0x0002
  108 
  109 hint.gpioled.1.at="gpiobus0"
  110 hint.gpioled.1.name="system"
  111 hint.gpioled.1.pins=0x0004
  112 
  113 hint.gpioled.2.at="gpiobus0"
  114 hint.gpioled.2.name="qss"
  115 hint.gpioled.2.pins=0x0020
  116 
  117 hint.gpioled.3.at="gpiobus0"
  118 hint.gpioled.3.name="wlan"
  119 hint.gpioled.3.pins=0x0200
  120 
  121 # GPIO I2C bus
  122 hint.gpioiic.0.at="gpiobus0"
  123 hint.gpioiic.0.pins=0xc0000
  124 hint.gpioiic.0.scl=1
  125 hint.gpioiic.0.sda=0
  126 
  127 # I2C bus
  128 # Don't be strict about I2C protocol - the relaxed semantics are required
  129 # by the realtek switch PHY.
  130 hint.iicbus.0.strict=0
  131 
  132 # Bit bang bus - override default delay
  133 #hint.iicbb.0.udelay=3

Cache object: c5bbc6465970a3dce3875703f6c72d7d


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