The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/idt/idtreg.h

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    1 /*-
    2  * Copyright (C) 2007 by Oleksandr Tymoshenko. All rights reserved.
    3  *
    4  * Redistribution and use in source and binary forms, with or without
    5  * modification, are permitted provided that the following conditions
    6  * are met:
    7  * 1. Redistributions of source code must retain the above copyright
    8  *    notice, this list of conditions and the following disclaimer.
    9  * 2. Redistributions in binary form must reproduce the above copyright
   10  *    notice, this list of conditions and the following disclaimer in the
   11  *    documentation and/or other materials provided with the distribution.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   16  * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
   17  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
   18  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
   19  * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
   21  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
   22  * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
   23  * THE POSSIBILITY OF SUCH DAMAGE.
   24  *
   25  * $FreeBSD: stable/8/sys/mips/idt/idtreg.h 215938 2010-11-27 12:26:40Z jchandra $
   26  *
   27  */
   28 #ifndef __IDTREG_H__
   29 #define __IDTREG_H__
   30 
   31 /* Interrupt controller */
   32 #define IDT_BASE_ICU    0x18038000
   33 #define         ICU_IPEND2      0x00
   34 #define         ICU_ITEST2      0x04
   35 #define         ICU_IMASK2      0x08
   36 #define         ICU_IPEND3      0x0C    
   37 #define         ICU_ITEST3      0x10
   38 #define         ICU_IMASK3      0x14
   39 #define         ICU_IPEND4      0x18    
   40 #define         ICU_ITEST4      0x1c
   41 #define         ICU_IMASK4      0x20
   42 #define         ICU_IPEND5      0x24    
   43 #define         ICU_ITEST5      0x28
   44 #define         ICU_IMASK5      0x2c
   45 #define         ICU_IPEND6      0x30    
   46 #define         ICU_ITEST6      0x34
   47 #define         ICU_IMASK6      0x38
   48 #define         ICU_NMIPS       0x3c
   49 
   50 #define IDT_BASE_GPIO   0x18050000
   51 #define         GPIO_FUNC       0x00
   52 #define         GPIO_CFG        0x04
   53 #define         GPIO_DATA       0x08
   54 #define         GPIO_ILEVEL     0x0C
   55 #define         GPIO_ISTAT      0x10
   56 #define         GPIO_NMIEN      0x14
   57 
   58 #define IDT_BASE_UART0  0x18058000
   59 
   60 /* PCI controller */
   61 #define IDT_BASE_PCI    0x18080000
   62 #define         IDT_PCI_CNTL            0x00
   63 #define                 IDT_PCI_CNTL_EN         0x001
   64 #define                 IDT_PCI_CNTL_TNR        0x002
   65 #define                 IDT_PCI_CNTL_SCE        0x004
   66 #define                 IDT_PCI_CNTL_IEN        0x008
   67 #define                 IDT_PCI_CNTL_AAA        0x010
   68 #define                 IDT_PCI_CNTL_EAP        0x020
   69 #define                 IDT_PCI_CNTL_IGM        0x200
   70 #define         IDT_PCI_STATUS          0x04
   71 #define                 IDT_PCI_STATUS_RIP      0x20000
   72 #define         IDT_PCI_STATUS_MASK     0x08
   73 #define         IDT_PCI_CFG_ADDR        0x0C
   74 #define         IDT_PCI_CFG_DATA        0x10
   75 /* LBA stuff */
   76 #define         IDT_PCI_LBA0            0x14
   77 #define         IDT_PCI_LBA0_CNTL       0x18
   78 #define                 IDT_PCI_LBA_MSI         0x01
   79 #define                 IDT_PCI_LBA_SIZE_1MB    (0x14 << 2)
   80 #define                 IDT_PCI_LBA_SIZE_2MB    (0x15 << 2)
   81 #define                 IDT_PCI_LBA_SIZE_4MB    (0x16 << 2)
   82 #define                 IDT_PCI_LBA_SIZE_8MB    (0x17 << 2)
   83 #define                 IDT_PCI_LBA_SIZE_16MB   (0x18 << 2)
   84 #define                 IDT_PCI_LBA_SIZE_32MB   (0x19 << 2)
   85 #define                 IDT_PCI_LBA_SIZE_64MB   (0x1A << 2)
   86 #define                 IDT_PCI_LBA_SIZE_128MB  (0x1B << 2)
   87 #define                 IDT_PCI_LBA_SIZE_256MB  (0x1C << 2)
   88 #define                 IDT_PCI_LBA_FE          0x80
   89 #define                 IDT_PCI_LBA_RT          0x100
   90 #define         IDT_PCI_LBA0_MAP        0x1C
   91 #define         IDT_PCI_LBA1            0x20
   92 #define         IDT_PCI_LBA1_CNTL       0x24
   93 #define         IDT_PCI_LBA1_MAP        0x28
   94 #define         IDT_PCI_LBA2            0x2C
   95 #define         IDT_PCI_LBA2_CNTL       0x30
   96 #define         IDT_PCI_LBA2_MAP        0x34
   97 #define         IDT_PCI_LBA3            0x38
   98 #define         IDT_PCI_LBA3_CNTL       0x3C
   99 #define         IDT_PCI_LBA3_MAP        0x40
  100 /* decoupled registers */
  101 #define         IDT_PCI_DAC             0x44
  102 #define         IDT_PCI_DAS             0x48
  103 #define         IDT_PCI_DASM            0x4C
  104 
  105 #define         IDT_PCI_TC              0x5C
  106 #define                 IDT_PCI_TC_RTIMER       0x10
  107 #define                 IDT_PCI_TC_DTIMER       0x08
  108 /* Messaging unit of PCI controller */
  109 #define         IDT_PCI_IIC             0x8024
  110 #define         IDT_PCI_IIM             0x8028
  111 #define         IDT_PCI_OIC             0x8030
  112 #define         IDT_PCI_OIM             0x8034
  113 
  114 /* PCI-related stuff */
  115 #define IDT_PCIMEM0_BASE        0x50000000
  116 #define IDT_PCIMEM0_SIZE        0x01000000
  117 
  118 #define IDT_PCIMEM1_BASE        0x60000000
  119 #define IDT_PCIMEM1_SIZE        0x10000000
  120 
  121 #define IDT_PCIMEM2_BASE        0x18C00000
  122 #define IDT_PCIMEM2_SIZE        0x00400000
  123 
  124 #define IDT_PCIMEM3_BASE        0x18800000
  125 #define IDT_PCIMEM3_SIZE        0x00100000
  126 
  127 /* Interrupts-related stuff */
  128 #define IRQ_BASE        8
  129 /* Convert <IPbit, irq_offset> pair to IRQ number */
  130 #define IP_IRQ(IPbit, offset) ((IPbit - 2) * 32 + (offset) + IRQ_BASE)
  131 /* The last one available IRQ */
  132 #define IRQ_END         IP_IRQ(6, 31)
  133 #define ICU_GROUP_REG_OFFSET    0x0C
  134 
  135 #define ICU_IP(irq)     (((irq) - IRQ_BASE) & 0x1f)
  136 #define ICU_IP_BIT(irq) (1 << ICU_IP(irq))
  137 #define ICU_GROUP(irq)  (((irq) - IRQ_BASE) >> 5)
  138 
  139 #define ICU_GROUP_MASK_REG(group)       \
  140     (ICU_IMASK2 + ((((group) - 2) * ICU_GROUP_REG_OFFSET)))
  141 #define ICU_GROUP_IPEND_REG(group)      \
  142     (ICU_IPEND2 + ((((group) - 2) * ICU_GROUP_REG_OFFSET)))
  143 
  144 #define ICU_IRQ_MASK_REG(irq)   \
  145     (ICU_IMASK2 + ((ICU_GROUP(irq) * ICU_GROUP_REG_OFFSET)))
  146 #define ICU_IRQ_IPEND_REG(irq)  \
  147     (ICU_IPEND2 + ((ICU_GROUP(irq) * ICU_GROUP_REG_OFFSET)))
  148 
  149 #define PCI_IRQ_BASE            IP_IRQ(6, 4)
  150 #define PCI_IRQ_END             IP_IRQ(6, 7)
  151 
  152 #endif /* __IDTREG_H__ */
  153 

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