FreeBSD/Linux Kernel Cross Reference
sys/mips/include/asm.h
1 /* $NetBSD: asm.h,v 1.29 2000/12/14 21:29:51 jeffs Exp $ */
2
3 /*
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 4. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * @(#)machAsmDefs.h 8.1 (Berkeley) 6/10/93
35 * JNPR: asm.h,v 1.10 2007/08/09 11:23:32 katta
36 * $FreeBSD: releng/10.4/sys/mips/include/asm.h 295019 2016-01-28 22:34:29Z brooks $
37 */
38
39 /*
40 * machAsmDefs.h --
41 *
42 * Macros used when writing assembler programs.
43 *
44 * Copyright (C) 1989 Digital Equipment Corporation.
45 * Permission to use, copy, modify, and distribute this software and
46 * its documentation for any purpose and without fee is hereby granted,
47 * provided that the above copyright notice appears in all copies.
48 * Digital Equipment Corporation makes no representations about the
49 * suitability of this software for any purpose. It is provided "as is"
50 * without express or implied warranty.
51 *
52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsmDefs.h,
53 * v 1.2 89/08/15 18:28:24 rab Exp SPRITE (DECWRL)
54 */
55
56 #ifndef _MACHINE_ASM_H_
57 #define _MACHINE_ASM_H_
58
59 #include <machine/regdef.h>
60 #include <machine/endian.h>
61 #include <machine/cdefs.h>
62
63 #undef __FBSDID
64 #if !defined(lint) && !defined(STRIP_FBSDID)
65 #define __FBSDID(s) .ident s
66 #else
67 #define __FBSDID(s) /* nothing */
68 #endif
69
70 /*
71 * Define -pg profile entry code.
72 * Must always be noreorder, must never use a macro instruction
73 * Final addiu to t9 must always equal the size of this _KERN_MCOUNT
74 */
75 #define _KERN_MCOUNT \
76 .set push; \
77 .set noreorder; \
78 .set noat; \
79 subu sp,sp,16; \
80 sw t9,12(sp); \
81 move AT,ra; \
82 lui t9,%hi(_mcount); \
83 addiu t9,t9,%lo(_mcount); \
84 jalr t9; \
85 nop; \
86 lw t9,4(sp); \
87 addiu sp,sp,8; \
88 addiu t9,t9,40; \
89 .set pop;
90
91 #ifdef GPROF
92 #define MCOUNT _KERN_MCOUNT
93 #else
94 #define MCOUNT
95 #endif
96
97 #define _C_LABEL(x) x
98
99 #ifdef USE_AENT
100 #define AENT(x) \
101 .aent x, 0
102 #else
103 #define AENT(x)
104 #endif
105
106 /*
107 * WARN_REFERENCES: create a warning if the specified symbol is referenced
108 */
109 #define WARN_REFERENCES(_sym,_msg) \
110 .section .gnu.warning. ## _sym ; .ascii _msg ; .text
111
112 #ifdef __ELF__
113 # define _C_LABEL(x) x
114 #else
115 # define _C_LABEL(x) _ ## x
116 #endif
117
118 /*
119 * WEAK_ALIAS: create a weak alias.
120 */
121 #define WEAK_ALIAS(alias,sym) \
122 .weak alias; \
123 alias = sym
124
125 /*
126 * STRONG_ALIAS: create a strong alias.
127 */
128 #define STRONG_ALIAS(alias,sym) \
129 .globl alias; \
130 alias = sym
131
132 #define GLOBAL(sym) \
133 .globl sym; sym:
134
135 #define ENTRY(sym) \
136 .text; .globl sym; .ent sym; sym:
137
138 #define ASM_ENTRY(sym) \
139 .text; .globl sym; .type sym,@function; sym:
140
141 /*
142 * LEAF
143 * A leaf routine does
144 * - call no other function,
145 * - never use any register that callee-saved (S0-S8), and
146 * - not use any local stack storage.
147 */
148 #define LEAF(x) \
149 .globl _C_LABEL(x); \
150 .ent _C_LABEL(x), 0; \
151 _C_LABEL(x): ; \
152 .frame sp, 0, ra; \
153 MCOUNT
154
155 /*
156 * LEAF_NOPROFILE
157 * No profilable leaf routine.
158 */
159 #define LEAF_NOPROFILE(x) \
160 .globl _C_LABEL(x); \
161 .ent _C_LABEL(x), 0; \
162 _C_LABEL(x): ; \
163 .frame sp, 0, ra
164
165 /*
166 * XLEAF
167 * declare alternate entry to leaf routine
168 */
169 #define XLEAF(x) \
170 .globl _C_LABEL(x); \
171 AENT (_C_LABEL(x)); \
172 _C_LABEL(x):
173
174 /*
175 * NESTED
176 * A function calls other functions and needs
177 * therefore stack space to save/restore registers.
178 */
179 #define NESTED(x, fsize, retpc) \
180 .globl _C_LABEL(x); \
181 .ent _C_LABEL(x), 0; \
182 _C_LABEL(x): ; \
183 .frame sp, fsize, retpc; \
184 MCOUNT
185
186 /*
187 * NESTED_NOPROFILE(x)
188 * No profilable nested routine.
189 */
190 #define NESTED_NOPROFILE(x, fsize, retpc) \
191 .globl _C_LABEL(x); \
192 .ent _C_LABEL(x), 0; \
193 _C_LABEL(x): ; \
194 .frame sp, fsize, retpc
195
196 /*
197 * XNESTED
198 * declare alternate entry point to nested routine.
199 */
200 #define XNESTED(x) \
201 .globl _C_LABEL(x); \
202 AENT (_C_LABEL(x)); \
203 _C_LABEL(x):
204
205 /*
206 * END
207 * Mark end of a procedure.
208 */
209 #define END(x) \
210 .end _C_LABEL(x)
211
212 /*
213 * IMPORT -- import external symbol
214 */
215 #define IMPORT(sym, size) \
216 .extern _C_LABEL(sym),size
217
218 /*
219 * EXPORT -- export definition of symbol
220 */
221 #define EXPORT(x) \
222 .globl _C_LABEL(x); \
223 _C_LABEL(x):
224
225 /*
226 * VECTOR
227 * exception vector entrypoint
228 * XXX: regmask should be used to generate .mask
229 */
230 #define VECTOR(x, regmask) \
231 .ent _C_LABEL(x),0; \
232 EXPORT(x); \
233
234 #define VECTOR_END(x) \
235 EXPORT(x ## End); \
236 END(x)
237
238 /*
239 * Macros to panic and printf from assembly language.
240 */
241 #define PANIC(msg) \
242 PTR_LA a0, 9f; \
243 jal _C_LABEL(panic); \
244 nop; \
245 MSG(msg)
246
247 #define PANIC_KSEG0(msg, reg) PANIC(msg)
248
249 #define PRINTF(msg) \
250 PTR_LA a0, 9f; \
251 jal _C_LABEL(printf); \
252 nop; \
253 MSG(msg)
254
255 #define MSG(msg) \
256 .rdata; \
257 9: .asciiz msg; \
258 .text
259
260 #define ASMSTR(str) \
261 .asciiz str; \
262 .align 3
263
264 /*
265 * Call ast if required
266 *
267 * XXX Do we really need to disable interrupts?
268 */
269 #define DO_AST \
270 44: \
271 mfc0 t0, MIPS_COP_0_STATUS ;\
272 and a0, t0, MIPS_SR_INT_IE ;\
273 xor t0, a0, t0 ;\
274 mtc0 t0, MIPS_COP_0_STATUS ;\
275 COP0_SYNC ;\
276 GET_CPU_PCPU(s1) ;\
277 PTR_L s3, PC_CURPCB(s1) ;\
278 PTR_L s1, PC_CURTHREAD(s1) ;\
279 lw s2, TD_FLAGS(s1) ;\
280 li s0, TDF_ASTPENDING | TDF_NEEDRESCHED;\
281 and s2, s0 ;\
282 mfc0 t0, MIPS_COP_0_STATUS ;\
283 or t0, a0, t0 ;\
284 mtc0 t0, MIPS_COP_0_STATUS ;\
285 COP0_SYNC ;\
286 beq s2, zero, 4f ;\
287 nop ;\
288 PTR_LA s0, _C_LABEL(ast) ;\
289 jalr s0 ;\
290 PTR_ADDU a0, s3, U_PCB_REGS ;\
291 j 44b ;\
292 nop ;\
293 4:
294
295
296 /*
297 * XXX retain dialects XXX
298 */
299 #define ALEAF(x) XLEAF(x)
300 #define NLEAF(x) LEAF_NOPROFILE(x)
301 #define NON_LEAF(x, fsize, retpc) NESTED(x, fsize, retpc)
302 #define NNON_LEAF(x, fsize, retpc) NESTED_NOPROFILE(x, fsize, retpc)
303
304 #if defined(__mips_o32)
305 #define SZREG 4
306 #else
307 #define SZREG 8
308 #endif
309
310 #if defined(__mips_o32) || defined(__mips_o64)
311 #define ALSK 7 /* stack alignment */
312 #define ALMASK -7 /* stack alignment */
313 #define SZFPREG 4
314 #define FP_L lwc1
315 #define FP_S swc1
316 #else
317 #define ALSK 15 /* stack alignment */
318 #define ALMASK -15 /* stack alignment */
319 #define SZFPREG 8
320 #define FP_L ldc1
321 #define FP_S sdc1
322 #endif
323
324 /*
325 * standard callframe {
326 * register_t cf_pad[N]; o32/64 (N=0), n32 (N=1) n64 (N=1)
327 * register_t cf_args[4]; arg0 - arg3 (only on o32 and o64)
328 * register_t cf_gp; global pointer (only on n32 and n64)
329 * register_t cf_sp; frame pointer
330 * register_t cf_ra; return address
331 * };
332 */
333 #if defined(__mips_o32) || defined(__mips_o64)
334 #define CALLFRAME_SIZ (SZREG * (4 + 2))
335 #define CALLFRAME_S0 0
336 #elif defined(__mips_n32) || defined(__mips_n64)
337 #define CALLFRAME_SIZ (SZREG * 4)
338 #define CALLFRAME_S0 (CALLFRAME_SIZ - 4 * SZREG)
339 #endif
340 #ifndef _KERNEL
341 #define CALLFRAME_GP (CALLFRAME_SIZ - 3 * SZREG)
342 #endif
343 #define CALLFRAME_SP (CALLFRAME_SIZ - 2 * SZREG)
344 #define CALLFRAME_RA (CALLFRAME_SIZ - 1 * SZREG)
345
346 /*
347 * Endian-independent assembly-code aliases for unaligned memory accesses.
348 */
349 #if _BYTE_ORDER == _LITTLE_ENDIAN
350 # define LWHI lwr
351 # define LWLO lwl
352 # define SWHI swr
353 # define SWLO swl
354 # if SZREG == 4
355 # define REG_LHI lwr
356 # define REG_LLO lwl
357 # define REG_SHI swr
358 # define REG_SLO swl
359 # else
360 # define REG_LHI ldr
361 # define REG_LLO ldl
362 # define REG_SHI sdr
363 # define REG_SLO sdl
364 # endif
365 #endif
366
367 #if _BYTE_ORDER == _BIG_ENDIAN
368 # define LWHI lwl
369 # define LWLO lwr
370 # define SWHI swl
371 # define SWLO swr
372 # if SZREG == 4
373 # define REG_LHI lwl
374 # define REG_LLO lwr
375 # define REG_SHI swl
376 # define REG_SLO swr
377 # else
378 # define REG_LHI ldl
379 # define REG_LLO ldr
380 # define REG_SHI sdl
381 # define REG_SLO sdr
382 # endif
383 #endif
384
385 /*
386 * While it would be nice to be compatible with the SGI
387 * REG_L and REG_S macros, because they do not take parameters, it
388 * is impossible to use them with the _MIPS_SIM_ABIX32 model.
389 *
390 * These macros hide the use of mips3 instructions from the
391 * assembler to prevent the assembler from generating 64-bit style
392 * ABI calls.
393 */
394 #if _MIPS_SZPTR == 32
395 #define PTR_ADD add
396 #define PTR_ADDI addi
397 #define PTR_ADDU addu
398 #define PTR_ADDIU addiu
399 #define PTR_SUB add
400 #define PTR_SUBI subi
401 #define PTR_SUBU subu
402 #define PTR_SUBIU subu
403 #define PTR_L lw
404 #define PTR_LA la
405 #define PTR_LI li
406 #define PTR_S sw
407 #define PTR_SLL sll
408 #define PTR_SLLV sllv
409 #define PTR_SRL srl
410 #define PTR_SRLV srlv
411 #define PTR_SRA sra
412 #define PTR_SRAV srav
413 #define PTR_LL ll
414 #define PTR_SC sc
415 #define PTR_WORD .word
416 #define PTR_SCALESHIFT 2
417 #else /* _MIPS_SZPTR == 64 */
418 #define PTR_ADD dadd
419 #define PTR_ADDI daddi
420 #define PTR_ADDU daddu
421 #define PTR_ADDIU daddiu
422 #define PTR_SUB dadd
423 #define PTR_SUBI dsubi
424 #define PTR_SUBU dsubu
425 #define PTR_SUBIU dsubu
426 #define PTR_L ld
427 #define PTR_LA dla
428 #define PTR_LI dli
429 #define PTR_S sd
430 #define PTR_SLL dsll
431 #define PTR_SLLV dsllv
432 #define PTR_SRL dsrl
433 #define PTR_SRLV dsrlv
434 #define PTR_SRA dsra
435 #define PTR_SRAV dsrav
436 #define PTR_LL lld
437 #define PTR_SC scd
438 #define PTR_WORD .dword
439 #define PTR_SCALESHIFT 3
440 #endif /* _MIPS_SZPTR == 64 */
441
442 #if _MIPS_SZINT == 32
443 #define INT_ADD add
444 #define INT_ADDI addi
445 #define INT_ADDU addu
446 #define INT_ADDIU addiu
447 #define INT_SUB add
448 #define INT_SUBI subi
449 #define INT_SUBU subu
450 #define INT_SUBIU subu
451 #define INT_L lw
452 #define INT_LA la
453 #define INT_S sw
454 #define INT_SLL sll
455 #define INT_SLLV sllv
456 #define INT_SRL srl
457 #define INT_SRLV srlv
458 #define INT_SRA sra
459 #define INT_SRAV srav
460 #define INT_LL ll
461 #define INT_SC sc
462 #define INT_WORD .word
463 #define INT_SCALESHIFT 2
464 #else
465 #define INT_ADD dadd
466 #define INT_ADDI daddi
467 #define INT_ADDU daddu
468 #define INT_ADDIU daddiu
469 #define INT_SUB dadd
470 #define INT_SUBI dsubi
471 #define INT_SUBU dsubu
472 #define INT_SUBIU dsubu
473 #define INT_L ld
474 #define INT_LA dla
475 #define INT_S sd
476 #define INT_SLL dsll
477 #define INT_SLLV dsllv
478 #define INT_SRL dsrl
479 #define INT_SRLV dsrlv
480 #define INT_SRA dsra
481 #define INT_SRAV dsrav
482 #define INT_LL lld
483 #define INT_SC scd
484 #define INT_WORD .dword
485 #define INT_SCALESHIFT 3
486 #endif
487
488 #if _MIPS_SZLONG == 32
489 #define LONG_ADD add
490 #define LONG_ADDI addi
491 #define LONG_ADDU addu
492 #define LONG_ADDIU addiu
493 #define LONG_SUB add
494 #define LONG_SUBI subi
495 #define LONG_SUBU subu
496 #define LONG_SUBIU subu
497 #define LONG_L lw
498 #define LONG_LA la
499 #define LONG_S sw
500 #define LONG_SLL sll
501 #define LONG_SLLV sllv
502 #define LONG_SRL srl
503 #define LONG_SRLV srlv
504 #define LONG_SRA sra
505 #define LONG_SRAV srav
506 #define LONG_LL ll
507 #define LONG_SC sc
508 #define LONG_WORD .word
509 #define LONG_SCALESHIFT 2
510 #else
511 #define LONG_ADD dadd
512 #define LONG_ADDI daddi
513 #define LONG_ADDU daddu
514 #define LONG_ADDIU daddiu
515 #define LONG_SUB dadd
516 #define LONG_SUBI dsubi
517 #define LONG_SUBU dsubu
518 #define LONG_SUBIU dsubu
519 #define LONG_L ld
520 #define LONG_LA dla
521 #define LONG_S sd
522 #define LONG_SLL dsll
523 #define LONG_SLLV dsllv
524 #define LONG_SRL dsrl
525 #define LONG_SRLV dsrlv
526 #define LONG_SRA dsra
527 #define LONG_SRAV dsrav
528 #define LONG_LL lld
529 #define LONG_SC scd
530 #define LONG_WORD .dword
531 #define LONG_SCALESHIFT 3
532 #endif
533
534 #if SZREG == 4
535 #define REG_L lw
536 #define REG_S sw
537 #define REG_LI li
538 #define REG_ADDU addu
539 #define REG_SLL sll
540 #define REG_SLLV sllv
541 #define REG_SRL srl
542 #define REG_SRLV srlv
543 #define REG_SRA sra
544 #define REG_SRAV srav
545 #define REG_LL ll
546 #define REG_SC sc
547 #define REG_SCALESHIFT 2
548 #else
549 #define REG_L ld
550 #define REG_S sd
551 #define REG_LI dli
552 #define REG_ADDU daddu
553 #define REG_SLL dsll
554 #define REG_SLLV dsllv
555 #define REG_SRL dsrl
556 #define REG_SRLV dsrlv
557 #define REG_SRA dsra
558 #define REG_SRAV dsrav
559 #define REG_LL lld
560 #define REG_SC scd
561 #define REG_SCALESHIFT 3
562 #endif
563
564 #if _MIPS_ISA == _MIPS_ISA_MIPS1 || _MIPS_ISA == _MIPS_ISA_MIPS2 || \
565 _MIPS_ISA == _MIPS_ISA_MIPS32
566 #define MFC0 mfc0
567 #define MTC0 mtc0
568 #endif
569 #if _MIPS_ISA == _MIPS_ISA_MIPS3 || _MIPS_ISA == _MIPS_ISA_MIPS4 || \
570 _MIPS_ISA == _MIPS_ISA_MIPS64
571 #define MFC0 dmfc0
572 #define MTC0 dmtc0
573 #endif
574
575 #if defined(__mips_o32) || defined(__mips_o64)
576
577 #ifdef __ABICALLS__
578 #define CPRESTORE(r) .cprestore r
579 #define CPLOAD(r) .cpload r
580 #else
581 #define CPRESTORE(r) /* not needed */
582 #define CPLOAD(r) /* not needed */
583 #endif
584
585 #define SETUP_GP \
586 .set push; \
587 .set noreorder; \
588 .cpload t9; \
589 .set pop
590 #define SETUP_GPX(r) \
591 .set push; \
592 .set noreorder; \
593 move r,ra; /* save old ra */ \
594 bal 7f; \
595 nop; \
596 7: .cpload ra; \
597 move ra,r; \
598 .set pop
599 #define SETUP_GPX_L(r,lbl) \
600 .set push; \
601 .set noreorder; \
602 move r,ra; /* save old ra */ \
603 bal lbl; \
604 nop; \
605 lbl: .cpload ra; \
606 move ra,r; \
607 .set pop
608 #define SAVE_GP(x) .cprestore x
609
610 #define SETUP_GP64(a,b) /* n32/n64 specific */
611 #define SETUP_GP64_R(a,b) /* n32/n64 specific */
612 #define SETUP_GPX64(a,b) /* n32/n64 specific */
613 #define SETUP_GPX64_L(a,b,c) /* n32/n64 specific */
614 #define RESTORE_GP64 /* n32/n64 specific */
615 #define USE_ALT_CP(a) /* n32/n64 specific */
616 #endif /* __mips_o32 || __mips_o64 */
617
618 #if defined(__mips_o32) || defined(__mips_o64)
619 #define REG_PROLOGUE .set push
620 #define REG_EPILOGUE .set pop
621 #endif
622 #if defined(__mips_n32) || defined(__mips_n64)
623 #define REG_PROLOGUE .set push ; .set mips3
624 #define REG_EPILOGUE .set pop
625 #endif
626
627 #if defined(__mips_n32) || defined(__mips_n64)
628 #define SETUP_GP /* o32 specific */
629 #define SETUP_GPX(r) /* o32 specific */
630 #define SETUP_GPX_L(r,lbl) /* o32 specific */
631 #define SAVE_GP(x) /* o32 specific */
632 #define SETUP_GP64(a,b) .cpsetup $25, a, b
633 #define SETUP_GPX64(a,b) \
634 .set push; \
635 move b,ra; \
636 .set noreorder; \
637 bal 7f; \
638 nop; \
639 7: .set pop; \
640 .cpsetup ra, a, 7b; \
641 move ra,b
642 #define SETUP_GPX64_L(a,b,c) \
643 .set push; \
644 move b,ra; \
645 .set noreorder; \
646 bal c; \
647 nop; \
648 c: .set pop; \
649 .cpsetup ra, a, c; \
650 move ra,b
651 #define RESTORE_GP64 .cpreturn
652 #define USE_ALT_CP(a) .cplocal a
653 #endif /* __mips_n32 || __mips_n64 */
654
655 #define GET_CPU_PCPU(reg) \
656 PTR_L reg, _C_LABEL(pcpup);
657
658 /*
659 * Description of the setjmp buffer
660 *
661 * word 0 magic number (dependant on creator)
662 * 1 RA
663 * 2 S0
664 * 3 S1
665 * 4 S2
666 * 5 S3
667 * 6 S4
668 * 7 S5
669 * 8 S6
670 * 9 S7
671 * 10 SP
672 * 11 S8
673 * 12 GP (dependent on ABI)
674 * 13 signal mask (dependant on magic)
675 * 14 (con't)
676 * 15 (con't)
677 * 16 (con't)
678 *
679 * The magic number number identifies the jmp_buf and
680 * how the buffer was created as well as providing
681 * a sanity check
682 *
683 */
684
685 #define _JB_MAGIC__SETJMP 0xBADFACED
686 #define _JB_MAGIC_SETJMP 0xFACEDBAD
687
688 /* Valid for all jmp_buf's */
689
690 #define _JB_MAGIC 0
691 #define _JB_REG_RA 1
692 #define _JB_REG_S0 2
693 #define _JB_REG_S1 3
694 #define _JB_REG_S2 4
695 #define _JB_REG_S3 5
696 #define _JB_REG_S4 6
697 #define _JB_REG_S5 7
698 #define _JB_REG_S6 8
699 #define _JB_REG_S7 9
700 #define _JB_REG_SP 10
701 #define _JB_REG_S8 11
702 #if defined(__mips_n32) || defined(__mips_n64)
703 #define _JB_REG_GP 12
704 #endif
705
706 /* Only valid with the _JB_MAGIC_SETJMP magic */
707
708 #define _JB_SIGMASK 13
709 #define __JB_SIGMASK_REMAINDER 14 /* sigmask_t is 128-bits */
710
711 #define _JB_FPREG_F20 15
712 #define _JB_FPREG_F21 16
713 #define _JB_FPREG_F22 17
714 #define _JB_FPREG_F23 18
715 #define _JB_FPREG_F24 19
716 #define _JB_FPREG_F25 20
717 #define _JB_FPREG_F26 21
718 #define _JB_FPREG_F27 22
719 #define _JB_FPREG_F28 23
720 #define _JB_FPREG_F29 24
721 #define _JB_FPREG_F30 25
722 #define _JB_FPREG_F31 26
723 #define _JB_FPREG_FCSR 27
724
725 /*
726 * Various macros for dealing with TLB hazards
727 * (a) why so many?
728 * (b) when to use?
729 * (c) why not used everywhere?
730 */
731 /*
732 * Assume that w alaways need nops to escape CP0 hazard
733 * TODO: Make hazard delays configurable. Stuck with 5 cycles on the moment
734 * For more info on CP0 hazards see Chapter 7 (p.99) of "MIPS32 Architecture
735 * For Programmers Volume III: The MIPS32 Privileged Resource Architecture"
736 */
737 #if defined(CPU_NLM)
738 #define HAZARD_DELAY sll $0,3
739 #define ITLBNOPFIX sll $0,3
740 #elif defined(CPU_RMI)
741 #define HAZARD_DELAY
742 #define ITLBNOPFIX
743 #elif defined(CPU_MIPS74KC)
744 #define HAZARD_DELAY sll $0,$0,3
745 #define ITLBNOPFIX sll $0,$0,3
746 #else
747 #define ITLBNOPFIX nop;nop;nop;nop;nop;nop;nop;nop;nop;sll $0,$0,3;
748 #define HAZARD_DELAY nop;nop;nop;nop;sll $0,$0,3;
749 #endif
750
751 #endif /* !_MACHINE_ASM_H_ */
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