1 /* $NetBSD: cache.h,v 1.6 2003/02/17 11:35:01 simonb Exp $ */
2
3 /*-
4 * SPDX-License-Identifier: BSD-4-Clause
5 *
6 * Copyright 2001 Wasabi Systems, Inc.
7 * All rights reserved.
8 *
9 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed for the NetBSD Project by
22 * Wasabi Systems, Inc.
23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
24 * or promote products derived from this software without specific prior
25 * written permission.
26 *
27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
38 *
39 * $FreeBSD$
40 */
41
42 #ifndef _MACHINE_CACHE_H_
43 #define _MACHINE_CACHE_H_
44
45 /*
46 * Cache operations.
47 *
48 * We define the following primitives:
49 *
50 * --- Instruction cache synchronization (mandatory):
51 *
52 * icache_sync_all Synchronize I-cache
53 *
54 * icache_sync_range Synchronize I-cache range
55 *
56 * icache_sync_range_index (index ops)
57 *
58 * --- Primary data cache (mandatory):
59 *
60 * pdcache_wbinv_all Write-back Invalidate primary D-cache
61 *
62 * pdcache_wbinv_range Write-back Invalidate primary D-cache range
63 *
64 * pdcache_wbinv_range_index (index ops)
65 *
66 * pdcache_inv_range Invalidate primary D-cache range
67 *
68 * pdcache_wb_range Write-back primary D-cache range
69 *
70 * --- Secondary data cache (optional):
71 *
72 * sdcache_wbinv_all Write-back Invalidate secondary D-cache
73 *
74 * sdcache_wbinv_range Write-back Invalidate secondary D-cache range
75 *
76 * sdcache_wbinv_range_index (index ops)
77 *
78 * sdcache_inv_range Invalidate secondary D-cache range
79 *
80 * sdcache_wb_range Write-back secondary D-cache range
81 *
82 * There are some rules that must be followed:
83 *
84 * I-cache Synch (all or range):
85 * The goal is to synchronize the instruction stream,
86 * so you may need to write-back dirty data cache
87 * blocks first. If a range is requested, and you
88 * can't synchronize just a range, you have to hit
89 * the whole thing.
90 *
91 * D-cache Write-back Invalidate range:
92 * If you can't WB-Inv a range, you must WB-Inv the
93 * entire D-cache.
94 *
95 * D-cache Invalidate:
96 * If you can't Inv the D-cache without doing a
97 * Write-back, YOU MUST PANIC. This is to catch
98 * errors in calling code. Callers must be aware
99 * of this scenario, and must handle it appropriately
100 * (consider the bus_dma(9) operations).
101 *
102 * D-cache Write-back:
103 * If you can't Write-back without doing an invalidate,
104 * that's fine. Then treat this as a WB-Inv. Skipping
105 * the invalidate is merely an optimization.
106 *
107 * All operations:
108 * Valid virtual addresses must be passed to the
109 * cache operation.
110 *
111 * Finally, these primitives are grouped together in reasonable
112 * ways. For all operations described here, first the primary
113 * cache is frobbed, then the secondary cache frobbed, if the
114 * operation for the secondary cache exists.
115 *
116 * mips_icache_sync_all Synchronize I-cache
117 *
118 * mips_icache_sync_range Synchronize I-cache range
119 *
120 * mips_icache_sync_range_index (index ops)
121 *
122 * mips_dcache_wbinv_all Write-back Invalidate D-cache
123 *
124 * mips_dcache_wbinv_range Write-back Invalidate D-cache range
125 *
126 * mips_dcache_wbinv_range_index (index ops)
127 *
128 * mips_dcache_inv_range Invalidate D-cache range
129 *
130 * mips_dcache_wb_range Write-back D-cache range
131 */
132
133 struct mips_cache_ops {
134 void (*mco_icache_sync_all)(void);
135 void (*mco_icache_sync_range)(vm_offset_t, vm_size_t);
136 void (*mco_icache_sync_range_index)(vm_offset_t, vm_size_t);
137
138 void (*mco_pdcache_wbinv_all)(void);
139 void (*mco_pdcache_wbinv_range)(vm_offset_t, vm_size_t);
140 void (*mco_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
141 void (*mco_pdcache_inv_range)(vm_offset_t, vm_size_t);
142 void (*mco_pdcache_wb_range)(vm_offset_t, vm_size_t);
143
144 /* These are called only by the (mipsNN) icache functions. */
145 void (*mco_intern_pdcache_wbinv_all)(void);
146 void (*mco_intern_pdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
147 void (*mco_intern_pdcache_wb_range)(vm_offset_t, vm_size_t);
148
149 void (*mco_sdcache_wbinv_all)(void);
150 void (*mco_sdcache_wbinv_range)(vm_offset_t, vm_size_t);
151 void (*mco_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
152 void (*mco_sdcache_inv_range)(vm_offset_t, vm_size_t);
153 void (*mco_sdcache_wb_range)(vm_offset_t, vm_size_t);
154
155 /* These are called only by the (mipsNN) icache functions. */
156 void (*mco_intern_sdcache_wbinv_all)(void);
157 void (*mco_intern_sdcache_wbinv_range_index)(vm_offset_t, vm_size_t);
158 void (*mco_intern_sdcache_wb_range)(vm_offset_t, vm_size_t);
159 };
160
161 extern struct mips_cache_ops mips_cache_ops;
162
163 /* PRIMARY CACHE VARIABLES */
164 extern int mips_picache_linesize;
165 extern int mips_pdcache_linesize;
166 extern int mips_sdcache_linesize;
167 extern int mips_dcache_max_linesize;
168
169 #define __mco_noargs(prefix, x) \
170 do { \
171 (*mips_cache_ops.mco_ ## prefix ## p ## x )(); \
172 if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \
173 (*mips_cache_ops.mco_ ## prefix ## s ## x )(); \
174 } while (/*CONSTCOND*/0)
175
176 #define __mco_2args(prefix, x, a, b) \
177 do { \
178 (*mips_cache_ops.mco_ ## prefix ## p ## x )((a), (b)); \
179 if (*mips_cache_ops.mco_ ## prefix ## s ## x ) \
180 (*mips_cache_ops.mco_ ## prefix ## s ## x )((a), (b)); \
181 } while (/*CONSTCOND*/0)
182
183 #define mips_icache_sync_all() \
184 (*mips_cache_ops.mco_icache_sync_all)()
185
186 #define mips_icache_sync_range(v, s) \
187 (*mips_cache_ops.mco_icache_sync_range)((v), (s))
188
189 #define mips_icache_sync_range_index(v, s) \
190 (*mips_cache_ops.mco_icache_sync_range_index)((v), (s))
191
192 #define mips_dcache_wbinv_all() \
193 __mco_noargs(, dcache_wbinv_all)
194
195 #define mips_dcache_wbinv_range(v, s) \
196 __mco_2args(, dcache_wbinv_range, (v), (s))
197
198 #define mips_dcache_wbinv_range_index(v, s) \
199 __mco_2args(, dcache_wbinv_range_index, (v), (s))
200
201 #define mips_dcache_inv_range(v, s) \
202 __mco_2args(, dcache_inv_range, (v), (s))
203
204 #define mips_dcache_wb_range(v, s) \
205 __mco_2args(, dcache_wb_range, (v), (s))
206
207 /*
208 * Private D-cache functions only called from (currently only the
209 * mipsNN) I-cache functions.
210 */
211 #define mips_intern_dcache_wbinv_all() \
212 __mco_noargs(intern_, dcache_wbinv_all)
213
214 #define mips_intern_dcache_wbinv_range_index(v, s) \
215 __mco_2args(intern_, dcache_wbinv_range_index, (v), (s))
216
217 #define mips_intern_dcache_wb_range(v, s) \
218 __mco_2args(intern_, dcache_wb_range, (v), (s))
219
220 /* forward declaration */
221 struct mips_cpuinfo;
222
223 void mips_config_cache(struct mips_cpuinfo *);
224
225 #include <machine/cache_mipsNN.h>
226 #endif /* _MACHINE_CACHE_H_ */
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