FreeBSD/Linux Kernel Cross Reference
sys/mips/include/cca.h
1 /* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */
2
3 /*
4 * SPDX-License-Identifier: BSD-3-Clause
5 *
6 * Copyright (c) 1992, 1993
7 * The Regents of the University of California. All rights reserved.
8 *
9 * This code is derived from software contributed to Berkeley by
10 * Ralph Campbell and Rick Macklem.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * @(#)machConst.h 8.1 (Berkeley) 6/10/93
37 *
38 * machConst.h --
39 *
40 * Machine dependent constants.
41 *
42 * Copyright (C) 1989 Digital Equipment Corporation.
43 * Permission to use, copy, modify, and distribute this software and
44 * its documentation for any purpose and without fee is hereby granted,
45 * provided that the above copyright notice appears in all copies.
46 * Digital Equipment Corporation makes no representations about the
47 * suitability of this software for any purpose. It is provided "as is"
48 * without express or implied warranty.
49 *
50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
51 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
52 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
53 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
54 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
55 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
56 *
57 * $FreeBSD$
58 */
59
60 #ifndef _MIPS_CCA_H_
61 #define _MIPS_CCA_H_
62
63 /*
64 * Cache Coherency Attributes:
65 * UC: Uncached.
66 * UA: Uncached accelerated.
67 * C: Cacheable, coherency unspecified.
68 * CNC: Cacheable non-coherent.
69 * CC: Cacheable coherent.
70 * CCS: Cacheable coherent, shared read.
71 * CCE: Cacheable coherent, exclusive read.
72 * CCEW: Cacheable coherent, exclusive write.
73 * CCUOW: Cacheable coherent, update on write.
74 *
75 * Note that some bits vary in meaning across implementations (and that the
76 * listing here is no doubt incomplete) and that the optimal cached mode varies
77 * between implementations. 0x02 is required to be UC and 0x03 is required to
78 * be a least C.
79 *
80 * We define the following logical bits:
81 * UNCACHED:
82 * The optimal uncached mode for the target CPU type. This must
83 * be suitable for use in accessing memory-mapped devices.
84 * CACHED: The optional cached mode for the target CPU type.
85 */
86
87 #define MIPS_CCA_UC 0x02 /* Uncached. */
88 #define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */
89
90 #if defined(CPU_R4000) || defined(CPU_R10000)
91 #define MIPS_CCA_CNC 0x03
92 #define MIPS_CCA_CCE 0x04
93 #define MIPS_CCA_CCEW 0x05
94
95 #ifdef CPU_R4000
96 #define MIPS_CCA_CCUOW 0x06
97 #endif
98
99 #ifdef CPU_R10000
100 #define MIPS_CCA_UA 0x07
101 #endif
102
103 #define MIPS_CCA_CACHED MIPS_CCA_CCEW
104 #endif /* defined(CPU_R4000) || defined(CPU_R10000) */
105
106 #if defined(CPU_SB1)
107 #define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */
108 #endif
109
110 #if defined(CPU_MIPS74K)
111 #define MIPS_CCA_UNCACHED 0x02
112 #define MIPS_CCA_CACHED 0x03
113 #endif
114
115 /*
116 * 1004K and 1074K cores, as well as interAptiv and proAptiv cores, support
117 * Cacheable Coherent CCAs 0x04 and 0x05, as well as Cacheable non-Coherent
118 * CCA 0x03 and Uncached Accelerated CCA 0x07
119 */
120 #if defined(CPU_MIPS1004K) || defined(CPU_MIPS1074K) || \
121 defined(CPU_INTERAPTIV) || defined(CPU_PROAPTIV)
122 #define MIPS_CCA_CNC 0x03
123 #define MIPS_CCA_CCE 0x04
124 #define MIPS_CCA_CCS 0x05
125 #define MIPS_CCA_UA 0x07
126
127 /* We use shared read CCA for CACHED CCA */
128 #define MIPS_CCA_CACHED MIPS_CCA_CCS
129 #endif
130
131 #if defined(CPU_XBURST)
132 #define MIPS_CCA_UA 0x01
133 #define MIPS_CCA_WC MIPS_CCA_UA
134 #endif
135
136 #ifndef MIPS_CCA_UNCACHED
137 #define MIPS_CCA_UNCACHED MIPS_CCA_UC
138 #endif
139
140 /*
141 * If we don't know which cached mode to use and there is a cache coherent
142 * mode, use it. If there is not a cache coherent mode, use the required
143 * cacheable mode.
144 */
145 #ifndef MIPS_CCA_CACHED
146 #ifdef MIPS_CCA_CC
147 #define MIPS_CCA_CACHED MIPS_CCA_CC
148 #else
149 #define MIPS_CCA_CACHED MIPS_CCA_C
150 #endif
151 #endif
152
153 #endif
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