1 /* $OpenBSD: pio.h,v 1.2 1998/09/15 10:50:12 pefo Exp $ */
2
3 /*-
4 * Copyright (c) 2002-2004 Juli Mallett. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27 /*
28 * Copyright (c) 1995-1999 Per Fogelstrom. All rights reserved.
29 *
30 * Redistribution and use in source and binary forms, with or without
31 * modification, are permitted provided that the following conditions
32 * are met:
33 * 1. Redistributions of source code must retain the above copyright
34 * notice, this list of conditions and the following disclaimer.
35 * 2. Redistributions in binary form must reproduce the above copyright
36 * notice, this list of conditions and the following disclaimer in the
37 * documentation and/or other materials provided with the distribution.
38 * 3. All advertising materials mentioning features or use of this software
39 * must display the following acknowledgement:
40 * This product includes software developed by Per Fogelstrom.
41 * 4. The name of the author may not be used to endorse or promote products
42 * derived from this software without specific prior written permission
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
45 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
46 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
47 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
48 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
49 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
50 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
51 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
52 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
53 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 * JNPR: cpufunc.h,v 1.5 2007/08/09 11:23:32 katta
56 * $FreeBSD: releng/8.2/sys/mips/include/cpufunc.h 215938 2010-11-27 12:26:40Z jchandra $
57 */
58
59 #ifndef _MACHINE_CPUFUNC_H_
60 #define _MACHINE_CPUFUNC_H_
61
62 #include <sys/types.h>
63 #include <machine/cpuregs.h>
64
65 /*
66 * These functions are required by user-land atomi ops
67 */
68
69 static __inline void
70 mips_barrier(void)
71 {
72 __asm __volatile (".set noreorder\n\t"
73 "nop\n\t"
74 "nop\n\t"
75 "nop\n\t"
76 "nop\n\t"
77 "nop\n\t"
78 "nop\n\t"
79 "nop\n\t"
80 "nop\n\t"
81 ".set reorder\n\t"
82 : : : "memory");
83 }
84
85 static __inline void
86 mips_cp0_sync(void)
87 {
88 __asm __volatile (__XSTRING(COP0_SYNC));
89 }
90
91 static __inline void
92 mips_wbflush(void)
93 {
94 __asm __volatile ("sync" : : : "memory");
95 mips_barrier();
96 }
97
98 static __inline void
99 mips_read_membar(void)
100 {
101 /* Nil */
102 }
103
104 static __inline void
105 mips_write_membar(void)
106 {
107 mips_wbflush();
108 }
109
110 #ifdef _KERNEL
111 #if defined(__mips_n32) || defined(__mips_n64)
112 #define MIPS_RDRW64_COP0(n,r) \
113 static __inline uint64_t \
114 mips_rd_ ## n (void) \
115 { \
116 int v0; \
117 __asm __volatile ("dmfc0 %[v0], $"__XSTRING(r)";" \
118 : [v0] "=&r"(v0)); \
119 mips_barrier(); \
120 return (v0); \
121 } \
122 static __inline void \
123 mips_wr_ ## n (uint64_t a0) \
124 { \
125 __asm __volatile ("dmtc0 %[a0], $"__XSTRING(r)";" \
126 __XSTRING(COP0_SYNC)";" \
127 "nop;" \
128 "nop;" \
129 : \
130 : [a0] "r"(a0)); \
131 mips_barrier(); \
132 } struct __hack
133
134 #if defined(__mips_n64)
135 MIPS_RDRW64_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
136 MIPS_RDRW64_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
137 MIPS_RDRW64_COP0(entryhi, MIPS_COP_0_TLB_HI);
138 MIPS_RDRW64_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
139 #endif
140 MIPS_RDRW64_COP0(xcontext, MIPS_COP_0_TLB_XCONTEXT);
141
142 #undef MIPS_RDRW64_COP0
143 #endif
144
145 #define MIPS_RDRW32_COP0(n,r) \
146 static __inline uint32_t \
147 mips_rd_ ## n (void) \
148 { \
149 int v0; \
150 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)";" \
151 : [v0] "=&r"(v0)); \
152 mips_barrier(); \
153 return (v0); \
154 } \
155 static __inline void \
156 mips_wr_ ## n (uint32_t a0) \
157 { \
158 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)";" \
159 __XSTRING(COP0_SYNC)";" \
160 "nop;" \
161 "nop;" \
162 : \
163 : [a0] "r"(a0)); \
164 mips_barrier(); \
165 } struct __hack
166
167 #define MIPS_RDRW32_COP0_SEL(n,r,s) \
168 static __inline uint32_t \
169 mips_rd_ ## n(void) \
170 { \
171 int v0; \
172 __asm __volatile ("mfc0 %[v0], $"__XSTRING(r)", "__XSTRING(s)";" \
173 : [v0] "=&r"(v0)); \
174 mips_barrier(); \
175 return (v0); \
176 } \
177 static __inline void \
178 mips_wr_ ## n(uint32_t a0) \
179 { \
180 __asm __volatile ("mtc0 %[a0], $"__XSTRING(r)", "__XSTRING(s)";" \
181 __XSTRING(COP0_SYNC)";" \
182 "nop;" \
183 "nop;" \
184 : \
185 : [a0] "r"(a0)); \
186 mips_barrier(); \
187 } struct __hack
188
189 #ifdef CPU_CNMIPS
190 static __inline void mips_sync_icache (void)
191 {
192 __asm __volatile (
193 ".set push\n"
194 ".set mips64\n"
195 ".word 0x041f0000\n" /* xxx ICACHE */
196 "nop\n"
197 ".set pop\n"
198 : : );
199 }
200 #endif
201
202 MIPS_RDRW32_COP0(compare, MIPS_COP_0_COMPARE);
203 MIPS_RDRW32_COP0(config, MIPS_COP_0_CONFIG);
204 MIPS_RDRW32_COP0_SEL(config1, MIPS_COP_0_CONFIG, 1);
205 MIPS_RDRW32_COP0_SEL(config2, MIPS_COP_0_CONFIG, 2);
206 MIPS_RDRW32_COP0_SEL(config3, MIPS_COP_0_CONFIG, 3);
207 MIPS_RDRW32_COP0(count, MIPS_COP_0_COUNT);
208 MIPS_RDRW32_COP0(index, MIPS_COP_0_TLB_INDEX);
209 MIPS_RDRW32_COP0(wired, MIPS_COP_0_TLB_WIRED);
210 MIPS_RDRW32_COP0(cause, MIPS_COP_0_CAUSE);
211 MIPS_RDRW32_COP0(status, MIPS_COP_0_STATUS);
212
213 /* XXX: Some of these registers are specific to MIPS32. */
214 #if !defined(__mips_n64)
215 MIPS_RDRW32_COP0(entrylo0, MIPS_COP_0_TLB_LO0);
216 MIPS_RDRW32_COP0(entrylo1, MIPS_COP_0_TLB_LO1);
217 MIPS_RDRW32_COP0(entryhi, MIPS_COP_0_TLB_HI);
218 MIPS_RDRW32_COP0(pagemask, MIPS_COP_0_TLB_PG_MASK);
219 #endif
220 MIPS_RDRW32_COP0(prid, MIPS_COP_0_PRID);
221 /* XXX 64-bit? */
222 MIPS_RDRW32_COP0_SEL(ebase, MIPS_COP_0_PRID, 1);
223 MIPS_RDRW32_COP0(watchlo, MIPS_COP_0_WATCH_LO);
224 MIPS_RDRW32_COP0_SEL(watchlo1, MIPS_COP_0_WATCH_LO, 1);
225 MIPS_RDRW32_COP0_SEL(watchlo2, MIPS_COP_0_WATCH_LO, 2);
226 MIPS_RDRW32_COP0_SEL(watchlo3, MIPS_COP_0_WATCH_LO, 3);
227 MIPS_RDRW32_COP0(watchhi, MIPS_COP_0_WATCH_HI);
228 MIPS_RDRW32_COP0_SEL(watchhi1, MIPS_COP_0_WATCH_HI, 1);
229 MIPS_RDRW32_COP0_SEL(watchhi2, MIPS_COP_0_WATCH_HI, 2);
230 MIPS_RDRW32_COP0_SEL(watchhi3, MIPS_COP_0_WATCH_HI, 3);
231
232 MIPS_RDRW32_COP0_SEL(perfcnt0, MIPS_COP_0_PERFCNT, 0);
233 MIPS_RDRW32_COP0_SEL(perfcnt1, MIPS_COP_0_PERFCNT, 1);
234 MIPS_RDRW32_COP0_SEL(perfcnt2, MIPS_COP_0_PERFCNT, 2);
235 MIPS_RDRW32_COP0_SEL(perfcnt3, MIPS_COP_0_PERFCNT, 3);
236
237 #undef MIPS_RDRW32_COP0
238
239 static __inline register_t
240 intr_disable(void)
241 {
242 register_t s;
243
244 s = mips_rd_status();
245 mips_wr_status(s & ~MIPS_SR_INT_IE);
246
247 return (s & MIPS_SR_INT_IE);
248 }
249
250 static __inline register_t
251 intr_enable(void)
252 {
253 register_t s;
254
255 s = mips_rd_status();
256 mips_wr_status(s | MIPS_SR_INT_IE);
257
258 return (s);
259 }
260
261 static __inline void
262 intr_restore(register_t ie)
263 {
264 if (ie == MIPS_SR_INT_IE) {
265 intr_enable();
266 }
267 }
268
269 static __inline uint32_t
270 set_intr_mask(uint32_t mask)
271 {
272 uint32_t ostatus;
273
274 ostatus = mips_rd_status();
275 mask = (ostatus & ~MIPS_SR_INT_MASK) | (mask & MIPS_SR_INT_MASK);
276 mips_wr_status(mask);
277 return (ostatus);
278 }
279
280 static __inline uint32_t
281 get_intr_mask(void)
282 {
283
284 return (mips_rd_status() & MIPS_SR_INT_MASK);
285 }
286
287 static __inline void
288 breakpoint(void)
289 {
290 __asm __volatile ("break");
291 }
292
293 #if defined(__GNUC__) && !defined(__mips_o32)
294 static inline uint64_t
295 mips3_ld(const volatile uint64_t *va)
296 {
297 uint64_t rv;
298
299 #if defined(_LP64)
300 rv = *va;
301 #else
302 __asm volatile("ld %0,0(%1)" : "=d"(rv) : "r"(va));
303 #endif
304
305 return (rv);
306 }
307
308 static inline void
309 mips3_sd(volatile uint64_t *va, uint64_t v)
310 {
311 #if defined(_LP64)
312 *va = v;
313 #else
314 __asm volatile("sd %0,0(%1)" :: "r"(v), "r"(va));
315 #endif
316 }
317 #else
318 uint64_t mips3_ld(volatile uint64_t *va);
319 void mips3_sd(volatile uint64_t *, uint64_t);
320 #endif /* __GNUC__ */
321
322 #endif /* _KERNEL */
323
324 #define readb(va) (*(volatile uint8_t *) (va))
325 #define readw(va) (*(volatile uint16_t *) (va))
326 #define readl(va) (*(volatile uint32_t *) (va))
327
328 #define writeb(va, d) (*(volatile uint8_t *) (va) = (d))
329 #define writew(va, d) (*(volatile uint16_t *) (va) = (d))
330 #define writel(va, d) (*(volatile uint32_t *) (va) = (d))
331
332 /*
333 * I/O macros.
334 */
335
336 #define outb(a,v) (*(volatile unsigned char*)(a) = (v))
337 #define out8(a,v) (*(volatile unsigned char*)(a) = (v))
338 #define outw(a,v) (*(volatile unsigned short*)(a) = (v))
339 #define out16(a,v) outw(a,v)
340 #define outl(a,v) (*(volatile unsigned int*)(a) = (v))
341 #define out32(a,v) outl(a,v)
342 #define inb(a) (*(volatile unsigned char*)(a))
343 #define in8(a) (*(volatile unsigned char*)(a))
344 #define inw(a) (*(volatile unsigned short*)(a))
345 #define in16(a) inw(a)
346 #define inl(a) (*(volatile unsigned int*)(a))
347 #define in32(a) inl(a)
348
349 #define out8rb(a,v) (*(volatile unsigned char*)(a) = (v))
350 #define out16rb(a,v) (__out16rb((volatile uint16_t *)(a), v))
351 #define out32rb(a,v) (__out32rb((volatile uint32_t *)(a), v))
352 #define in8rb(a) (*(volatile unsigned char*)(a))
353 #define in16rb(a) (__in16rb((volatile uint16_t *)(a)))
354 #define in32rb(a) (__in32rb((volatile uint32_t *)(a)))
355
356 #define _swap_(x) (((x) >> 24) | ((x) << 24) | \
357 (((x) >> 8) & 0xff00) | (((x) & 0xff00) << 8))
358
359 static __inline void __out32rb(volatile uint32_t *, uint32_t);
360 static __inline void __out16rb(volatile uint16_t *, uint16_t);
361 static __inline uint32_t __in32rb(volatile uint32_t *);
362 static __inline uint16_t __in16rb(volatile uint16_t *);
363
364 static __inline void
365 __out32rb(volatile uint32_t *a, uint32_t v)
366 {
367 uint32_t _v_ = v;
368
369 _v_ = _swap_(_v_);
370 out32(a, _v_);
371 }
372
373 static __inline void
374 __out16rb(volatile uint16_t *a, uint16_t v)
375 {
376 uint16_t _v_;
377
378 _v_ = ((v >> 8) & 0xff) | (v << 8);
379 out16(a, _v_);
380 }
381
382 static __inline uint32_t
383 __in32rb(volatile uint32_t *a)
384 {
385 uint32_t _v_;
386
387 _v_ = in32(a);
388 _v_ = _swap_(_v_);
389 return _v_;
390 }
391
392 static __inline uint16_t
393 __in16rb(volatile uint16_t *a)
394 {
395 uint16_t _v_;
396
397 _v_ = in16(a);
398 _v_ = ((_v_ >> 8) & 0xff) | (_v_ << 8);
399 return _v_;
400 }
401
402 void insb(uint8_t *, uint8_t *,int);
403 void insw(uint16_t *, uint16_t *,int);
404 void insl(uint32_t *, uint32_t *,int);
405 void outsb(uint8_t *, const uint8_t *,int);
406 void outsw(uint16_t *, const uint16_t *,int);
407 void outsl(uint32_t *, const uint32_t *,int);
408 u_int loadandclear(volatile u_int *addr);
409
410 #endif /* !_MACHINE_CPUFUNC_H_ */
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