1 /* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */
2
3 /*
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * @(#)machConst.h 8.1 (Berkeley) 6/10/93
35 *
36 * machConst.h --
37 *
38 * Machine dependent constants.
39 *
40 * Copyright (C) 1989 Digital Equipment Corporation.
41 * Permission to use, copy, modify, and distribute this software and
42 * its documentation for any purpose and without fee is hereby granted,
43 * provided that the above copyright notice appears in all copies.
44 * Digital Equipment Corporation makes no representations about the
45 * suitability of this software for any purpose. It is provided "as is"
46 * without express or implied warranty.
47 *
48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
54 *
55 * $FreeBSD: releng/11.0/sys/mips/include/cpuregs.h 295150 2016-02-02 16:00:42Z adrian $
56 */
57
58 #ifndef _MIPS_CPUREGS_H_
59 #define _MIPS_CPUREGS_H_
60
61 /*
62 * Address space.
63 * 32-bit mips CPUS partition their 32-bit address space into four segments:
64 *
65 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
66 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
67 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
68 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
69 *
70 * Caching of mapped addresses is controlled by bits in the TLB entry.
71 */
72
73 #define MIPS_KSEG0_LARGEST_PHYS (0x20000000)
74 #define MIPS_KSEG0_PHYS_MASK (0x1fffffff)
75 #define MIPS_XKPHYS_LARGEST_PHYS (0x10000000000) /* 40 bit PA */
76 #define MIPS_XKPHYS_PHYS_MASK (0x0ffffffffff)
77
78 #ifndef LOCORE
79 #define MIPS_KUSEG_START 0x00000000
80 #define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000)
81 #define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff)
82 #define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000)
83 #define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff)
84 #define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000)
85 #define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff)
86 #define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000)
87 #define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff)
88 #define MIPS_KSEG2_START MIPS_KSSEG_START
89 #define MIPS_KSEG2_END MIPS_KSSEG_END
90 #endif
91
92 #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START)
93 #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START)
94 #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK)
95 #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK)
96
97 #define MIPS_IS_KSEG0_ADDR(x) \
98 (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \
99 ((vm_offset_t)(x) <= MIPS_KSEG0_END))
100 #define MIPS_IS_KSEG1_ADDR(x) \
101 (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \
102 ((vm_offset_t)(x) <= MIPS_KSEG1_END))
103 #define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \
104 MIPS_IS_KSEG1_ADDR(x))
105
106 /*
107 * Cache Coherency Attributes:
108 * UC: Uncached.
109 * UA: Uncached accelerated.
110 * C: Cacheable, coherency unspecified.
111 * CNC: Cacheable non-coherent.
112 * CC: Cacheable coherent.
113 * CCS: Cacheable coherent, shared read.
114 * CCE: Cacheable coherent, exclusive read.
115 * CCEW: Cacheable coherent, exclusive write.
116 * CCUOW: Cacheable coherent, update on write.
117 *
118 * Note that some bits vary in meaning across implementations (and that the
119 * listing here is no doubt incomplete) and that the optimal cached mode varies
120 * between implementations. 0x02 is required to be UC and 0x03 is required to
121 * be a least C.
122 *
123 * We define the following logical bits:
124 * UNCACHED:
125 * The optimal uncached mode for the target CPU type. This must
126 * be suitable for use in accessing memory-mapped devices.
127 * CACHED: The optional cached mode for the target CPU type.
128 */
129
130 #define MIPS_CCA_UC 0x02 /* Uncached. */
131 #define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */
132
133 #if defined(CPU_R4000) || defined(CPU_R10000)
134 #define MIPS_CCA_CNC 0x03
135 #define MIPS_CCA_CCE 0x04
136 #define MIPS_CCA_CCEW 0x05
137
138 #ifdef CPU_R4000
139 #define MIPS_CCA_CCUOW 0x06
140 #endif
141
142 #ifdef CPU_R10000
143 #define MIPS_CCA_UA 0x07
144 #endif
145
146 #define MIPS_CCA_CACHED MIPS_CCA_CCEW
147 #endif /* defined(CPU_R4000) || defined(CPU_R10000) */
148
149 #if defined(CPU_SB1)
150 #define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */
151 #endif
152
153 #if defined(CPU_MIPS74K)
154 #define MIPS_CCA_UNCACHED 0x02
155 #define MIPS_CCA_CACHED 0x03
156 #endif
157
158 /*
159 * 1004K and 1074K cores, as well as interAptiv and proAptiv cores, support
160 * Cacheable Coherent CCAs 0x04 and 0x05, as well as Cacheable non-Coherent
161 * CCA 0x03 and Uncached Accelerated CCA 0x07
162 */
163 #if defined(CPU_MIPS1004K) || defined(CPU_MIPS1074K) || \
164 defined(CPU_INTERAPTIV) || defined(CPU_PROAPTIV)
165 #define MIPS_CCA_CNC 0x03
166 #define MIPS_CCA_CCE 0x04
167 #define MIPS_CCA_CCS 0x05
168 #define MIPS_CCA_UA 0x07
169
170 /* We use shared read CCA for CACHED CCA */
171 #define MIPS_CCA_CACHED MIPS_CCA_CCS
172 #endif
173
174 #ifndef MIPS_CCA_UNCACHED
175 #define MIPS_CCA_UNCACHED MIPS_CCA_UC
176 #endif
177
178 /*
179 * If we don't know which cached mode to use and there is a cache coherent
180 * mode, use it. If there is not a cache coherent mode, use the required
181 * cacheable mode.
182 */
183 #ifndef MIPS_CCA_CACHED
184 #ifdef MIPS_CCA_CC
185 #define MIPS_CCA_CACHED MIPS_CCA_CC
186 #else
187 #define MIPS_CCA_CACHED MIPS_CCA_C
188 #endif
189 #endif
190
191 #define MIPS_PHYS_TO_XKPHYS(cca,x) \
192 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
193 #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
194 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x))
195 #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
196 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x))
197
198 #define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK)
199
200 #define MIPS_XKPHYS_START 0x8000000000000000
201 #define MIPS_XKPHYS_END 0xbfffffffffffffff
202 #define MIPS_XUSEG_START 0x0000000000000000
203 #define MIPS_XUSEG_END 0x0000010000000000
204 #define MIPS_XKSEG_START 0xc000000000000000
205 #define MIPS_XKSEG_END 0xc00000ff80000000
206 #define MIPS_XKSEG_COMPAT32_START 0xffffffff80000000
207 #define MIPS_XKSEG_COMPAT32_END 0xffffffffffffffff
208 #define MIPS_XKSEG_TO_COMPAT32(va) ((va) & 0xffffffff)
209
210 #ifdef __mips_n64
211 #define MIPS_DIRECT_MAPPABLE(pa) 1
212 #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_XKPHYS_CACHED(pa)
213 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_XKPHYS_UNCACHED(pa)
214 #define MIPS_DIRECT_TO_PHYS(va) MIPS_XKPHYS_TO_PHYS(va)
215 #else
216 #define MIPS_DIRECT_MAPPABLE(pa) ((pa) < MIPS_KSEG0_LARGEST_PHYS)
217 #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_KSEG0(pa)
218 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_KSEG1(pa)
219 #define MIPS_DIRECT_TO_PHYS(va) MIPS_KSEG0_TO_PHYS(va)
220 #endif
221
222 /* CPU dependent mtc0 hazard hook */
223 #if defined(CPU_CNMIPS) || defined(CPU_RMI)
224 #define COP0_SYNC
225 #elif defined(CPU_NLM)
226 #define COP0_SYNC .word 0xc0 /* ehb */
227 #elif defined(CPU_SB1)
228 #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
229 #elif defined(CPU_MIPS24K) || defined(CPU_MIPS34K) || \
230 defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) || \
231 defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) || \
232 defined(CPU_PROAPTIV)
233 /*
234 * According to MIPS32tm Architecture for Programmers, Vol.II, rev. 2.00:
235 * "As EHB becomes standard in MIPS implementations, the previous SSNOPs can be
236 * removed, leaving only the EHB".
237 * Also, all MIPS32 Release 2 implementations have the EHB instruction, which
238 * resolves all execution hazards. The same goes for MIPS32 Release 3.
239 */
240 #define COP0_SYNC .word 0xc0 /* ehb */
241 #else
242 /*
243 * Pick a reasonable default based on the "typical" spacing described in the
244 * "CP0 Hazards" chapter of MIPS Architecture Book Vol III.
245 */
246 #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; .word 0xc0;
247 #endif
248 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
249
250 /*
251 * The bits in the cause register.
252 *
253 * Bits common to r3000 and r4000:
254 *
255 * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
256 * MIPS_CR_COP_ERR Coprocessor error.
257 * MIPS_CR_IP Interrupt pending bits defined below.
258 * (same meaning as in CAUSE register).
259 * MIPS_CR_EXC_CODE The exception type (see exception codes below).
260 *
261 * Differences:
262 * r3k has 4 bits of execption type, r4k has 5 bits.
263 */
264 #define MIPS_CR_BR_DELAY 0x80000000
265 #define MIPS_CR_COP_ERR 0x30000000
266 #define MIPS_CR_EXC_CODE 0x0000007C /* five bits */
267 #define MIPS_CR_IP 0x0000FF00
268 #define MIPS_CR_EXC_CODE_SHIFT 2
269 #define MIPS_CR_COP_ERR_SHIFT 28
270
271 /*
272 * The bits in the status register. All bits are active when set to 1.
273 *
274 * R3000 status register fields:
275 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
276 * MIPS_SR_TS TLB shutdown.
277 *
278 * MIPS_SR_INT_IE Master (current) interrupt enable bit.
279 *
280 * Differences:
281 * r3k has cache control is via frobbing SR register bits, whereas the
282 * r4k cache control is via explicit instructions.
283 * r3k has a 3-entry stack of kernel/user bits, whereas the
284 * r4k has kernel/supervisor/user.
285 */
286 #define MIPS_SR_COP_USABILITY 0xf0000000
287 #define MIPS_SR_COP_0_BIT 0x10000000
288 #define MIPS_SR_COP_1_BIT 0x20000000
289 #define MIPS_SR_COP_2_BIT 0x40000000
290
291 /* r4k and r3k differences, see below */
292
293 #define MIPS_SR_MX 0x01000000 /* MIPS64 */
294 #define MIPS_SR_PX 0x00800000 /* MIPS64 */
295 #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
296 #define MIPS_SR_TS 0x00200000
297 #define MIPS_SR_DE 0x00010000
298
299 #define MIPS_SR_INT_IE 0x00000001
300 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
301 #define MIPS_SR_INT_MASK 0x0000ff00
302
303 /*
304 * R4000 status register bit definitons,
305 * where different from r2000/r3000.
306 */
307 #define MIPS_SR_XX 0x80000000
308 #define MIPS_SR_RP 0x08000000
309 #define MIPS_SR_FR 0x04000000
310 #define MIPS_SR_RE 0x02000000
311
312 #define MIPS_SR_DIAG_DL 0x01000000 /* QED 52xx */
313 #define MIPS_SR_DIAG_IL 0x00800000 /* QED 52xx */
314 #define MIPS_SR_SR 0x00100000
315 #define MIPS_SR_NMI 0x00080000 /* MIPS32/64 */
316 #define MIPS_SR_DIAG_CH 0x00040000
317 #define MIPS_SR_DIAG_CE 0x00020000
318 #define MIPS_SR_DIAG_PE 0x00010000
319 #define MIPS_SR_EIE 0x00010000 /* TX79/R5900 */
320 #define MIPS_SR_KX 0x00000080
321 #define MIPS_SR_SX 0x00000040
322 #define MIPS_SR_UX 0x00000020
323 #define MIPS_SR_KSU_MASK 0x00000018
324 #define MIPS_SR_KSU_USER 0x00000010
325 #define MIPS_SR_KSU_SUPER 0x00000008
326 #define MIPS_SR_KSU_KERNEL 0x00000000
327 #define MIPS_SR_ERL 0x00000004
328 #define MIPS_SR_EXL 0x00000002
329
330 /*
331 * The interrupt masks.
332 * If a bit in the mask is 1 then the interrupt is enabled (or pending).
333 */
334 #define MIPS_INT_MASK 0xff00
335 #define MIPS_INT_MASK_5 0x8000
336 #define MIPS_INT_MASK_4 0x4000
337 #define MIPS_INT_MASK_3 0x2000
338 #define MIPS_INT_MASK_2 0x1000
339 #define MIPS_INT_MASK_1 0x0800
340 #define MIPS_INT_MASK_0 0x0400
341 #define MIPS_HARD_INT_MASK 0xfc00
342 #define MIPS_SOFT_INT_MASK_1 0x0200
343 #define MIPS_SOFT_INT_MASK_0 0x0100
344
345 /*
346 * The bits in the MIPS3 config register.
347 *
348 * bit 0..5: R/W, Bit 6..31: R/O
349 */
350
351 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
352 #define MIPS_CONFIG_K0_MASK 0x00000007
353
354 /*
355 * R/W Update on Store Conditional
356 * 0: Store Conditional uses coherency algorithm specified by TLB
357 * 1: Store Conditional uses cacheable coherent update on write
358 */
359 #define MIPS_CONFIG_CU 0x00000008
360
361 #define MIPS_CONFIG_DB 0x00000010 /* Primary D-cache line size */
362 #define MIPS_CONFIG_IB 0x00000020 /* Primary I-cache line size */
363 #define MIPS_CONFIG_CACHE_L1_LSIZE(config, bit) \
364 (((config) & (bit)) ? 32 : 16)
365
366 #define MIPS_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
367 #define MIPS_CONFIG_DC_SHIFT 6
368 #define MIPS_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
369 #define MIPS_CONFIG_IC_SHIFT 9
370 #define MIPS_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
371
372 /* Cache size mode indication: available only on Vr41xx CPUs */
373 #define MIPS_CONFIG_CS 0x00001000
374 #define MIPS_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
375 #define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \
376 ((base) << (((config) & (mask)) >> (shift)))
377
378 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
379 #define MIPS_CONFIG_SE 0x00001000
380
381 /* Block ordering: 0: sequential, 1: sub-block */
382 #define MIPS_CONFIG_EB 0x00002000
383
384 /* ECC mode - 0: ECC mode, 1: parity mode */
385 #define MIPS_CONFIG_EM 0x00004000
386
387 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
388 #define MIPS_CONFIG_BE 0x00008000
389
390 /* Dirty Shared coherency state - 0: enabled, 1: disabled */
391 #define MIPS_CONFIG_SM 0x00010000
392
393 /* Secondary Cache - 0: present, 1: not present */
394 #define MIPS_CONFIG_SC 0x00020000
395
396 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
397 #define MIPS_CONFIG_EW_MASK 0x000c0000
398 #define MIPS_CONFIG_EW_SHIFT 18
399
400 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
401 #define MIPS_CONFIG_SW 0x00100000
402
403 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
404 #define MIPS_CONFIG_SS 0x00200000
405
406 /* Secondary Cache line size */
407 #define MIPS_CONFIG_SB_MASK 0x00c00000
408 #define MIPS_CONFIG_SB_SHIFT 22
409 #define MIPS_CONFIG_CACHE_L2_LSIZE(config) \
410 (0x10 << (((config) & MIPS_CONFIG_SB_MASK) >> MIPS_CONFIG_SB_SHIFT))
411
412 /* Write back data rate */
413 #define MIPS_CONFIG_EP_MASK 0x0f000000
414 #define MIPS_CONFIG_EP_SHIFT 24
415
416 /* System clock ratio - this value is CPU dependent */
417 #define MIPS_CONFIG_EC_MASK 0x70000000
418 #define MIPS_CONFIG_EC_SHIFT 28
419
420 /* Master-Checker Mode - 1: enabled */
421 #define MIPS_CONFIG_CM 0x80000000
422
423 /*
424 * The bits in the MIPS4 config register.
425 */
426
427 /*
428 * Location of exception vectors.
429 *
430 * Common vectors: reset and UTLB miss.
431 */
432 #define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000)
433 #define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000)
434
435 /*
436 * MIPS-III exception vectors
437 */
438 #define MIPS_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080)
439 #define MIPS_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100)
440 #define MIPS_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180)
441
442 /*
443 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
444 */
445 #define MIPS_INTR_EXC_VEC 0x80000200
446
447 /*
448 * Coprocessor 0 registers:
449 *
450 * v--- width for mips I,III,32,64
451 * (3=32bit, 6=64bit, i=impl dep)
452 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
453 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
454 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
455 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
456 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
457 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
458 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
459 * 7 MIPS_COP_0_INFO ..33 Info registers
460 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
461 * 9 MIPS_COP_0_COUNT .333 Count register.
462 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
463 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
464 * 12 MIPS_COP_0_STATUS 3333 Status register.
465 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
466 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
467 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
468 * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
469 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
470 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
471 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
472 * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 4.
473 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
474 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
475 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
476 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
477 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
478 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
479 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
480 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
481 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
482 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
483 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
484 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
485 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
486 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
487 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
488 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
489 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
490 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
491 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
492 */
493
494 /* Deal with inclusion from an assembly file. */
495 #if defined(_LOCORE) || defined(LOCORE)
496 #define _(n) $n
497 #else
498 #define _(n) n
499 #endif
500
501
502 #define MIPS_COP_0_TLB_INDEX _(0)
503 #define MIPS_COP_0_TLB_RANDOM _(1)
504 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
505
506 #define MIPS_COP_0_TLB_CONTEXT _(4)
507 /* $5 and $6 new with MIPS-III */
508 #define MIPS_COP_0_BAD_VADDR _(8)
509 #define MIPS_COP_0_TLB_HI _(10)
510 #define MIPS_COP_0_STATUS _(12)
511 #define MIPS_COP_0_CAUSE _(13)
512 #define MIPS_COP_0_EXC_PC _(14)
513 #define MIPS_COP_0_PRID _(15)
514
515 /* MIPS-III */
516 #define MIPS_COP_0_TLB_LO0 _(2)
517 #define MIPS_COP_0_TLB_LO1 _(3)
518
519 #define MIPS_COP_0_TLB_PG_MASK _(5)
520 #define MIPS_COP_0_TLB_WIRED _(6)
521
522 #define MIPS_COP_0_COUNT _(9)
523 #define MIPS_COP_0_COMPARE _(11)
524
525 #define MIPS_COP_0_CONFIG _(16)
526 #define MIPS_COP_0_LLADDR _(17)
527 #define MIPS_COP_0_WATCH_LO _(18)
528 #define MIPS_COP_0_WATCH_HI _(19)
529 #define MIPS_COP_0_TLB_XCONTEXT _(20)
530 #define MIPS_COP_0_ECC _(26)
531 #define MIPS_COP_0_CACHE_ERR _(27)
532 #define MIPS_COP_0_TAG_LO _(28)
533 #define MIPS_COP_0_TAG_HI _(29)
534 #define MIPS_COP_0_ERROR_PC _(30)
535
536 /* MIPS32/64 */
537 #define MIPS_COP_0_INFO _(7)
538 #define MIPS_COP_0_DEBUG _(23)
539 #define MIPS_COP_0_DEPC _(24)
540 #define MIPS_COP_0_PERFCNT _(25)
541 #define MIPS_COP_0_DATA_LO _(28)
542 #define MIPS_COP_0_DATA_HI _(29)
543 #define MIPS_COP_0_DESAVE _(31)
544
545 /* MIPS32 Config register definitions */
546 #define MIPS_MMU_NONE 0x00 /* No MMU present */
547 #define MIPS_MMU_TLB 0x01 /* Standard TLB */
548 #define MIPS_MMU_BAT 0x02 /* Standard BAT */
549 #define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */
550
551 #define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */
552 #define MIPS_CONFIG0_MT_SHIFT 7
553 #define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */
554 #define MIPS_CONFIG0_VI 0x00000008 /* instruction cache is virtual */
555
556 #define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */
557 #define MIPS_CONFIG1_TLBSZ_SHIFT 25
558
559 #define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */
560 #define MIPS_CONFIG1_IS_SHIFT 22
561 #define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */
562 #define MIPS_CONFIG1_IL_SHIFT 19
563 #define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */
564 #define MIPS_CONFIG1_IA_SHIFT 16
565 #define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */
566 #define MIPS_CONFIG1_DS_SHIFT 13
567 #define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */
568 #define MIPS_CONFIG1_DL_SHIFT 10
569 #define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */
570 #define MIPS_CONFIG1_DA_SHIFT 7
571 #define MIPS_CONFIG1_LOWBITS 0x0000007F
572 #define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */
573 #define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */
574 #define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */
575 #define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */
576 #define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */
577 #define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */
578 #define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */
579
580 #define MIPS_CONFIG2_SA_SHIFT 0 /* Secondary cache associativity */
581 #define MIPS_CONFIG2_SA_MASK 0xf
582 #define MIPS_CONFIG2_SL_SHIFT 4 /* Secondary cache line size */
583 #define MIPS_CONFIG2_SL_MASK 0xf
584 #define MIPS_CONFIG2_SS_SHIFT 8 /* Secondary cache sets per way */
585 #define MIPS_CONFIG2_SS_MASK 0xf
586
587 #define MIPS_CONFIG3_CMGCR_MASK (1 << 29) /* Coherence manager present */
588
589 #define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */
590 #define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */
591 #define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */
592
593 /*
594 * Values for the code field in a break instruction.
595 */
596 #define MIPS_BREAK_INSTR 0x0000000d
597 #define MIPS_BREAK_VAL_MASK 0x03ff0000
598 #define MIPS_BREAK_VAL_SHIFT 16
599 #define MIPS_BREAK_KDB_VAL 512
600 #define MIPS_BREAK_SSTEP_VAL 513
601 #define MIPS_BREAK_BRKPT_VAL 514
602 #define MIPS_BREAK_SOVER_VAL 515
603 #define MIPS_BREAK_DDB_VAL 516
604 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
605 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
606 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
607 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
608 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
609 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
610 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
611 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
612 #define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \
613 (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT))
614
615 /*
616 * Mininum and maximum cache sizes.
617 */
618 #define MIPS_MIN_CACHE_SIZE (16 * 1024)
619 #define MIPS_MAX_CACHE_SIZE (256 * 1024)
620 #define MIPS_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
621
622 /*
623 * The floating point version and status registers.
624 */
625 #define MIPS_FPU_ID $0
626 #define MIPS_FPU_CSR $31
627
628 /*
629 * The floating point coprocessor status register bits.
630 */
631 #define MIPS_FPU_ROUNDING_BITS 0x00000003
632 #define MIPS_FPU_ROUND_RN 0x00000000
633 #define MIPS_FPU_ROUND_RZ 0x00000001
634 #define MIPS_FPU_ROUND_RP 0x00000002
635 #define MIPS_FPU_ROUND_RM 0x00000003
636 #define MIPS_FPU_STICKY_BITS 0x0000007c
637 #define MIPS_FPU_STICKY_INEXACT 0x00000004
638 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
639 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010
640 #define MIPS_FPU_STICKY_DIV0 0x00000020
641 #define MIPS_FPU_STICKY_INVALID 0x00000040
642 #define MIPS_FPU_ENABLE_BITS 0x00000f80
643 #define MIPS_FPU_ENABLE_INEXACT 0x00000080
644 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
645 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
646 #define MIPS_FPU_ENABLE_DIV0 0x00000400
647 #define MIPS_FPU_ENABLE_INVALID 0x00000800
648 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000
649 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
650 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
651 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
652 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000
653 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000
654 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
655 #define MIPS_FPU_COND_BIT 0x00800000
656 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
657 #define MIPS_FPC_MBZ_BITS 0xfe7c0000
658
659
660 /*
661 * Constants to determine if have a floating point instruction.
662 */
663 #define MIPS_OPCODE_SHIFT 26
664 #define MIPS_OPCODE_C1 0x11
665
666 /* Coherence manager constants */
667 #define MIPS_CMGCRB_BASE 11
668 #define MIPS_CMGCRF_BASE (~((1 << MIPS_CMGCRB_BASE) - 1))
669
670 #endif /* _MIPS_CPUREGS_H_ */
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