The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/mips/include/cpuregs.h

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    1 /*      $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $      */
    2 
    3 /*
    4  * SPDX-License-Identifier: BSD-3-Clause
    5  *
    6  * Copyright (c) 1992, 1993
    7  *      The Regents of the University of California.  All rights reserved.
    8  *
    9  * This code is derived from software contributed to Berkeley by
   10  * Ralph Campbell and Rick Macklem.
   11  *
   12  * Redistribution and use in source and binary forms, with or without
   13  * modification, are permitted provided that the following conditions
   14  * are met:
   15  * 1. Redistributions of source code must retain the above copyright
   16  *    notice, this list of conditions and the following disclaimer.
   17  * 2. Redistributions in binary form must reproduce the above copyright
   18  *    notice, this list of conditions and the following disclaimer in the
   19  *    documentation and/or other materials provided with the distribution.
   20  * 3. Neither the name of the University nor the names of its contributors
   21  *    may be used to endorse or promote products derived from this software
   22  *    without specific prior written permission.
   23  *
   24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   34  * SUCH DAMAGE.
   35  *
   36  *      @(#)machConst.h 8.1 (Berkeley) 6/10/93
   37  *
   38  * machConst.h --
   39  *
   40  *      Machine dependent constants.
   41  *
   42  *      Copyright (C) 1989 Digital Equipment Corporation.
   43  *      Permission to use, copy, modify, and distribute this software and
   44  *      its documentation for any purpose and without fee is hereby granted,
   45  *      provided that the above copyright notice appears in all copies.
   46  *      Digital Equipment Corporation makes no representations about the
   47  *      suitability of this software for any purpose.  It is provided "as is"
   48  *      without express or implied warranty.
   49  *
   50  * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
   51  *      v 9.2 89/10/21 15:55:22 jhh Exp  SPRITE (DECWRL)
   52  * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
   53  *      v 1.2 89/08/15 18:28:21 rab Exp  SPRITE (DECWRL)
   54  * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
   55  *      v 9.1 89/09/18 17:33:00 shirriff Exp  SPRITE (DECWRL)
   56  *
   57  * $FreeBSD$
   58  */
   59 
   60 #ifndef _MIPS_CPUREGS_H_
   61 #define _MIPS_CPUREGS_H_
   62 
   63 #ifndef _KVM_MINIDUMP
   64 #include <machine/cca.h>
   65 #endif
   66 
   67 /*
   68  * Address space.
   69  * 32-bit mips CPUS partition their 32-bit address space into four segments:
   70  *
   71  * kuseg   0x00000000 - 0x7fffffff  User virtual mem,  mapped
   72  * kseg0   0x80000000 - 0x9fffffff  Physical memory, cached, unmapped
   73  * kseg1   0xa0000000 - 0xbfffffff  Physical memory, uncached, unmapped
   74  * kseg2   0xc0000000 - 0xffffffff  kernel-virtual,  mapped
   75  *
   76  * Caching of mapped addresses is controlled by bits in the TLB entry.
   77  */
   78 
   79 #define MIPS_KSEG0_LARGEST_PHYS         (0x20000000)
   80 #define MIPS_KSEG0_PHYS_MASK            (0x1fffffff)
   81 #define MIPS_XKPHYS_LARGEST_PHYS        (0x10000000000)  /* 40 bit PA */
   82 #define MIPS_XKPHYS_PHYS_MASK           (0x0ffffffffff)
   83 
   84 #ifndef LOCORE
   85 #define MIPS_KUSEG_START                0x00000000
   86 #define MIPS_KSEG0_START                ((intptr_t)(int32_t)0x80000000)
   87 #define MIPS_KSEG0_END                  ((intptr_t)(int32_t)0x9fffffff)
   88 #define MIPS_KSEG1_START                ((intptr_t)(int32_t)0xa0000000)
   89 #define MIPS_KSEG1_END                  ((intptr_t)(int32_t)0xbfffffff)
   90 #define MIPS_KSSEG_START                ((intptr_t)(int32_t)0xc0000000)
   91 #define MIPS_KSSEG_END                  ((intptr_t)(int32_t)0xdfffffff)
   92 #define MIPS_KSEG3_START                ((intptr_t)(int32_t)0xe0000000)
   93 #define MIPS_KSEG3_END                  ((intptr_t)(int32_t)0xffffffff)
   94 #define MIPS_KSEG2_START                MIPS_KSSEG_START
   95 #define MIPS_KSEG2_END                  MIPS_KSSEG_END
   96 #endif
   97 
   98 #define MIPS_PHYS_TO_KSEG0(x)           ((uintptr_t)(x) | MIPS_KSEG0_START)
   99 #define MIPS_PHYS_TO_KSEG1(x)           ((uintptr_t)(x) | MIPS_KSEG1_START)
  100 #define MIPS_KSEG0_TO_PHYS(x)           ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK)
  101 #define MIPS_KSEG1_TO_PHYS(x)           ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK)
  102 
  103 #define MIPS_IS_KSEG0_ADDR(x)                                   \
  104         (((vm_offset_t)(x) >= MIPS_KSEG0_START) &&              \
  105             ((vm_offset_t)(x) <= MIPS_KSEG0_END))
  106 #define MIPS_IS_KSEG1_ADDR(x)                                   \
  107         (((vm_offset_t)(x) >= MIPS_KSEG1_START) &&              \
  108             ((vm_offset_t)(x) <= MIPS_KSEG1_END))
  109 #define MIPS_IS_VALID_PTR(x)            (MIPS_IS_KSEG0_ADDR(x) || \
  110                                             MIPS_IS_KSEG1_ADDR(x))
  111 
  112 #define MIPS_PHYS_TO_XKPHYS(cca,x) \
  113         ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
  114 #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
  115         ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x))
  116 #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
  117         ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x))
  118 
  119 #define MIPS_XKPHYS_TO_PHYS(x)          ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK)
  120 
  121 #define MIPS_XKPHYS_START               0x8000000000000000
  122 #define MIPS_XKPHYS_END                 0xbfffffffffffffff
  123 #define MIPS_XUSEG_START                0x0000000000000000
  124 #define MIPS_XUSEG_END                  0x0000010000000000
  125 #define MIPS_XKSEG_START                0xc000000000000000
  126 #define MIPS_XKSEG_END                  0xc00000ff80000000
  127 #define MIPS_XKSEG_COMPAT32_START       0xffffffff80000000
  128 #define MIPS_XKSEG_COMPAT32_END         0xffffffffffffffff
  129 #define MIPS_XKSEG_TO_COMPAT32(va)      ((va) & 0xffffffff)
  130 
  131 #ifdef __mips_n64
  132 #define MIPS_DIRECT_MAPPABLE(pa)        1
  133 #define MIPS_PHYS_TO_DIRECT(pa)         MIPS_PHYS_TO_XKPHYS_CACHED(pa)
  134 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa)        MIPS_PHYS_TO_XKPHYS_UNCACHED(pa)
  135 #define MIPS_DIRECT_TO_PHYS(va)         MIPS_XKPHYS_TO_PHYS(va)
  136 #else
  137 #define MIPS_DIRECT_MAPPABLE(pa)        ((pa) < MIPS_KSEG0_LARGEST_PHYS)
  138 #define MIPS_PHYS_TO_DIRECT(pa)         MIPS_PHYS_TO_KSEG0(pa)
  139 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa)        MIPS_PHYS_TO_KSEG1(pa)
  140 #define MIPS_DIRECT_TO_PHYS(va)         MIPS_KSEG0_TO_PHYS(va)
  141 #endif
  142 
  143 /* CPU dependent mtc0 hazard hook */
  144 #if defined(CPU_CNMIPS) || defined(CPU_RMI)
  145 #define COP0_SYNC
  146 #elif defined(CPU_NLM)
  147 #define COP0_SYNC       .word 0xc0      /* ehb */
  148 #elif defined(CPU_SB1)
  149 #define COP0_SYNC  ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
  150 #elif defined(CPU_MIPS24K) || defined(CPU_MIPS34K) ||           \
  151       defined(CPU_MIPS74K) || defined(CPU_MIPS1004K)  ||        \
  152       defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) ||      \
  153       defined(CPU_PROAPTIV)
  154 /*
  155  * According to MIPS32tm Architecture for Programmers, Vol.II, rev. 2.00:
  156  * "As EHB becomes standard in MIPS implementations, the previous SSNOPs can be
  157  *  removed, leaving only the EHB".
  158  * Also, all MIPS32 Release 2 implementations have the EHB instruction, which
  159  * resolves all execution hazards. The same goes for MIPS32 Release 3.
  160  */
  161 #define COP0_SYNC       .word 0xc0      /* ehb */
  162 #else
  163 /*
  164  * Pick a reasonable default based on the "typical" spacing described in the
  165  * "CP0 Hazards" chapter of MIPS Architecture Book Vol III.
  166  */
  167 #define COP0_SYNC  ssnop; ssnop; ssnop; ssnop; .word 0xc0;
  168 #endif
  169 #define COP0_HAZARD_FPUENABLE   nop; nop; nop; nop;
  170 
  171 /*
  172  * The bits in the cause register.
  173  *
  174  * Bits common to r3000 and r4000:
  175  *
  176  *      MIPS_CR_BR_DELAY        Exception happened in branch delay slot.
  177  *      MIPS_CR_COP_ERR         Coprocessor error.
  178  *      MIPS_CR_IP              Interrupt pending bits defined below.
  179  *                              (same meaning as in CAUSE register).
  180  *      MIPS_CR_EXC_CODE        The exception type (see exception codes below).
  181  *
  182  * Differences:
  183  *  r3k has 4 bits of execption type, r4k has 5 bits.
  184  */
  185 #define MIPS_CR_BR_DELAY        0x80000000
  186 #define MIPS_CR_COP_ERR         0x30000000
  187 #define MIPS_CR_EXC_CODE        0x0000007C      /* five bits */
  188 #define MIPS_CR_IP              0x0000FF00
  189 #define MIPS_CR_EXC_CODE_SHIFT  2
  190 #define MIPS_CR_COP_ERR_SHIFT   28
  191 
  192 /*
  193  * The bits in the status register.  All bits are active when set to 1.
  194  *
  195  *      R3000 status register fields:
  196  *      MIPS_SR_COP_USABILITY   Control the usability of the four coprocessors.
  197  *      MIPS_SR_TS              TLB shutdown.
  198  *
  199  *      MIPS_SR_INT_IE          Master (current) interrupt enable bit.
  200  *
  201  * Differences:
  202  *      r3k has cache control is via frobbing SR register bits, whereas the
  203  *      r4k cache control is via explicit instructions.
  204  *      r3k has a 3-entry stack of kernel/user bits, whereas the
  205  *      r4k has kernel/supervisor/user.
  206  */
  207 #define MIPS_SR_COP_USABILITY   0xf0000000
  208 #define MIPS_SR_COP_0_BIT       0x10000000
  209 #define MIPS_SR_COP_1_BIT       0x20000000
  210 #define MIPS_SR_COP_2_BIT       0x40000000
  211 
  212         /* r4k and r3k differences, see below */
  213 
  214 #define MIPS_SR_MX              0x01000000      /* MIPS64 */
  215 #define MIPS_SR_PX              0x00800000      /* MIPS64 */
  216 #define MIPS_SR_BEV             0x00400000      /* Use boot exception vector */
  217 #define MIPS_SR_TS              0x00200000
  218 #define MIPS_SR_DE              0x00010000
  219 
  220 #define MIPS_SR_INT_IE          0x00000001
  221 /*#define MIPS_SR_MBZ           0x0f8000c0*/    /* Never used, true for r3k */
  222 #define MIPS_SR_INT_MASK        0x0000ff00
  223 
  224 /*
  225  * R4000 status register bit definitions,
  226  * where different from r2000/r3000.
  227  */
  228 #define MIPS_SR_XX              0x80000000
  229 #define MIPS_SR_RP              0x08000000
  230 #define MIPS_SR_FR              0x04000000
  231 #define MIPS_SR_RE              0x02000000
  232 
  233 #define MIPS_SR_DIAG_DL 0x01000000              /* QED 52xx */
  234 #define MIPS_SR_DIAG_IL 0x00800000              /* QED 52xx */
  235 #define MIPS_SR_SR              0x00100000
  236 #define MIPS_SR_NMI             0x00080000              /* MIPS32/64 */
  237 #define MIPS_SR_DIAG_CH 0x00040000
  238 #define MIPS_SR_DIAG_CE 0x00020000
  239 #define MIPS_SR_DIAG_PE 0x00010000
  240 #define MIPS_SR_EIE             0x00010000              /* TX79/R5900 */
  241 #define MIPS_SR_KX              0x00000080
  242 #define MIPS_SR_SX              0x00000040
  243 #define MIPS_SR_UX              0x00000020
  244 #define MIPS_SR_KSU_MASK        0x00000018
  245 #define MIPS_SR_KSU_USER        0x00000010
  246 #define MIPS_SR_KSU_SUPER       0x00000008
  247 #define MIPS_SR_KSU_KERNEL      0x00000000
  248 #define MIPS_SR_ERL             0x00000004
  249 #define MIPS_SR_EXL             0x00000002
  250 
  251 /*
  252  * The interrupt masks.
  253  * If a bit in the mask is 1 then the interrupt is enabled (or pending).
  254  */
  255 #define MIPS_INT_MASK           0xff00
  256 #define MIPS_INT_MASK_5         0x8000
  257 #define MIPS_INT_MASK_4         0x4000
  258 #define MIPS_INT_MASK_3         0x2000
  259 #define MIPS_INT_MASK_2         0x1000
  260 #define MIPS_INT_MASK_1         0x0800
  261 #define MIPS_INT_MASK_0         0x0400
  262 #define MIPS_HARD_INT_MASK      0xfc00
  263 #define MIPS_SOFT_INT_MASK_1    0x0200
  264 #define MIPS_SOFT_INT_MASK_0    0x0100
  265 
  266 /*
  267  * The bits in the MIPS3 config register.
  268  *
  269  *      bit 0..5: R/W, Bit 6..31: R/O
  270  */
  271 
  272 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
  273 #define MIPS_CONFIG_K0_MASK     0x00000007
  274 
  275 /*
  276  * R/W Update on Store Conditional
  277  *      0: Store Conditional uses coherency algorithm specified by TLB
  278  *      1: Store Conditional uses cacheable coherent update on write
  279  */
  280 #define MIPS_CONFIG_CU          0x00000008
  281 
  282 #define MIPS_CONFIG_DB          0x00000010      /* Primary D-cache line size */
  283 #define MIPS_CONFIG_IB          0x00000020      /* Primary I-cache line size */
  284 #define MIPS_CONFIG_CACHE_L1_LSIZE(config, bit) \
  285         (((config) & (bit)) ? 32 : 16)
  286 
  287 #define MIPS_CONFIG_DC_MASK     0x000001c0      /* Primary D-cache size */
  288 #define MIPS_CONFIG_DC_SHIFT    6
  289 #define MIPS_CONFIG_IC_MASK     0x00000e00      /* Primary I-cache size */
  290 #define MIPS_CONFIG_IC_SHIFT    9
  291 #define MIPS_CONFIG_C_DEFBASE   0x1000          /* default base 2^12 */
  292 
  293 /* Cache size mode indication: available only on Vr41xx CPUs */
  294 #define MIPS_CONFIG_CS          0x00001000
  295 #define MIPS_CONFIG_C_4100BASE  0x0400          /* base is 2^10 if CS=1 */
  296 #define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \
  297         ((base) << (((config) & (mask)) >> (shift)))
  298 
  299 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
  300 #define MIPS_CONFIG_SE          0x00001000
  301 
  302 /* Block ordering: 0: sequential, 1: sub-block */
  303 #define MIPS_CONFIG_EB          0x00002000
  304 
  305 /* ECC mode - 0: ECC mode, 1: parity mode */
  306 #define MIPS_CONFIG_EM          0x00004000
  307 
  308 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
  309 #define MIPS_CONFIG_BE          0x00008000
  310 
  311 /* Dirty Shared coherency state - 0: enabled, 1: disabled */
  312 #define MIPS_CONFIG_SM          0x00010000
  313 
  314 /* Secondary Cache - 0: present, 1: not present */
  315 #define MIPS_CONFIG_SC          0x00020000
  316 
  317 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
  318 #define MIPS_CONFIG_EW_MASK     0x000c0000
  319 #define MIPS_CONFIG_EW_SHIFT    18
  320 
  321 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
  322 #define MIPS_CONFIG_SW          0x00100000
  323 
  324 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
  325 #define MIPS_CONFIG_SS          0x00200000
  326 
  327 /* Secondary Cache line size */
  328 #define MIPS_CONFIG_SB_MASK     0x00c00000
  329 #define MIPS_CONFIG_SB_SHIFT    22
  330 #define MIPS_CONFIG_CACHE_L2_LSIZE(config) \
  331         (0x10 << (((config) & MIPS_CONFIG_SB_MASK) >> MIPS_CONFIG_SB_SHIFT))
  332 
  333 /* Write back data rate */
  334 #define MIPS_CONFIG_EP_MASK     0x0f000000
  335 #define MIPS_CONFIG_EP_SHIFT    24
  336 
  337 /* System clock ratio - this value is CPU dependent */
  338 #define MIPS_CONFIG_EC_MASK     0x70000000
  339 #define MIPS_CONFIG_EC_SHIFT    28
  340 
  341 /* Master-Checker Mode - 1: enabled */
  342 #define MIPS_CONFIG_CM          0x80000000
  343 
  344 /*
  345  * The bits in the MIPS4 config register.
  346  */
  347 
  348 /*
  349  * Location of exception vectors.
  350  *
  351  * Common vectors:  reset and UTLB miss.
  352  */
  353 #define MIPS_RESET_EXC_VEC      ((intptr_t)(int32_t)0xBFC00000)
  354 #define MIPS_UTLB_MISS_EXC_VEC  ((intptr_t)(int32_t)0x80000000)
  355 
  356 /*
  357  * MIPS-III exception vectors
  358  */
  359 #define MIPS_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080)
  360 #define MIPS_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100)
  361 #define MIPS_GEN_EXC_VEC        ((intptr_t)(int32_t)0x80000180)
  362 
  363 /*
  364  * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
  365  */
  366 #define MIPS_INTR_EXC_VEC       0x80000200
  367 
  368 /*
  369  * Coprocessor 0 registers:
  370  *
  371  *                              v--- width for mips I,III,32,64
  372  *                                   (3=32bit, 6=64bit, i=impl dep)
  373  *  0   MIPS_COP_0_TLB_INDEX    3333 TLB Index.
  374  *  1   MIPS_COP_0_TLB_RANDOM   3333 TLB Random.
  375  *  2   MIPS_COP_0_TLB_LO0      .636 r4k TLB entry low.
  376  *  3   MIPS_COP_0_TLB_LO1      .636 r4k TLB entry low, extended.
  377  *  4   MIPS_COP_0_TLB_CONTEXT  3636 TLB Context.
  378  *  4/2 MIPS_COP_0_USERLOCAL    ..36 UserLocal.
  379  *  5   MIPS_COP_0_TLB_PG_MASK  .333 TLB Page Mask register.
  380  *  6   MIPS_COP_0_TLB_WIRED    .333 Wired TLB number.
  381  *  7   MIPS_COP_0_HWRENA       ..33 rdHWR Enable.
  382  *  8   MIPS_COP_0_BAD_VADDR    3636 Bad virtual address.
  383  *  9   MIPS_COP_0_COUNT        .333 Count register.
  384  * 10   MIPS_COP_0_TLB_HI       3636 TLB entry high.
  385  * 11   MIPS_COP_0_COMPARE      .333 Compare (against Count).
  386  * 12   MIPS_COP_0_STATUS       3333 Status register.
  387  * 12/1 MIPS_COP_0_INTCTL       ..33 Interrupt setup (MIPS32/64 r2).
  388  * 13   MIPS_COP_0_CAUSE        3333 Exception cause register.
  389  * 14   MIPS_COP_0_EXC_PC       3636 Exception PC.
  390  * 15   MIPS_COP_0_PRID         3333 Processor revision identifier.
  391  * 16   MIPS_COP_0_CONFIG       3333 Configuration register.
  392  * 16/1 MIPS_COP_0_CONFIG1      ..33 Configuration register 1.
  393  * 16/2 MIPS_COP_0_CONFIG2      ..33 Configuration register 2.
  394  * 16/3 MIPS_COP_0_CONFIG3      ..33 Configuration register 3.
  395  * 16/4 MIPS_COP_0_CONFIG4      ..33 Configuration register 4.
  396  * 17   MIPS_COP_0_LLADDR       .336 Load Linked Address.
  397  * 18   MIPS_COP_0_WATCH_LO     .336 WatchLo register.
  398  * 19   MIPS_COP_0_WATCH_HI     .333 WatchHi register.
  399  * 20   MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
  400  * 23   MIPS_COP_0_DEBUG        .... Debug JTAG register.
  401  * 24   MIPS_COP_0_DEPC         .... DEPC JTAG register.
  402  * 25   MIPS_COP_0_PERFCNT      ..36 Performance Counter register.
  403  * 26   MIPS_COP_0_ECC          .3ii ECC / Error Control register.
  404  * 27   MIPS_COP_0_CACHE_ERR    .3ii Cache Error register.
  405  * 28/0 MIPS_COP_0_TAG_LO       .3ii Cache TagLo register (instr).
  406  * 28/1 MIPS_COP_0_DATA_LO      ..ii Cache DataLo register (instr).
  407  * 28/2 MIPS_COP_0_TAG_LO       ..ii Cache TagLo register (data).
  408  * 28/3 MIPS_COP_0_DATA_LO      ..ii Cache DataLo register (data).
  409  * 29/0 MIPS_COP_0_TAG_HI       .3ii Cache TagHi register (instr).
  410  * 29/1 MIPS_COP_0_DATA_HI      ..ii Cache DataHi register (instr).
  411  * 29/2 MIPS_COP_0_TAG_HI       ..ii Cache TagHi register (data).
  412  * 29/3 MIPS_COP_0_DATA_HI      ..ii Cache DataHi register (data).
  413  * 30   MIPS_COP_0_ERROR_PC     .636 Error EPC register.
  414  * 31   MIPS_COP_0_DESAVE       .... DESAVE JTAG register.
  415  */
  416 
  417 /* Deal with inclusion from an assembly file. */
  418 #if defined(_LOCORE) || defined(LOCORE)
  419 #define _(n)    $n
  420 #else
  421 #define _(n)    n
  422 #endif
  423 
  424 
  425 #define MIPS_COP_0_TLB_INDEX    _(0)
  426 #define MIPS_COP_0_TLB_RANDOM   _(1)
  427         /* Name and meaning of  TLB bits for $2 differ on r3k and r4k. */
  428 
  429 #define MIPS_COP_0_TLB_CONTEXT  _(4)
  430                                         /* $5 and $6 new with MIPS-III */
  431 #define MIPS_COP_0_BAD_VADDR    _(8)
  432 #define MIPS_COP_0_TLB_HI       _(10)
  433 #define MIPS_COP_0_STATUS       _(12)
  434 #define MIPS_COP_0_CAUSE        _(13)
  435 #define MIPS_COP_0_EXC_PC       _(14)
  436 #define MIPS_COP_0_PRID         _(15)
  437 
  438 /* MIPS-III */
  439 #define MIPS_COP_0_TLB_LO0      _(2)
  440 #define MIPS_COP_0_TLB_LO1      _(3)
  441 
  442 #define MIPS_COP_0_TLB_PG_MASK  _(5)
  443 #define MIPS_COP_0_TLB_WIRED    _(6)
  444 
  445 #define MIPS_COP_0_COUNT        _(9)
  446 #define MIPS_COP_0_COMPARE      _(11)
  447 #ifdef CPU_XBURST
  448 #define MIPS_COP_0_XBURST_C12   _(12)
  449 #endif
  450 #define MIPS_COP_0_CONFIG       _(16)
  451 #define MIPS_COP_0_LLADDR       _(17)
  452 #define MIPS_COP_0_WATCH_LO     _(18)
  453 #define MIPS_COP_0_WATCH_HI     _(19)
  454 #define MIPS_COP_0_TLB_XCONTEXT _(20)
  455 #ifdef CPU_XBURST
  456 #define MIPS_COP_0_XBURST_MBOX  _(20)
  457 #endif
  458 
  459 #define MIPS_COP_0_ECC          _(26)
  460 #define MIPS_COP_0_CACHE_ERR    _(27)
  461 #define MIPS_COP_0_TAG_LO       _(28)
  462 #define MIPS_COP_0_TAG_HI       _(29)
  463 #define MIPS_COP_0_ERROR_PC     _(30)
  464 
  465 /* MIPS32/64 */
  466 #define MIPS_COP_0_USERLOCAL    _(4)    /* sel 2 is userlevel register */
  467 #define MIPS_COP_0_HWRENA       _(7)
  468 #define MIPS_COP_0_INTCTL       _(12)
  469 #define MIPS_COP_0_DEBUG        _(23)
  470 #define MIPS_COP_0_DEPC         _(24)
  471 #define MIPS_COP_0_PERFCNT      _(25)
  472 #define MIPS_COP_0_DATA_LO      _(28)
  473 #define MIPS_COP_0_DATA_HI      _(29)
  474 #define MIPS_COP_0_DESAVE       _(31)
  475 
  476 /* MIPS32 Config register definitions */
  477 #define MIPS_MMU_NONE                   0x00            /* No MMU present */
  478 #define MIPS_MMU_TLB                    0x01            /* Standard TLB */
  479 #define MIPS_MMU_BAT                    0x02            /* Standard BAT */
  480 #define MIPS_MMU_FIXED                  0x03            /* Standard fixed mapping */
  481 
  482 /*
  483  * IntCtl Register Fields
  484  */
  485 #define MIPS_INTCTL_IPTI_MASK   0xE0000000      /* bits 31..29 timer intr # */
  486 #define MIPS_INTCTL_IPTI_SHIFT  29
  487 #define MIPS_INTCTL_IPPCI_MASK  0x1C000000      /* bits 26..29 perf counter intr # */
  488 #define MIPS_INTCTL_IPPCI_SHIFT 26
  489 #define MIPS_INTCTL_VS_MASK     0x000001F0      /* bits 5..9 vector spacing */
  490 #define MIPS_INTCTL_VS_SHIFT    4
  491 
  492 /*
  493  * Config Register Fields
  494  * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9.39)
  495  */
  496 #define MIPS_CONFIG0_M          0x80000000      /* Flag: Config1 is present. */
  497 #define MIPS_CONFIG0_MT_MASK    0x00000380      /* bits 9..7 MMU Type */
  498 #define MIPS_CONFIG0_MT_SHIFT   7
  499 #define MIPS_CONFIG0_BE         0x00008000      /* data is big-endian */
  500 #define MIPS_CONFIG0_VI         0x00000008      /* inst cache is virtual */
  501  
  502 /*
  503  * Config1 Register Fields
  504  * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9-1)
  505  */
  506 #define MIPS_CONFIG1_M          0x80000000      /* Flag: Config2 is present. */
  507 #define MIPS_CONFIG1_TLBSZ_MASK         0x7E000000      /* bits 30..25 # tlb entries minus one */
  508 #define MIPS_CONFIG1_TLBSZ_SHIFT        25
  509 
  510 #define MIPS_CONFIG1_IS_MASK            0x01C00000      /* bits 24..22 icache sets per way */
  511 #define MIPS_CONFIG1_IS_SHIFT           22
  512 #define MIPS_CONFIG1_IL_MASK            0x00380000      /* bits 21..19 icache line size */
  513 #define MIPS_CONFIG1_IL_SHIFT           19
  514 #define MIPS_CONFIG1_IA_MASK            0x00070000      /* bits 18..16 icache associativity */
  515 #define MIPS_CONFIG1_IA_SHIFT           16
  516 #define MIPS_CONFIG1_DS_MASK            0x0000E000      /* bits 15..13 dcache sets per way */
  517 #define MIPS_CONFIG1_DS_SHIFT           13
  518 #define MIPS_CONFIG1_DL_MASK            0x00001C00      /* bits 12..10 dcache line size */
  519 #define MIPS_CONFIG1_DL_SHIFT           10
  520 #define MIPS_CONFIG1_DA_MASK            0x00000380      /* bits  9.. 7 dcache associativity */
  521 #define MIPS_CONFIG1_DA_SHIFT           7
  522 #define MIPS_CONFIG1_LOWBITS            0x0000007F
  523 #define MIPS_CONFIG1_C2                 0x00000040      /* Coprocessor 2 implemented */
  524 #define MIPS_CONFIG1_MD                 0x00000020      /* MDMX ASE implemented (MIPS64) */
  525 #define MIPS_CONFIG1_PC                 0x00000010      /* Performance counters implemented */
  526 #define MIPS_CONFIG1_WR                 0x00000008      /* Watch registers implemented */
  527 #define MIPS_CONFIG1_CA                 0x00000004      /* MIPS16e ISA implemented */
  528 #define MIPS_CONFIG1_EP                 0x00000002      /* EJTAG implemented */
  529 #define MIPS_CONFIG1_FP                 0x00000001      /* FPU implemented */
  530 
  531 #define MIPS_CONFIG2_SA_SHIFT           0               /* Secondary cache associativity */
  532 #define MIPS_CONFIG2_SA_MASK            0xf
  533 #define MIPS_CONFIG2_SL_SHIFT           4               /* Secondary cache line size */
  534 #define MIPS_CONFIG2_SL_MASK            0xf
  535 #define MIPS_CONFIG2_SS_SHIFT           8               /* Secondary cache sets per way */
  536 #define MIPS_CONFIG2_SS_MASK            0xf
  537 
  538 #define MIPS_CONFIG3_CMGCR_MASK         (1 << 29)       /* Coherence manager present */
  539 
  540 /*
  541  * Config2 Register Fields
  542  * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9.40)
  543  */
  544 #define MIPS_CONFIG2_M          0x80000000      /* Flag: Config3 is present. */
  545 
  546 /*
  547  * Config3 Register Fields
  548  * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9.41)
  549  */
  550 #define MIPS_CONFIG3_M          0x80000000      /* Flag: Config4 is present */
  551 #define MIPS_CONFIG3_ULR        0x00002000      /* UserLocal reg implemented */
  552 
  553 #define MIPS_CONFIG4_MMUSIZEEXT         0x000000FF      /* bits 7.. 0 MMU Size Extension */
  554 #define MIPS_CONFIG4_MMUEXTDEF          0x0000C000      /* bits 15.14 MMU Extension Definition */
  555 #define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT       0x00004000 /* This values denotes CONFIG4 bits  */
  556 
  557 /*
  558  * Values for the code field in a break instruction.
  559  */
  560 #define MIPS_BREAK_INSTR        0x0000000d
  561 #define MIPS_BREAK_VAL_MASK     0x03ff0000
  562 #define MIPS_BREAK_VAL_SHIFT    16
  563 #define MIPS_BREAK_KDB_VAL      512
  564 #define MIPS_BREAK_SSTEP_VAL    513
  565 #define MIPS_BREAK_BRKPT_VAL    514
  566 #define MIPS_BREAK_SOVER_VAL    515
  567 #define MIPS_BREAK_DDB_VAL      516
  568 #define MIPS_BREAK_KDB          (MIPS_BREAK_INSTR | \
  569                                 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
  570 #define MIPS_BREAK_SSTEP        (MIPS_BREAK_INSTR | \
  571                                 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
  572 #define MIPS_BREAK_BRKPT        (MIPS_BREAK_INSTR | \
  573                                 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
  574 #define MIPS_BREAK_SOVER        (MIPS_BREAK_INSTR | \
  575                                 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
  576 #define MIPS_BREAK_DDB          (MIPS_BREAK_INSTR | \
  577                                 (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT))
  578 
  579 /*
  580  * Mininum and maximum cache sizes.
  581  */
  582 #define MIPS_MIN_CACHE_SIZE     (16 * 1024)
  583 #define MIPS_MAX_CACHE_SIZE     (256 * 1024)
  584 #define MIPS_MAX_PCACHE_SIZE    (32 * 1024)     /* max. primary cache size */
  585 
  586 /*
  587  * The floating point version and status registers.
  588  */
  589 #define MIPS_FPU_ID     $0
  590 #define MIPS_FPU_CSR    $31
  591 
  592 /*
  593  * The floating point coprocessor status register bits.
  594  */
  595 #define MIPS_FPU_ROUNDING_BITS          0x00000003
  596 #define MIPS_FPU_ROUND_RN               0x00000000
  597 #define MIPS_FPU_ROUND_RZ               0x00000001
  598 #define MIPS_FPU_ROUND_RP               0x00000002
  599 #define MIPS_FPU_ROUND_RM               0x00000003
  600 #define MIPS_FPU_STICKY_BITS            0x0000007c
  601 #define MIPS_FPU_STICKY_INEXACT         0x00000004
  602 #define MIPS_FPU_STICKY_UNDERFLOW       0x00000008
  603 #define MIPS_FPU_STICKY_OVERFLOW        0x00000010
  604 #define MIPS_FPU_STICKY_DIV0            0x00000020
  605 #define MIPS_FPU_STICKY_INVALID         0x00000040
  606 #define MIPS_FPU_ENABLE_BITS            0x00000f80
  607 #define MIPS_FPU_ENABLE_INEXACT         0x00000080
  608 #define MIPS_FPU_ENABLE_UNDERFLOW       0x00000100
  609 #define MIPS_FPU_ENABLE_OVERFLOW        0x00000200
  610 #define MIPS_FPU_ENABLE_DIV0            0x00000400
  611 #define MIPS_FPU_ENABLE_INVALID         0x00000800
  612 #define MIPS_FPU_EXCEPTION_BITS         0x0003f000
  613 #define MIPS_FPU_EXCEPTION_INEXACT      0x00001000
  614 #define MIPS_FPU_EXCEPTION_UNDERFLOW    0x00002000
  615 #define MIPS_FPU_EXCEPTION_OVERFLOW     0x00004000
  616 #define MIPS_FPU_EXCEPTION_DIV0         0x00008000
  617 #define MIPS_FPU_EXCEPTION_INVALID      0x00010000
  618 #define MIPS_FPU_EXCEPTION_UNIMPL       0x00020000
  619 #define MIPS_FPU_COND_BIT               0x00800000
  620 #define MIPS_FPU_FLUSH_BIT              0x01000000      /* r4k,  MBZ on r3k */
  621 #define MIPS_FPC_MBZ_BITS               0xfe7c0000
  622 
  623 
  624 /*
  625  * Constants to determine if have a floating point instruction.
  626  */
  627 #define MIPS_OPCODE_SHIFT       26
  628 #define MIPS_OPCODE_C1          0x11
  629 
  630 /* Coherence manager constants */
  631 #define MIPS_CMGCRB_BASE        11
  632 #define MIPS_CMGCRF_BASE        (~((1 << MIPS_CMGCRB_BASE) - 1))
  633 
  634 /*
  635  * Bits defined for for the HWREna (CP0 register 7, select 0).
  636  */
  637 #define MIPS_HWRENA_CPUNUM      (1<<0)  /* CPU number program is running on */
  638 #define MIPS_HWRENA_SYNCI_STEP  (1<<1)  /* Address step sized used with SYNCI */
  639 #define MIPS_HWRENA_CC          (1<<2)  /* Hi Res cycle counter */
  640 #define MIPS_HWRENA_CCRES       (1<<3)  /* Cycle counter resolution */
  641 #define MIPS_HWRENA_UL          (1<<29) /* UserLocal Register */
  642 #define MIPS_HWRENA_IMPL30      (1<<30) /* Implementation-dependent 30 */
  643 #define MIPS_HWRENA_IMPL31      (1<<31) /* Implementation-dependent 31 */
  644 
  645 #endif /* _MIPS_CPUREGS_H_ */

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