The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/include/pte.h

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    1 /*-
    2  * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: releng/10.0/sys/mips/include/pte.h 257523 2013-11-01 20:30:19Z brooks $
   27  */
   28 
   29 #ifndef _MACHINE_PTE_H_
   30 #define _MACHINE_PTE_H_
   31 
   32 #ifndef _LOCORE
   33 #if defined(__mips_n64) || defined(__mips_n32) /*  PHYSADDR_64_BIT */
   34 typedef uint64_t pt_entry_t;
   35 #else
   36 typedef uint32_t pt_entry_t;
   37 #endif
   38 typedef pt_entry_t *pd_entry_t;
   39 #endif
   40 
   41 /*
   42  * TLB and PTE management.  Most things operate within the context of
   43  * EntryLo0,1, and begin with TLBLO_.  Things which work with EntryHi
   44  * start with TLBHI_.  PTE bits begin with PTE_.
   45  *
   46  * Note that we use the same size VM and TLB pages.
   47  */
   48 #define TLB_PAGE_SHIFT  (PAGE_SHIFT)
   49 #define TLB_PAGE_SIZE   (1 << TLB_PAGE_SHIFT)
   50 #define TLB_PAGE_MASK   (TLB_PAGE_SIZE - 1)
   51 
   52 /*
   53  * TLB PageMask register.  Has mask bits set above the default, 4K, page mask.
   54  */
   55 #define TLBMASK_SHIFT   (13)
   56 #define TLBMASK_MASK    ((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT)
   57 
   58 /*
   59  * FreeBSD/mips page-table entries take a near-identical format to MIPS TLB
   60  * entries, each consisting of two 32-bit or 64-bit values ("EntryHi" and
   61  * "EntryLo").  MIPS4k and MIPS64 both define certain bits in TLB entries as
   62  * reserved, and these must be zero-filled by software.  We overload these
   63  * bits in PTE entries to hold  PTE_ flags such as RO, W, and MANAGED.
   64  * However, we must mask these out when writing to TLB entries to ensure that
   65  * they do not become visible to hardware -- especially on MIPS64r2 which has
   66  * an extended physical memory space.
   67  *
   68  * When using n64 and n32, shift software-defined bits into the MIPS64r2
   69  * reserved range, which runs from bit 55 ... 63.  In other configurations
   70  * (32-bit MIPS4k and compatible), shift them out to bits 29 ... 31.
   71  *
   72  * NOTE: This means that for 32-bit use of CP0, we aren't able to set the top
   73  * bit of PFN to a non-zero value, as software is using it!  This physical
   74  * memory size limit may not be sufficiently enforced elsewhere.
   75  */
   76 #if defined(__mips_n64) || defined(__mips_n32) /*  PHYSADDR_64_BIT */
   77 #define TLBLO_SWBITS_SHIFT      (55)
   78 #define TLBLO_SWBITS_CLEAR_SHIFT        (9)
   79 #define TLBLO_PFN_MASK          0x3FFFFFFC0ULL
   80 #else
   81 #define TLBLO_SWBITS_SHIFT      (29)
   82 #define TLBLO_SWBITS_CLEAR_SHIFT        (3)
   83 #define TLBLO_PFN_MASK          (0x1FFFFFC0)
   84 #endif
   85 #define TLBLO_PFN_SHIFT         (6)
   86 #define TLBLO_SWBITS_MASK       ((pt_entry_t)0x7 << TLBLO_SWBITS_SHIFT)
   87 #define TLBLO_PA_TO_PFN(pa)     ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK)
   88 #define TLBLO_PFN_TO_PA(pfn)    ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT)
   89 #define TLBLO_PTE_TO_PFN(pte)   ((pte) & TLBLO_PFN_MASK)
   90 #define TLBLO_PTE_TO_PA(pte)    (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte))))
   91 
   92 /*
   93  * XXX This comment is not correct for anything more modern than R4K.
   94  *
   95  * VPN for EntryHi register.  Upper two bits select user, supervisor,
   96  * or kernel.  Bits 61 to 40 copy bit 63.  VPN2 is bits 39 and down to
   97  * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*.  From bit 12
   98  * to bit 8 there is a 5-bit 0 field.  Low byte is ASID.
   99  *
  100  * XXX This comment is not correct for FreeBSD.
  101  * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page.
  102  */
  103 #define TLBHI_ASID_MASK         (0xff)
  104 #if defined(__mips_n64)
  105 #define TLBHI_R_SHIFT           62
  106 #define TLBHI_R_USER            (0x00UL << TLBHI_R_SHIFT)
  107 #define TLBHI_R_SUPERVISOR      (0x01UL << TLBHI_R_SHIFT)
  108 #define TLBHI_R_KERNEL          (0x03UL << TLBHI_R_SHIFT)
  109 #define TLBHI_R_MASK            (0x03UL << TLBHI_R_SHIFT)
  110 #define TLBHI_VA_R(va)          ((va) & TLBHI_R_MASK)
  111 #define TLBHI_FILL_SHIFT        40
  112 #define TLBHI_VPN2_SHIFT        (TLB_PAGE_SHIFT + 1)
  113 #define TLBHI_VPN2_MASK         (((~((1UL << TLBHI_VPN2_SHIFT) - 1)) << (63 - TLBHI_FILL_SHIFT)) >> (63 - TLBHI_FILL_SHIFT))
  114 #define TLBHI_VA_TO_VPN2(va)    ((va) & TLBHI_VPN2_MASK)
  115 #define TLBHI_ENTRY(va, asid)   ((TLBHI_VA_R((va))) /* Region. */ | \
  116                                  (TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \
  117                                  ((asid) & TLBHI_ASID_MASK))
  118 #else /* !defined(__mips_n64) */
  119 #define TLBHI_PAGE_MASK         (2 * PAGE_SIZE - 1)
  120 #define TLBHI_ENTRY(va, asid)   (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
  121 #endif /* defined(__mips_n64) */
  122 
  123 /*
  124  * TLB flags managed in hardware:
  125  *      C:      Cache attribute.
  126  *      D:      Dirty bit.  This means a page is writable.  It is not
  127  *              set at first, and a write is trapped, and the dirty
  128  *              bit is set.  See also PTE_RO.
  129  *      V:      Valid bit.  Obvious, isn't it?
  130  *      G:      Global bit.  This means that this mapping is present
  131  *              in EVERY address space, and to ignore the ASID when
  132  *              it is matched.
  133  */
  134 #define PTE_C(attr)             ((attr & 0x07) << 3)
  135 #define PTE_C_UNCACHED          (PTE_C(MIPS_CCA_UNCACHED))
  136 #define PTE_C_CACHE             (PTE_C(MIPS_CCA_CACHED))
  137 #define PTE_D                   0x04
  138 #define PTE_V                   0x02
  139 #define PTE_G                   0x01
  140 
  141 /*
  142  * VM flags managed in software:
  143  *      RO:     Read only.  Never set PTE_D on this page, and don't
  144  *              listen to requests to write to it.
  145  *      W:      Wired.  ???
  146  *      MANAGED:Managed.  This PTE maps a managed page.
  147  *
  148  * These bits should not be written into the TLB, so must first be masked out
  149  * explicitly in C, or using CLEAR_PTE_SWBITS() in assembly.
  150  */
  151 #define PTE_RO                  ((pt_entry_t)0x01 << TLBLO_SWBITS_SHIFT)
  152 #define PTE_W                   ((pt_entry_t)0x02 << TLBLO_SWBITS_SHIFT)
  153 #define PTE_MANAGED             ((pt_entry_t)0x04 << TLBLO_SWBITS_SHIFT)
  154 
  155 /*
  156  * PTE management functions for bits defined above.
  157  */
  158 #define pte_clear(pte, bit)     (*(pte) &= ~(bit))
  159 #define pte_set(pte, bit)       (*(pte) |= (bit))
  160 #define pte_test(pte, bit)      ((*(pte) & (bit)) == (bit))
  161 
  162 /* Assembly support for PTE access*/
  163 #ifdef LOCORE
  164 #if defined(__mips_n64) || defined(__mips_n32) /*  PHYSADDR_64_BIT */
  165 #define PTESHIFT                3
  166 #define PTE2MASK                0xff0   /* for the 2-page lo0/lo1 */
  167 #define PTEMASK                 0xff8
  168 #define PTESIZE                 8
  169 #define PTE_L                   ld
  170 #define PTE_MTC0                dmtc0
  171 #define CLEAR_PTE_SWBITS(pr)
  172 #else
  173 #define PTESHIFT                2
  174 #define PTE2MASK                0xff8   /* for the 2-page lo0/lo1 */
  175 #define PTEMASK                 0xffc
  176 #define PTESIZE                 4
  177 #define PTE_L                   lw
  178 #define PTE_MTC0                mtc0
  179 #define CLEAR_PTE_SWBITS(r)     LONG_SLL r, TLBLO_SWBITS_CLEAR_SHIFT; LONG_SRL r, TLBLO_SWBITS_CLEAR_SHIFT /* remove swbits */
  180 #endif /* defined(__mips_n64) || defined(__mips_n32) */
  181 
  182 #if defined(__mips_n64)
  183 #define PTRSHIFT                3
  184 #define PDEPTRMASK              0xff8
  185 #else
  186 #define PTRSHIFT                2
  187 #define PDEPTRMASK              0xffc
  188 #endif
  189 
  190 #endif /* LOCORE */
  191 #endif /* !_MACHINE_PTE_H_ */

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