The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/include/pte.h

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    1 /*-
    2  * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: stable/8/sys/mips/include/pte.h 215938 2010-11-27 12:26:40Z jchandra $
   27  */
   28 
   29 #ifndef _MACHINE_PTE_H_
   30 #define _MACHINE_PTE_H_
   31 
   32 #ifndef _LOCORE
   33 /* pt_entry_t is 32 bit for now, has to be made 64 bit for n64 */
   34 typedef uint32_t pt_entry_t;
   35 typedef pt_entry_t *pd_entry_t;
   36 #endif
   37 
   38 /*
   39  * TLB and PTE management.  Most things operate within the context of
   40  * EntryLo0,1, and begin with TLBLO_.  Things which work with EntryHi
   41  * start with TLBHI_.  PTE bits begin with PTE_.
   42  *
   43  * Note that we use the same size VM and TLB pages.
   44  */
   45 #define TLB_PAGE_SHIFT  (PAGE_SHIFT)
   46 #define TLB_PAGE_SIZE   (1 << TLB_PAGE_SHIFT)
   47 #define TLB_PAGE_MASK   (TLB_PAGE_SIZE - 1)
   48 
   49 /*
   50  * TLB PageMask register.  Has mask bits set above the default, 4K, page mask.
   51  */
   52 #define TLBMASK_SHIFT   (13)
   53 #define TLBMASK_MASK    ((PAGE_MASK >> TLBMASK_SHIFT) << TLBMASK_SHIFT)
   54 
   55 /*
   56  * PFN for EntryLo register.  Upper bits are 0, which is to say that
   57  * bit 29 is the last hardware bit;  Bits 30 and upwards (EntryLo is
   58  * 64 bit though it can be referred to in 32-bits providing 2 software
   59  * bits safely.  We use it as 64 bits to get many software bits, and
   60  * god knows what else.) are unacknowledged by hardware.  They may be
   61  * written as anything, but otherwise they have as much meaning as
   62  * other 0 fields.
   63  */
   64 #define TLBLO_SWBITS_SHIFT      (30)
   65 #define TLBLO_SWBITS_MASK       (0x3U << TLBLO_SWBITS_SHIFT)
   66 #define TLBLO_PFN_SHIFT         (6)
   67 #define TLBLO_PFN_MASK          (0x3FFFFFC0)
   68 #define TLBLO_PA_TO_PFN(pa)     ((((pa) >> TLB_PAGE_SHIFT) << TLBLO_PFN_SHIFT) & TLBLO_PFN_MASK)
   69 #define TLBLO_PFN_TO_PA(pfn)    ((vm_paddr_t)((pfn) >> TLBLO_PFN_SHIFT) << TLB_PAGE_SHIFT)
   70 #define TLBLO_PTE_TO_PFN(pte)   ((pte) & TLBLO_PFN_MASK)
   71 #define TLBLO_PTE_TO_PA(pte)    (TLBLO_PFN_TO_PA(TLBLO_PTE_TO_PFN((pte))))
   72 
   73 /*
   74  * XXX This comment is not correct for anything more modern than R4K.
   75  *
   76  * VPN for EntryHi register.  Upper two bits select user, supervisor,
   77  * or kernel.  Bits 61 to 40 copy bit 63.  VPN2 is bits 39 and down to
   78  * as low as 13, down to PAGE_SHIFT, to index 2 TLB pages*.  From bit 12
   79  * to bit 8 there is a 5-bit 0 field.  Low byte is ASID.
   80  *
   81  * XXX This comment is not correct for FreeBSD.
   82  * Note that in FreeBSD, we map 2 TLB pages is equal to 1 VM page.
   83  */
   84 #define TLBHI_ASID_MASK         (0xff)
   85 #if defined(__mips_n64)
   86 #define TLBHI_R_SHIFT           62
   87 #define TLBHI_R_USER            (0x00UL << TLBHI_R_SHIFT)
   88 #define TLBHI_R_SUPERVISOR      (0x01UL << TLBHI_R_SHIFT)
   89 #define TLBHI_R_KERNEL          (0x03UL << TLBHI_R_SHIFT)
   90 #define TLBHI_R_MASK            (0x03UL << TLBHI_R_SHIFT)
   91 #define TLBHI_VA_R(va)          ((va) & TLBHI_R_MASK)
   92 #define TLBHI_FILL_SHIFT        40
   93 #define TLBHI_VPN2_SHIFT        (TLB_PAGE_SHIFT + 1)
   94 #define TLBHI_VPN2_MASK         (((~((1UL << TLBHI_VPN2_SHIFT) - 1)) << (63 - TLBHI_FILL_SHIFT)) >> (63 - TLBHI_FILL_SHIFT))
   95 #define TLBHI_VA_TO_VPN2(va)    ((va) & TLBHI_VPN2_MASK)
   96 #define TLBHI_ENTRY(va, asid)   ((TLBHI_VA_R((va))) /* Region. */ | \
   97                                  (TLBHI_VA_TO_VPN2((va))) /* VPN2. */ | \
   98                                  ((asid) & TLBHI_ASID_MASK))
   99 #else
  100 #define TLBHI_PAGE_MASK         (2 * PAGE_SIZE - 1)
  101 #define TLBHI_ENTRY(va, asid)   (((va) & ~TLBHI_PAGE_MASK) | ((asid) & TLBHI_ASID_MASK))
  102 #endif
  103 
  104 /*
  105  * TLB flags managed in hardware:
  106  *      C:      Cache attribute.
  107  *      D:      Dirty bit.  This means a page is writable.  It is not
  108  *              set at first, and a write is trapped, and the dirty
  109  *              bit is set.  See also PTE_RO.
  110  *      V:      Valid bit.  Obvious, isn't it?
  111  *      G:      Global bit.  This means that this mapping is present
  112  *              in EVERY address space, and to ignore the ASID when
  113  *              it is matched.
  114  */
  115 #define PTE_C(attr)     ((attr & 0x07) << 3)
  116 #define PTE_C_UNCACHED  (PTE_C(MIPS_CCA_UNCACHED))
  117 #define PTE_C_CACHE     (PTE_C(MIPS_CCA_CACHED))
  118 #define PTE_D           0x04
  119 #define PTE_V           0x02
  120 #define PTE_G           0x01
  121 
  122 /*
  123  * VM flags managed in software:
  124  *      RO:     Read only.  Never set PTE_D on this page, and don't
  125  *              listen to requests to write to it.
  126  *      W:      Wired.  ???
  127  */
  128 #define PTE_RO  (0x01 << TLBLO_SWBITS_SHIFT)
  129 #define PTE_W   (0x02 << TLBLO_SWBITS_SHIFT)
  130 
  131 /*
  132  * PTE management functions for bits defined above.
  133  */
  134 #define pte_clear(pte, bit)     (*(pte) &= ~(bit))
  135 #define pte_set(pte, bit)       (*(pte) |= (bit))
  136 #define pte_test(pte, bit)      ((*(pte) & (bit)) == (bit))
  137 
  138 #endif /* !_MACHINE_PTE_H_ */

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