The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/include/rm7000.h

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    1 /*      $OpenBSD$ */
    2 
    3 /*
    4  * Copyright (c) 2000 Opsycon Open System Consulting AB  (www.opsycon.se)
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  * 3. All advertising materials mentioning features or use of this software
   15  *    must display the following acknowledgement:
   16  *      This product includes software developed by Opsycon Open System
   17  *      Consulting AB, Sweden under contract to QED, Inc.
   18  * 4. The name of the author may not be used to endorse or promote products
   19  *    derived from this software without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
   22  * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
   23  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
   25  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   31  * SUCH DAMAGE.
   32  *
   33  *      JNPR: rm7000.h,v 1.2.4.1 2007/08/29 12:06:30 girish
   34  * $FreeBSD: releng/8.0/sys/mips/include/rm7000.h 178172 2008-04-13 07:27:37Z imp $
   35  */
   36 
   37 #ifndef _MACHINE_RM7000_H_
   38 #define _MACHINE_RM7000_H_
   39 
   40 /*
   41  *  QED RM7000 specific defines.
   42  */
   43 
   44 /*
   45  *  Performance counters.
   46  */
   47 
   48 #define PCNT_SRC_CLOCKS         0x00    /* Clock cycles */
   49 #define PCNT_SRC_INSTR          0x01    /* Total instructions issued */
   50 #define PCNT_SRC_FPINSTR        0x02    /* Float instructions issued */
   51 #define PCNT_SRC_IINSTR         0x03    /* Integer instructions issued */
   52 #define PCNT_SRC_LOAD           0x04    /* Load instructions issued */
   53 #define PCNT_SRC_STORE          0x05    /* Store instructions issued */
   54 #define PCNT_SRC_DUAL           0x06    /* Dual issued pairs */
   55 #define PCNT_SRC_BRPREF         0x07    /* Branch prefetches */
   56 #define PCNT_SRC_EXTMISS        0x08    /* External cache misses */
   57 #define PCNT_SRC_STALL          0x09    /* Stall cycles */
   58 #define PCNT_SRC_SECMISS        0x0a    /* Secondary cache misses */
   59 #define PCNT_SRC_INSMISS        0x0b    /* Instruction cache misses */
   60 #define PCNT_SRC_DTAMISS        0x0c    /* Data cache misses */
   61 #define PCNT_SRC_DTLBMISS       0x0d    /* Data TLB misses */
   62 #define PCNT_SRC_ITLBMISS       0x0e    /* Instruction TLB misses */
   63 #define PCNT_SRC_JTLBIMISS      0x0f    /* Joint TLB instruction misses */
   64 #define PCNT_SRC_JTLBDMISS      0x10    /* Joint TLB data misses */
   65 #define PCNT_SRC_BRTAKEN        0x11    /* Branches taken */
   66 #define PCNT_SRC_BRISSUED       0x12    /* Branches issued */
   67 #define PCNT_SRC_SECWBACK       0x13    /* Secondary cache writebacks */
   68 #define PCNT_SRC_PRIWBACK       0x14    /* Primary cache writebacks */
   69 #define PCNT_SRC_DCSTALL        0x15    /* Dcache miss stall cycles */
   70 #define PCNT_SRC_MISS           0x16    /* Cache misses */
   71 #define PCNT_SRC_FPEXC          0x17    /* FP possible execption cycles */
   72 #define PCNT_SRC_MULSLIP        0x18    /* Slip cycles due to mult. busy */
   73 #define PCNT_SRC_CP0SLIP        0x19    /* CP0 Slip cycles */
   74 #define PCNT_SRC_LDSLIP         0x1a    /* Slip cycles  due to pend. non-b ld */
   75 #define PCNT_SRC_WBFULL         0x1b    /* Write buffer full stall cycles  */
   76 #define PCNT_SRC_CISTALL        0x1c    /* Cache instruction stall cycles  */
   77 #define PCNT_SRC_MULSTALL       0x1d    /* Multiplier stall cycles  */
   78 #define PCNT_SRC_ELDSTALL       0x1d    /* Excepion stall due to non-b ld */
   79 #define PCNT_SRC_MAX            0x1d    /* Maximum PCNT select code */
   80 
   81 /*
   82  *  Counter control bits.
   83  */
   84 
   85 #define PCNT_CE                 0x0400  /* Count enable */
   86 #define PCNT_UM                 0x0200  /* Count in User mode */
   87 #define PCNT_KM                 0x0100  /* Count in kernel mode */
   88 
   89 /*
   90  *  Performance counter system call function codes.
   91  */
   92 #define PCNT_FNC_SELECT         0x0001  /* Select counter source */
   93 #define PCNT_FNC_READ           0x0002  /* Read current value of counter */
   94 
   95 #endif /* _MACHINE_RM7000_H_ */

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