The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/ingenic/jz4780_aic.h

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    1 /*-
    2  * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * This software was developed by SRI International and the University of
    6  * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
    7  * ("CTSRD"), as part of the DARPA CRASH research programme.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  *
   30  * $FreeBSD: stable/12/sys/mips/ingenic/jz4780_aic.h 309739 2016-12-09 17:16:09Z br $
   31  */
   32 
   33 #define AICFR           0x00    /* AIC Configuration Register */
   34 #define  AICFR_TFTH_S   16      /* Transmit FIFO threshold for interrupt or DMA request. */
   35 #define  AICFR_TFTH_M   (0x1f << AICFR_TFTH_S)
   36 #define  AICFR_TFTH(x)  ((x) << AICFR_TFTH_S)
   37 #define  AICFR_RFTH_S   24      /* Receive FIFO threshold for interrupt or DMA request. */
   38 #define  AICFR_RFTH_M   (0x0f << AICFR_RFTH_S)
   39 #define  AICFR_RFTH(x)  ((x) << AICFR_RFTH_S)
   40 #define  AICFR_ICDC     (1 << 5) /* Internal CODEC used. */
   41 #define  AICFR_AUSEL    (1 << 4) /* Audio Unit Select */
   42 #define  AICFR_RST      (1 << 3) /* Reset AIC. */
   43 #define  AICFR_BCKD     (1 << 2) /* BIT_CLK Direction. */
   44 #define  AICFR_SYNCD    (1 << 1) /* SYNC is generated internally and driven out to the CODEC. */
   45 #define  AICFR_ENB      (1 << 0) /* Enable AIC Controller. */
   46 #define AICCR           0x04    /* AIC Common Control Register */
   47 #define  AICCR_TFLUSH           (1 << 8) /* Transmit FIFO Flush. */
   48 #define  AICCR_RFLUSH           (1 << 7) /* Receive FIFO Flush. */
   49 #define  AICCR_CHANNEL_S        24
   50 #define  AICCR_CHANNEL_M        (0x7 << AICCR_CHANNEL_S)
   51 #define  AICCR_CHANNEL_2        (0x1 << AICCR_CHANNEL_S) /* 2 channels, stereo */
   52 #define  AICCR_ISS_S            16      /* Input Sample Size. */
   53 #define  AICCR_ISS_M            (0x7 << AICCR_ISS_S)
   54 #define  AICCR_ISS_16           (0x1 << AICCR_ISS_S)
   55 #define  AICCR_OSS_S            19      /* Output Sample Size. */
   56 #define  AICCR_OSS_M            (0x7 << AICCR_OSS_S)
   57 #define  AICCR_OSS_16           (0x1 << AICCR_OSS_S)
   58 #define  AICCR_RDMS             (1 << 15) /* Receive DMA enable. */
   59 #define  AICCR_TDMS             (1 << 14) /* Transmit DMA enable. */
   60 #define  AICCR_ENLBF            (1 << 2) /* Enable AIC Loop Back Function. */
   61 #define  AICCR_ERPL             (1 << 1) /* Enable Playing Back function. */
   62 #define I2SCR           0x10    /* AIC I2S/MSB-justified Control */
   63 #define  I2SCR_ESCLK    (1 << 4) /* Enable SYSCLK output. */
   64 #define  I2SCR_AMSL     (1 << 0) /* Select MSB-Justified Operation Mode. */
   65 #define AICSR           0x14    /* AIC FIFO Status Register Register */
   66 #define I2SSR           0x1C    /* AIC I2S/MSB-justified Status Register */
   67 #define I2SDIV          0x30    /* AIC I2S/MSB-justified Clock Divider Register */
   68 #define AICDR           0x34    /* AIC FIFO Data Port Register */
   69 #define SPENA           0x80    /* SPDIF Enable Register */
   70 #define SPCTRL          0x84    /* SPDIF Control Register */
   71 #define SPSTATE         0x88    /* SPDIF Status Register */
   72 #define SPCFG1          0x8C    /* SPDIF Configure 1 Register */
   73 #define SPCFG2          0x90    /* SPDIF Configure 2 Register */
   74 #define SPFIFO          0x94    /* SPDIF FIFO Register */

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