1 /*-
2 * Copyright 2015 Alexander Kabaev <kan@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /*
28 * Ingenic JZ4780 OTG PHY clock driver.
29 *
30 */
31
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/conf.h>
38 #include <sys/bus.h>
39 #include <sys/lock.h>
40 #include <sys/mutex.h>
41 #include <sys/resource.h>
42
43 #include <machine/bus.h>
44
45 #include <mips/ingenic/jz4780_clk.h>
46 #include <mips/ingenic/jz4780_regs.h>
47
48 /* JZ4780 OTG PHY clock */
49 static int jz4780_clk_otg_init(struct clknode *clk, device_t dev);
50 static int jz4780_clk_otg_recalc_freq(struct clknode *clk, uint64_t *freq);
51 static int jz4780_clk_otg_set_freq(struct clknode *clk, uint64_t fin,
52 uint64_t *fout, int flags, int *stop);
53
54 struct jz4780_clk_otg_sc {
55 struct mtx *clk_mtx;
56 struct resource *clk_res;
57 };
58
59 /*
60 * JZ4780 OTG PHY clock methods
61 */
62 static clknode_method_t jz4780_clk_otg_methods[] = {
63 CLKNODEMETHOD(clknode_init, jz4780_clk_otg_init),
64 CLKNODEMETHOD(clknode_recalc_freq, jz4780_clk_otg_recalc_freq),
65 CLKNODEMETHOD(clknode_set_freq, jz4780_clk_otg_set_freq),
66
67 CLKNODEMETHOD_END
68 };
69 DEFINE_CLASS_1(jz4780_clk_pll, jz4780_clk_otg_class, jz4780_clk_otg_methods,
70 sizeof(struct jz4780_clk_otg_sc), clknode_class);
71
72 static int
73 jz4780_clk_otg_init(struct clknode *clk, device_t dev)
74 {
75 struct jz4780_clk_otg_sc *sc;
76 uint32_t reg;
77
78 sc = clknode_get_softc(clk);
79 CLK_LOCK(sc);
80 /* Force the use fo the core clock */
81 reg = CLK_RD_4(sc, JZ_USBPCR1);
82 reg &= ~PCR_REFCLK_M;
83 reg |= PCR_REFCLK_CORE;
84 CLK_WR_4(sc, JZ_USBPCR1, reg);
85 CLK_UNLOCK(sc);
86
87 clknode_init_parent_idx(clk, 0);
88 return (0);
89 }
90
91 static const struct {
92 uint32_t div_val;
93 uint32_t freq;
94 } otg_div_table[] = {
95 { PCR_CLK_12, 12000000 },
96 { PCR_CLK_192, 19200000 },
97 { PCR_CLK_24, 24000000 },
98 { PCR_CLK_48, 48000000 }
99 };
100
101 static int
102 jz4780_clk_otg_recalc_freq(struct clknode *clk, uint64_t *freq)
103 {
104 struct jz4780_clk_otg_sc *sc;
105 uint32_t reg;
106 int i;
107
108 sc = clknode_get_softc(clk);
109 reg = CLK_RD_4(sc, JZ_USBPCR1);
110 reg &= PCR_CLK_M;
111
112 for (i = 0; i < nitems(otg_div_table); i++)
113 if (otg_div_table[i].div_val == reg)
114 *freq = otg_div_table[i].freq;
115 return (0);
116 }
117
118 static int
119 jz4780_clk_otg_set_freq(struct clknode *clk, uint64_t fin,
120 uint64_t *fout, int flags, int *stop)
121 {
122 struct jz4780_clk_otg_sc *sc;
123 uint32_t reg;
124 int i;
125
126 sc = clknode_get_softc(clk);
127
128 for (i = 0; i < nitems(otg_div_table) - 1; i++) {
129 if (*fout < (otg_div_table[i].freq + otg_div_table[i + 1].freq) / 2)
130 break;
131 }
132
133 *fout = otg_div_table[i].freq;
134
135 *stop = 1;
136 if (flags & CLK_SET_DRYRUN)
137 return (0);
138
139 CLK_LOCK(sc);
140 reg = CLK_RD_4(sc, JZ_USBPCR1);
141 /* Set the calculated values */
142 reg &= ~PCR_CLK_M;
143 reg |= otg_div_table[i].div_val;
144 /* Initiate the change */
145 CLK_WR_4(sc, JZ_USBPCR1, reg);
146 CLK_UNLOCK(sc);
147
148 return (0);
149 }
150
151 int jz4780_clk_otg_register(struct clkdom *clkdom,
152 struct clknode_init_def *clkdef, struct mtx *dev_mtx,
153 struct resource *mem_res)
154 {
155 struct clknode *clk;
156 struct jz4780_clk_otg_sc *sc;
157
158 clk = clknode_create(clkdom, &jz4780_clk_otg_class, clkdef);
159 if (clk == NULL)
160 return (1);
161
162 sc = clknode_get_softc(clk);
163 sc->clk_mtx = dev_mtx;
164 sc->clk_res = mem_res;
165 clknode_register(clkdom, clk);
166 return (0);
167 }
Cache object: 75fc2bdad4a6656054b0c0a195a31f0b
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