The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/mips/ingenic/jz4780_codec.c

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    1 /*-
    2  * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
    3  * All rights reserved.
    4  *
    5  * This software was developed by SRI International and the University of
    6  * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
    7  * ("CTSRD"), as part of the DARPA CRASH research programme.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  *
   18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   28  * SUCH DAMAGE.
   29  */
   30 
   31 /* Ingenic JZ4780 CODEC. */
   32 
   33 #include <sys/cdefs.h>
   34 __FBSDID("$FreeBSD: releng/12.0/sys/mips/ingenic/jz4780_codec.c 310776 2016-12-29 14:00:10Z jmcneill $");
   35 
   36 #include <sys/param.h>
   37 #include <sys/systm.h>
   38 #include <sys/conf.h>
   39 #include <sys/bus.h>
   40 #include <sys/kernel.h>
   41 #include <sys/module.h>
   42 #include <sys/lock.h>
   43 #include <sys/mutex.h>
   44 #include <sys/resource.h>
   45 #include <sys/rman.h>
   46 #include <sys/gpio.h>
   47 
   48 #include <machine/bus.h>
   49 
   50 #include <dev/fdt/fdt_common.h>
   51 #include <dev/ofw/ofw_bus.h>
   52 #include <dev/ofw/ofw_bus_subr.h>
   53 
   54 #include <dev/gpio/gpiobusvar.h>
   55 
   56 #include <dev/extres/clk/clk.h>
   57 
   58 #include <mips/ingenic/jz4780_common.h>
   59 #include <mips/ingenic/jz4780_codec.h>
   60 
   61 #define CI20_HP_PIN     13
   62 #define CI20_HP_PORT    3
   63 
   64 struct codec_softc {
   65         device_t                dev;
   66         struct resource         *res[1];
   67         bus_space_tag_t         bst;
   68         bus_space_handle_t      bsh;
   69         clk_t                   clk;
   70 };
   71 
   72 static struct resource_spec codec_spec[] = {
   73         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
   74         { -1, 0 }
   75 };
   76 
   77 static int codec_probe(device_t dev);
   78 static int codec_attach(device_t dev);
   79 static int codec_detach(device_t dev);
   80 void codec_print_registers(struct codec_softc *sc);
   81 
   82 static int
   83 codec_write(struct codec_softc *sc, uint32_t reg, uint32_t val)
   84 {
   85         uint32_t tmp;
   86 
   87         clk_enable(sc->clk);
   88 
   89         tmp = (reg << RGADW_RGADDR_S);
   90         tmp |= (val << RGADW_RGDIN_S);
   91         tmp |= RGADW_RGWR;
   92 
   93         WRITE4(sc, CODEC_RGADW, tmp);
   94 
   95         while(READ4(sc, CODEC_RGADW) & RGADW_RGWR)
   96                 ;
   97 
   98         clk_disable(sc->clk);
   99 
  100         return (0);
  101 }
  102 
  103 static int
  104 codec_read(struct codec_softc *sc, uint32_t reg)
  105 {
  106         uint32_t tmp;
  107 
  108         clk_enable(sc->clk);
  109 
  110         tmp = (reg << RGADW_RGADDR_S);
  111         WRITE4(sc, CODEC_RGADW, tmp);
  112 
  113         tmp = READ4(sc, CODEC_RGDATA);
  114 
  115         clk_disable(sc->clk);
  116 
  117         return (tmp);
  118 }
  119 
  120 void
  121 codec_print_registers(struct codec_softc *sc)
  122 {
  123 
  124         printf("codec SR %x\n", codec_read(sc, SR));
  125         printf("codec SR2 %x\n", codec_read(sc, SR2));
  126         printf("codec MR %x\n", codec_read(sc, MR));
  127         printf("codec AICR_DAC %x\n", codec_read(sc, AICR_DAC));
  128         printf("codec AICR_ADC %x\n", codec_read(sc, AICR_ADC));
  129         printf("codec CR_LO %x\n", codec_read(sc, CR_LO));
  130         printf("codec CR_HP %x\n", codec_read(sc, CR_HP));
  131         printf("codec CR_DMIC %x\n", codec_read(sc, CR_DMIC));
  132         printf("codec CR_MIC1 %x\n", codec_read(sc, CR_MIC1));
  133         printf("codec CR_MIC2 %x\n", codec_read(sc, CR_MIC2));
  134         printf("codec CR_LI1 %x\n", codec_read(sc, CR_LI1));
  135         printf("codec CR_LI2 %x\n", codec_read(sc, CR_LI2));
  136         printf("codec CR_DAC %x\n", codec_read(sc, CR_DAC));
  137         printf("codec CR_ADC %x\n", codec_read(sc, CR_ADC));
  138         printf("codec CR_MIX %x\n", codec_read(sc, CR_MIX));
  139         printf("codec DR_MIX %x\n", codec_read(sc, DR_MIX));
  140         printf("codec CR_VIC %x\n", codec_read(sc, CR_VIC));
  141         printf("codec CR_CK %x\n", codec_read(sc, CR_CK));
  142         printf("codec FCR_DAC %x\n", codec_read(sc, FCR_DAC));
  143         printf("codec FCR_ADC %x\n", codec_read(sc, FCR_ADC));
  144         printf("codec CR_TIMER_MSB %x\n", codec_read(sc, CR_TIMER_MSB));
  145         printf("codec CR_TIMER_LSB %x\n", codec_read(sc, CR_TIMER_LSB));
  146         printf("codec ICR %x\n", codec_read(sc, ICR));
  147         printf("codec IMR %x\n", codec_read(sc, IMR));
  148         printf("codec IFR %x\n", codec_read(sc, IFR));
  149         printf("codec IMR2 %x\n", codec_read(sc, IMR2));
  150         printf("codec IFR2 %x\n", codec_read(sc, IFR2));
  151         printf("codec GCR_HPL %x\n", codec_read(sc, GCR_HPL));
  152         printf("codec GCR_HPR %x\n", codec_read(sc, GCR_HPR));
  153         printf("codec GCR_LIBYL %x\n", codec_read(sc, GCR_LIBYL));
  154         printf("codec GCR_LIBYR %x\n", codec_read(sc, GCR_LIBYR));
  155         printf("codec GCR_DACL %x\n", codec_read(sc, GCR_DACL));
  156         printf("codec GCR_DACR %x\n", codec_read(sc, GCR_DACR));
  157         printf("codec GCR_MIC1 %x\n", codec_read(sc, GCR_MIC1));
  158         printf("codec GCR_MIC2 %x\n", codec_read(sc, GCR_MIC2));
  159         printf("codec GCR_ADCL %x\n", codec_read(sc, GCR_ADCL));
  160         printf("codec GCR_ADCR %x\n", codec_read(sc, GCR_ADCR));
  161         printf("codec GCR_MIXDACL %x\n", codec_read(sc, GCR_MIXDACL));
  162         printf("codec GCR_MIXDACR %x\n", codec_read(sc, GCR_MIXDACR));
  163         printf("codec GCR_MIXADCL %x\n", codec_read(sc, GCR_MIXADCL));
  164         printf("codec GCR_MIXADCR %x\n", codec_read(sc, GCR_MIXADCR));
  165         printf("codec CR_ADC_AGC %x\n", codec_read(sc, CR_ADC_AGC));
  166         printf("codec DR_ADC_AGC %x\n", codec_read(sc, DR_ADC_AGC));
  167 }
  168 
  169 /*
  170  * CI20 board-specific
  171  */
  172 static int
  173 ci20_hp_unmute(struct codec_softc *sc)
  174 {
  175         device_t dev;
  176         int port;
  177         int err;
  178         int pin;
  179 
  180         pin = CI20_HP_PIN;
  181         port = CI20_HP_PORT;
  182 
  183         dev = devclass_get_device(devclass_find("gpio"), port);
  184         if (dev == NULL)
  185                 return (0);
  186 
  187         err = GPIO_PIN_SETFLAGS(dev, pin, GPIO_PIN_OUTPUT);
  188         if (err != 0) {
  189                 device_printf(dev, "Cannot configure GPIO pin %d on %s\n",
  190                     pin, device_get_nameunit(dev));
  191                 return (err);
  192         }
  193 
  194         err = GPIO_PIN_SET(dev, pin, 0);
  195         if (err != 0) {
  196                 device_printf(dev, "Cannot configure GPIO pin %d on %s\n",
  197                     pin, device_get_nameunit(dev));
  198                 return (err);
  199         }
  200 
  201         return (0);
  202 }
  203 
  204 static int
  205 codec_probe(device_t dev)
  206 {
  207 
  208         if (!ofw_bus_status_okay(dev))
  209                 return (ENXIO);
  210 
  211         if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-codec"))
  212                 return (ENXIO);
  213 
  214         device_set_desc(dev, "Ingenic JZ4780 CODEC");
  215 
  216         return (BUS_PROBE_DEFAULT);
  217 }
  218 
  219 static int
  220 codec_attach(device_t dev)
  221 {
  222         struct codec_softc *sc;
  223         uint8_t reg;
  224 
  225         sc = device_get_softc(dev);
  226         sc->dev = dev;
  227 
  228         if (bus_alloc_resources(dev, codec_spec, sc->res)) {
  229                 device_printf(dev, "could not allocate resources for device\n");
  230                 return (ENXIO);
  231         }
  232 
  233         /* Memory interface */
  234         sc->bst = rman_get_bustag(sc->res[0]);
  235         sc->bsh = rman_get_bushandle(sc->res[0]);
  236 
  237         if (clk_get_by_ofw_name(dev, 0, "i2s", &sc->clk) != 0) {
  238                 device_printf(dev, "could not get i2s clock\n");
  239                 bus_release_resources(dev, codec_spec, sc->res);
  240                 return (ENXIO);
  241         }
  242 
  243         /* Initialize codec. */
  244         reg = codec_read(sc, CR_VIC);
  245         reg &= ~(VIC_SB_SLEEP | VIC_SB);
  246         codec_write(sc, CR_VIC, reg);
  247 
  248         DELAY(20000);
  249 
  250         reg = codec_read(sc, CR_DAC);
  251         reg &= ~(DAC_SB | DAC_MUTE);
  252         codec_write(sc, CR_DAC, reg);
  253 
  254         DELAY(10000);
  255 
  256         /* I2S, 16-bit, 48 kHz. */
  257         reg = codec_read(sc, AICR_DAC);
  258         reg &= ~(AICR_DAC_SB | DAC_ADWL_M);
  259         reg |= DAC_ADWL_16;
  260         reg &= ~(AUDIOIF_M);
  261         reg |= AUDIOIF_I2S;
  262         codec_write(sc, AICR_DAC, reg);
  263 
  264         DELAY(10000);
  265 
  266         reg = FCR_DAC_48;
  267         codec_write(sc, FCR_DAC, reg);
  268 
  269         DELAY(10000);
  270 
  271         /* Unmute headphones. */
  272         reg = codec_read(sc, CR_HP);
  273         reg &= ~(HP_SB | HP_MUTE);
  274         codec_write(sc, CR_HP, reg);
  275 
  276         ci20_hp_unmute(sc);
  277 
  278         return (0);
  279 }
  280 
  281 static int
  282 codec_detach(device_t dev)
  283 {
  284         struct codec_softc *sc;
  285 
  286         sc = device_get_softc(dev);
  287 
  288         bus_release_resources(dev, codec_spec, sc->res);
  289 
  290         return (0);
  291 }
  292 
  293 static device_method_t codec_methods[] = {
  294         /* Device interface */
  295         DEVMETHOD(device_probe,                 codec_probe),
  296         DEVMETHOD(device_attach,                codec_attach),
  297         DEVMETHOD(device_detach,                codec_detach),
  298 
  299         DEVMETHOD_END
  300 };
  301 
  302 static driver_t codec_driver = {
  303         "codec",
  304         codec_methods,
  305         sizeof(struct codec_softc),
  306 };
  307 
  308 static devclass_t codec_devclass;
  309 
  310 DRIVER_MODULE(codec, simplebus, codec_driver, codec_devclass, 0, 0);

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