The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/ingenic/jz4780_cpuregs.h

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    1 /*-
    2  * Copyright (c) 2015 Alexander Kabaev <kan@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   15  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   16  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   17  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   18  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   19  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   20  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   21  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   22  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   23  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   24  * POSSIBILITY OF SUCH DAMAGE.
   25  *
   26  * $FreeBSD: stable/12/sys/mips/ingenic/jz4780_cpuregs.h 308857 2016-11-19 17:46:18Z br $
   27  */
   28 
   29 #ifndef JZ4780_CPUREGS_H
   30 #define JZ4780_CPUREGS_H
   31 
   32 /* Core control register */
   33 #define JZ_CORECTL_SLP1M_SHIFT  17
   34 #define JZ_CORECTL_SLP1M        (1u << JZ_CORECTL_SLP1M_SHIFT)
   35 #define JZ_CORECTL_SLP0M_SHIFT  16
   36 #define JZ_CORECTL_SLP0M        (1u << JZ_CORECTL_SLP0M_SHIFT)
   37 #define JZ_CORECTL_RPC1_SHIFT   9
   38 #define JZ_CORECTL_RPC1         (1u << JZ_CORECTL_RPC1_SHIFT)
   39 #define JZ_CORECTL_RPC0_SHIFT   8
   40 #define JZ_CORECTL_RPC0         (1u << JZ_CORECTL_RPC0_SHIFT)
   41 #define JZ_CORECTL_SWRST1_SHIFT 1
   42 #define JZ_CORECTL_SWRST1       (1u << JZ_CORECTL_SWRST1_SHIFT)
   43 #define JZ_CORECTL_SWRST0_SHIFT 0
   44 #define JZ_CORECTL_SWRST0       (1u << JZ_CORECTL_SWRST0_SHIFT)
   45 
   46 /* Core status register */
   47 #define JZ_CORESTS_SLP1_SHIFT   17
   48 #define JZ_CORESTS_SLP1         (1u << JZ_CORESTS_SLP1_SHIFT)
   49 #define JZ_CORESTS_SLP0_SHIFT   16
   50 #define JZ_CORESTS_SLP0         (1u << JZ_CORESTS_SLP0_SHIFT)
   51 #define JZ_CORESTS_IRQ1P_SHIFT  9
   52 #define JZ_CORESTS_IRQ1P        (1u << JZ_CORESTS_IRQ1P_SHIFT)
   53 #define JZ_CORESTS_IRQ0P_SHIFT  8
   54 #define JZ_CORESTS_IRQ0P        (1u << JZ_CORESTS_IRQ0P_SHIFT)
   55 #define JZ_CORESTS_MIRQ1P_SHIFT 1
   56 #define JZ_CORESTS_MIRQ1P       (1u << JZ_CORESTS_MIRQ1P_SHIFT)
   57 #define JZ_CORESTS_MIRQ0P_SHIFT 0
   58 #define JZ_CORESTS_MIRQ0P       (1u << JZ_CORESTS_MIRQ0P_SHIFT)
   59 
   60 /* Reset entry and IRQ mask */
   61 #define JZ_REIM_ENTRY_SHIFT     16
   62 #define JZ_REIM_ENTRY_WIDTH     16
   63 #define JZ_REIM_ENTRY_MASK      (0xFFFFu << JZ_REIM_ENTRY_SHIFT)
   64 #define JZ_REIM_IRQ1M_SHIFT     9
   65 #define JZ_REIM_IRQ1M           (1u << JZ_REIM_IRQ1M_SHIFT)
   66 #define JZ_REIM_IRQ0M_SHIFT     8
   67 #define JZ_REIM_IRQ0M           (1u << JZ_REIM_IRQ0M_SHIFT)
   68 #define JZ_REIM_MIRQ1M_SHIFT    1
   69 #define JZ_REIM_MIRQ1M          (1u << JZ_REIM_MIRQ1M_SHIFT)
   70 #define JZ_REIM_MIRQ0M_SHIFT    0
   71 #define JZ_REIM_MIRQ0M          (1u << JZ_REIM_MIRQ0M_SHIFT)
   72 
   73 #endif /* JZ4780_CPUREGS_H */

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