The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/ingenic/jz4780_dwc_fdt.c

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    1 /*
    2  * Copyright 2015 Alexander Kabaev <kan@FreeBSD.org>.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions are
    7  * met:
    8  *
    9  *  1. Redistributions of source code must retain the above copyright
   10  *     notice, this list of conditions and the following disclaimer.
   11  *  2. Redistributions in binary form must reproduce the above copyright
   12  *     notice, this list of conditions and the following disclaimer in the
   13  *     documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   18  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
   19  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   20  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   21  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
   22  * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
   23  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
   24  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
   25  * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   26  */
   27 
   28 #include <sys/cdefs.h>
   29 __FBSDID("$FreeBSD: stable/12/sys/mips/ingenic/jz4780_dwc_fdt.c 308857 2016-11-19 17:46:18Z br $");
   30 
   31 #include <sys/param.h>
   32 #include <sys/kernel.h>
   33 #include <sys/bus.h>
   34 #include <sys/callout.h>
   35 #include <sys/condvar.h>
   36 #include <sys/module.h>
   37 
   38 #include <dev/extres/clk/clk.h>
   39 
   40 #include <dev/ofw/ofw_bus_subr.h>
   41 
   42 #include <dev/usb/usb.h>
   43 #include <dev/usb/usbdi.h>
   44 
   45 #include <dev/usb/usb_busdma.h>
   46 #include <dev/usb/usb_process.h>
   47 
   48 #include <dev/usb/usb_controller.h>
   49 #include <dev/usb/usb_bus.h>
   50 
   51 #include <dev/usb/controller/dwc_otg.h>
   52 #include <dev/usb/controller/dwc_otg_fdt.h>
   53 
   54 #include <mips/ingenic/jz4780_clock.h>
   55 #include <mips/ingenic/jz4780_regs.h>
   56 
   57 static device_probe_t jz4780_dwc_otg_probe;
   58 static device_attach_t jz4780_dwc_otg_attach;
   59 static device_detach_t jz4780_dwc_otg_detach;
   60 
   61 struct jz4780_dwc_otg_softc {
   62         struct dwc_otg_fdt_softc base;  /* storage for DWC OTG code */
   63         clk_t                   phy_clk;
   64         clk_t                   otg_clk;
   65 };
   66 
   67 static int
   68 jz4780_dwc_otg_clk_enable(device_t dev)
   69 {
   70         struct jz4780_dwc_otg_softc *sc;
   71         int err;
   72 
   73         sc = device_get_softc(dev);
   74 
   75         /* Configure and enable phy clock */
   76         err = clk_get_by_ofw_name(dev, 0, "otg_phy", &sc->phy_clk);
   77         if (err != 0) {
   78                 device_printf(dev, "unable to lookup %s clock\n", "otg_phy");
   79                 return (err);
   80         }
   81         err = clk_set_freq(sc->phy_clk, 48000000, 0);
   82         if (err != 0) {
   83                 device_printf(dev, "unable to set %s clock to 48 kHZ\n",
   84                     "otg_phy");
   85                 return (err);
   86         }
   87         err = clk_enable(sc->phy_clk);
   88         if (err != 0) {
   89                 device_printf(dev, "unable to enable %s clock\n", "otg_phy");
   90                 return (err);
   91         }
   92 
   93         /* Configure and enable otg1 clock */
   94         err = clk_get_by_ofw_name(dev, 0, "otg1", &sc->otg_clk);
   95         if (err != 0) {
   96                 device_printf(dev, "unable to lookup %s clock\n", "otg1");
   97                 return (err);
   98         }
   99         err = clk_enable(sc->phy_clk);
  100         if (err != 0) {
  101                 device_printf(dev, "unable to enable %s clock\n", "otg1");
  102                 return (err);
  103         }
  104 
  105         return (0);
  106 }
  107 
  108 static int
  109 jz4780_dwc_otg_probe(device_t dev)
  110 {
  111 
  112         if (!ofw_bus_status_okay(dev))
  113                 return (ENXIO);
  114 
  115         if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-otg"))
  116                 return (ENXIO);
  117 
  118         device_set_desc(dev, "DWC OTG 2.0 integrated USB controller (jz4780)");
  119 
  120         return (BUS_PROBE_VENDOR);
  121 }
  122 
  123 static int
  124 jz4780_dwc_otg_attach(device_t dev)
  125 {
  126         struct jz4780_dwc_otg_softc *sc;
  127         struct resource *res;
  128         int err, rid;
  129 
  130         sc = device_get_softc(dev);
  131 
  132         err = jz4780_dwc_otg_clk_enable(dev);
  133         if (err != 0)
  134                 goto fail;
  135 
  136         err = jz4780_otg_enable();
  137         if (err != 0) {
  138                 device_printf(dev, "CGU failed to enable OTG\n");
  139                 goto fail;
  140         }
  141 
  142         /* Voodoo: Switch off VBUS overcurrent detection in OTG PHY */
  143         res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
  144         if (res != NULL) {
  145                 uint32_t reg;
  146 
  147                 reg = bus_read_4(res, JZ_DWC2_GUSBCFG);
  148                 reg |= 0xc;
  149                 bus_write_4(res, JZ_DWC2_GUSBCFG, reg);
  150                 bus_release_resource(dev, SYS_RES_MEMORY, rid, res);
  151         }
  152 
  153         sc->base.sc_otg.sc_phy_type = DWC_OTG_PHY_UTMI;
  154         sc->base.sc_otg.sc_phy_bits = 16;
  155 
  156         err = dwc_otg_attach(dev);
  157         if (err != 0)
  158                 goto fail;
  159 
  160         return (0);
  161 fail:
  162         if (sc->otg_clk)
  163                 clk_release(sc->otg_clk);
  164         if (sc->phy_clk)
  165                 clk_release(sc->phy_clk);
  166         return (err);
  167 }
  168 
  169 static int
  170 jz4780_dwc_otg_detach(device_t dev)
  171 {
  172         struct jz4780_dwc_otg_softc *sc;
  173         int err;
  174 
  175         err = dwc_otg_detach(dev);
  176         if (err != 0)
  177                 return (err);
  178 
  179         sc = device_get_softc(dev);
  180         if (sc->otg_clk)
  181                 clk_release(sc->otg_clk);
  182         if (sc->phy_clk)
  183                 clk_release(sc->phy_clk);
  184         return (0);
  185 }
  186 
  187 static device_method_t jz4780_dwc_otg_methods[] = {
  188         /* bus interface */
  189         DEVMETHOD(device_probe, jz4780_dwc_otg_probe),
  190         DEVMETHOD(device_attach, jz4780_dwc_otg_attach),
  191         DEVMETHOD(device_detach, jz4780_dwc_otg_detach),
  192 
  193         DEVMETHOD_END
  194 };
  195 
  196 static devclass_t jz4780_dwc_otg_devclass;
  197 
  198 DEFINE_CLASS_1(jzotg, jz4780_dwc_otg_driver, jz4780_dwc_otg_methods,
  199     sizeof(struct jz4780_dwc_otg_softc), dwc_otg_driver);
  200 DRIVER_MODULE(jzotg, simplebus, jz4780_dwc_otg_driver,
  201     jz4780_dwc_otg_devclass, 0, 0);
  202 MODULE_DEPEND(jzotg, usb, 1, 1, 1);

Cache object: e6cbfcc171e536ed57d473ef5389db23


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