The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/ingenic/jz4780_mmc.c

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    1 /*-
    2  * Copyright (c) 2015 Alexander Kabaev <kan@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 #include <sys/cdefs.h>
   28 __FBSDID("$FreeBSD: stable/12/sys/mips/ingenic/jz4780_mmc.c 362344 2020-06-18 21:44:49Z manu $");
   29 
   30 #include <sys/param.h>
   31 #include <sys/systm.h>
   32 #include <sys/bus.h>
   33 #include <sys/kernel.h>
   34 #include <sys/lock.h>
   35 #include <sys/malloc.h>
   36 #include <sys/module.h>
   37 #include <sys/mutex.h>
   38 #include <sys/resource.h>
   39 #include <sys/rman.h>
   40 #include <sys/sysctl.h>
   41 
   42 #include <machine/bus.h>
   43 
   44 #include <dev/extres/clk/clk.h>
   45 
   46 #include <dev/ofw/ofw_bus.h>
   47 #include <dev/ofw/ofw_bus_subr.h>
   48 
   49 #include <dev/mmc/bridge.h>
   50 #include <dev/mmc/mmcreg.h>
   51 #include <dev/mmc/mmcbrvar.h>
   52 
   53 #include <mips/ingenic/jz4780_regs.h>
   54 
   55 #undef JZ_MMC_DEBUG
   56 
   57 #define JZ_MSC_MEMRES           0
   58 #define JZ_MSC_IRQRES           1
   59 #define JZ_MSC_RESSZ            2
   60 #define JZ_MSC_DMA_SEGS         128
   61 #define JZ_MSC_DMA_MAX_SIZE     MAXPHYS
   62 
   63 #define JZ_MSC_INT_ERR_BITS     (JZ_INT_CRC_RES_ERR | JZ_INT_CRC_READ_ERR | \
   64                                 JZ_INT_CRC_WRITE_ERR | JZ_INT_TIMEOUT_RES | \
   65                                 JZ_INT_TIMEOUT_READ)
   66 static int jz4780_mmc_pio_mode = 0;
   67 
   68 TUNABLE_INT("hw.jz.mmc.pio_mode", &jz4780_mmc_pio_mode);
   69 
   70 struct jz4780_mmc_dma_desc {
   71         uint32_t                dma_next;
   72         uint32_t                dma_phys;
   73         uint32_t                dma_len;
   74         uint32_t                dma_cmd;
   75 };
   76 
   77 struct jz4780_mmc_softc {
   78         bus_space_handle_t      sc_bsh;
   79         bus_space_tag_t         sc_bst;
   80         device_t                sc_dev;
   81         clk_t                   sc_clk;
   82         int                     sc_bus_busy;
   83         int                     sc_resid;
   84         int                     sc_timeout;
   85         struct callout          sc_timeoutc;
   86         struct mmc_host         sc_host;
   87         struct mmc_request *    sc_req;
   88         struct mtx              sc_mtx;
   89         struct resource *       sc_res[JZ_MSC_RESSZ];
   90         uint32_t                sc_intr_seen;
   91         uint32_t                sc_intr_mask;
   92         uint32_t                sc_intr_wait;
   93         void *                  sc_intrhand;
   94         uint32_t                sc_cmdat;
   95 
   96         /* Fields required for DMA access. */
   97         bus_addr_t              sc_dma_desc_phys;
   98         bus_dmamap_t            sc_dma_map;
   99         bus_dma_tag_t           sc_dma_tag;
  100         void *                  sc_dma_desc;
  101         bus_dmamap_t            sc_dma_buf_map;
  102         bus_dma_tag_t           sc_dma_buf_tag;
  103         int                     sc_dma_inuse;
  104         int                     sc_dma_map_err;
  105         uint32_t                sc_dma_ctl;
  106 };
  107 
  108 static struct resource_spec jz4780_mmc_res_spec[] = {
  109         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  110         { SYS_RES_IRQ,          0,      RF_ACTIVE | RF_SHAREABLE },
  111         { -1,                   0,      0 }
  112 };
  113 
  114 static int jz4780_mmc_probe(device_t);
  115 static int jz4780_mmc_attach(device_t);
  116 static int jz4780_mmc_detach(device_t);
  117 static int jz4780_mmc_setup_dma(struct jz4780_mmc_softc *);
  118 static int jz4780_mmc_reset(struct jz4780_mmc_softc *);
  119 static void jz4780_mmc_intr(void *);
  120 static int jz4780_mmc_enable_clock(struct jz4780_mmc_softc *);
  121 static int jz4780_mmc_config_clock(struct jz4780_mmc_softc *, uint32_t);
  122 
  123 static int jz4780_mmc_update_ios(device_t, device_t);
  124 static int jz4780_mmc_request(device_t, device_t, struct mmc_request *);
  125 static int jz4780_mmc_get_ro(device_t, device_t);
  126 static int jz4780_mmc_acquire_host(device_t, device_t);
  127 static int jz4780_mmc_release_host(device_t, device_t);
  128 
  129 #define JZ_MMC_LOCK(_sc)        mtx_lock(&(_sc)->sc_mtx)
  130 #define JZ_MMC_UNLOCK(_sc)      mtx_unlock(&(_sc)->sc_mtx)
  131 #define JZ_MMC_READ_2(_sc, _reg)                                        \
  132         bus_space_read_2((_sc)->sc_bst, (_sc)->sc_bsh, _reg)
  133 #define JZ_MMC_WRITE_2(_sc, _reg, _value)                               \
  134         bus_space_write_2((_sc)->sc_bst, (_sc)->sc_bsh, _reg, _value)
  135 #define JZ_MMC_READ_4(_sc, _reg)                                        \
  136         bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _reg)
  137 #define JZ_MMC_WRITE_4(_sc, _reg, _value)                               \
  138         bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _reg, _value)
  139 
  140 static int
  141 jz4780_mmc_probe(device_t dev)
  142 {
  143 
  144         if (!ofw_bus_status_okay(dev))
  145                 return (ENXIO);
  146         if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-mmc"))
  147                 return (ENXIO);
  148         if (device_get_unit(dev) > 0) /* XXXKAN */
  149                 return (ENXIO);
  150         device_set_desc(dev, "Ingenic JZ4780 Integrated MMC/SD controller");
  151 
  152         return (BUS_PROBE_DEFAULT);
  153 }
  154 
  155 static int
  156 jz4780_mmc_attach(device_t dev)
  157 {
  158         struct jz4780_mmc_softc *sc;
  159         struct sysctl_ctx_list *ctx;
  160         struct sysctl_oid_list *tree;
  161         device_t child;
  162         ssize_t len;
  163         pcell_t prop;
  164         phandle_t node;
  165 
  166         sc = device_get_softc(dev);
  167         sc->sc_dev = dev;
  168         sc->sc_req = NULL;
  169         if (bus_alloc_resources(dev, jz4780_mmc_res_spec, sc->sc_res) != 0) {
  170                 device_printf(dev, "cannot allocate device resources\n");
  171                 return (ENXIO);
  172         }
  173         sc->sc_bst = rman_get_bustag(sc->sc_res[JZ_MSC_MEMRES]);
  174         sc->sc_bsh = rman_get_bushandle(sc->sc_res[JZ_MSC_MEMRES]);
  175         if (bus_setup_intr(dev, sc->sc_res[JZ_MSC_IRQRES],
  176             INTR_TYPE_MISC | INTR_MPSAFE, NULL, jz4780_mmc_intr, sc,
  177             &sc->sc_intrhand)) {
  178                 bus_release_resources(dev, jz4780_mmc_res_spec, sc->sc_res);
  179                 device_printf(dev, "cannot setup interrupt handler\n");
  180                 return (ENXIO);
  181         }
  182         sc->sc_timeout = 10;
  183         ctx = device_get_sysctl_ctx(dev);
  184         tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
  185         SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
  186             &sc->sc_timeout, 0, "Request timeout in seconds");
  187         mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), "jz4780_mmc",
  188             MTX_DEF);
  189         callout_init_mtx(&sc->sc_timeoutc, &sc->sc_mtx, 0);
  190 
  191         /* Reset controller. */
  192         if (jz4780_mmc_reset(sc) != 0) {
  193                 device_printf(dev, "cannot reset the controller\n");
  194                 goto fail;
  195         }
  196         if (jz4780_mmc_pio_mode == 0 && jz4780_mmc_setup_dma(sc) != 0) {
  197                 device_printf(sc->sc_dev, "Couldn't setup DMA!\n");
  198                 jz4780_mmc_pio_mode = 1;
  199         }
  200         if (bootverbose)
  201                 device_printf(sc->sc_dev, "DMA status: %s\n",
  202                     jz4780_mmc_pio_mode ? "disabled" : "enabled");
  203 
  204         node = ofw_bus_get_node(dev);
  205         /* Determine max operating frequency */
  206         sc->sc_host.f_max = 24000000;
  207         len = OF_getencprop(node, "max-frequency", &prop, sizeof(prop));
  208         if (len / sizeof(prop) == 1)
  209                 sc->sc_host.f_max = prop;
  210         sc->sc_host.f_min = sc->sc_host.f_max / 128;
  211 
  212         sc->sc_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
  213         sc->sc_host.caps = MMC_CAP_HSPEED;
  214         sc->sc_host.mode = mode_sd;
  215         /*
  216          * Check for bus-width property, default to both 4 and 8 bit
  217          * if no bus width is specified.
  218          */
  219         len = OF_getencprop(node, "bus-width", &prop, sizeof(prop));
  220         if (len / sizeof(prop) != 1)
  221                 sc->sc_host.caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
  222         else if (prop == 8)
  223                 sc->sc_host.caps |= MMC_CAP_8_BIT_DATA;
  224         else if (prop == 4)
  225                 sc->sc_host.caps |= MMC_CAP_4_BIT_DATA;
  226         /* Activate the module clock. */
  227         if (jz4780_mmc_enable_clock(sc) != 0) {
  228                 device_printf(dev, "cannot activate mmc clock\n");
  229                 goto fail;
  230         }
  231 
  232         child = device_add_child(dev, "mmc", -1);
  233         if (child == NULL) {
  234                 device_printf(dev, "attaching MMC bus failed!\n");
  235                 goto fail;
  236         }
  237         if (device_probe_and_attach(child) != 0) {
  238                 device_printf(dev, "attaching MMC child failed!\n");
  239                 device_delete_child(dev, child);
  240                 goto fail;
  241         }
  242 
  243         return (0);
  244 
  245 fail:
  246         callout_drain(&sc->sc_timeoutc);
  247         mtx_destroy(&sc->sc_mtx);
  248         bus_teardown_intr(dev, sc->sc_res[JZ_MSC_IRQRES], sc->sc_intrhand);
  249         bus_release_resources(dev, jz4780_mmc_res_spec, sc->sc_res);
  250         if (sc->sc_clk != NULL)
  251                 clk_release(sc->sc_clk);
  252         return (ENXIO);
  253 }
  254 
  255 static int
  256 jz4780_mmc_detach(device_t dev)
  257 {
  258 
  259         return (EBUSY);
  260 }
  261 
  262 static int
  263 jz4780_mmc_enable_clock(struct jz4780_mmc_softc *sc)
  264 {
  265         int err;
  266 
  267         err = clk_get_by_ofw_name(sc->sc_dev, 0, "mmc", &sc->sc_clk);
  268         if (err == 0)
  269                 err = clk_enable(sc->sc_clk);
  270         if (err == 0)
  271                 err = clk_set_freq(sc->sc_clk, sc->sc_host.f_max, 0);
  272         if (err != 0)
  273                 clk_release(sc->sc_clk);
  274         return (err);
  275 }
  276 
  277 static void
  278 jz4780_mmc_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
  279 {
  280         struct jz4780_mmc_softc *sc;
  281 
  282         sc = (struct jz4780_mmc_softc *)arg;
  283         if (err) {
  284                 sc->sc_dma_map_err = err;
  285                 return;
  286         }
  287         sc->sc_dma_desc_phys = segs[0].ds_addr;
  288 }
  289 
  290 static int
  291 jz4780_mmc_setup_dma(struct jz4780_mmc_softc *sc)
  292 {
  293         int dma_desc_size, error;
  294 
  295         /* Allocate the DMA descriptor memory. */
  296         dma_desc_size = sizeof(struct jz4780_mmc_dma_desc) * JZ_MSC_DMA_SEGS;
  297         error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
  298             BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
  299             dma_desc_size, 1, dma_desc_size, 0, NULL, NULL, &sc->sc_dma_tag);
  300         if (error)
  301                 return (error);
  302         error = bus_dmamem_alloc(sc->sc_dma_tag, &sc->sc_dma_desc,
  303             BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->sc_dma_map);
  304         if (error)
  305                 return (error);
  306 
  307         error = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
  308             sc->sc_dma_desc, dma_desc_size, jz4780_mmc_dma_desc_cb, sc, 0);
  309         if (error)
  310                 return (error);
  311         if (sc->sc_dma_map_err)
  312                 return (sc->sc_dma_map_err);
  313 
  314         /* Create the DMA map for data transfers. */
  315         error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
  316             BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
  317             JZ_MSC_DMA_MAX_SIZE * JZ_MSC_DMA_SEGS, JZ_MSC_DMA_SEGS,
  318             JZ_MSC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL,
  319             &sc->sc_dma_buf_tag);
  320         if (error)
  321                 return (error);
  322         error = bus_dmamap_create(sc->sc_dma_buf_tag, 0,
  323             &sc->sc_dma_buf_map);
  324         if (error)
  325                 return (error);
  326 
  327         return (0);
  328 }
  329 
  330 static void
  331 jz4780_mmc_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
  332 {
  333         struct jz4780_mmc_dma_desc *dma_desc;
  334         struct jz4780_mmc_softc *sc;
  335         uint32_t dma_desc_phys;
  336         int i;
  337 
  338         sc = (struct jz4780_mmc_softc *)arg;
  339         sc->sc_dma_map_err = err;
  340         dma_desc = sc->sc_dma_desc;
  341         dma_desc_phys = sc->sc_dma_desc_phys;
  342 
  343         /* Note nsegs is guaranteed to be zero if err is non-zero. */
  344         for (i = 0; i < nsegs; i++) {
  345                 dma_desc[i].dma_phys = segs[i].ds_addr;
  346                 dma_desc[i].dma_len  = segs[i].ds_len;
  347                 if (i < (nsegs - 1)) {
  348                         dma_desc_phys += sizeof(struct jz4780_mmc_dma_desc);
  349                         dma_desc[i].dma_next = dma_desc_phys;
  350                         dma_desc[i].dma_cmd = (i << 16) | JZ_DMA_LINK;
  351                 } else {
  352                         dma_desc[i].dma_next = 0;
  353                         dma_desc[i].dma_cmd = (i << 16) | JZ_DMA_ENDI;
  354                 }
  355 #ifdef JZ_MMC_DEBUG
  356                 device_printf(sc->sc_dev, "%d: desc %#x phys %#x len %d next %#x cmd %#x\n",
  357                     i, dma_desc_phys - sizeof(struct jz4780_mmc_dma_desc),
  358                     dma_desc[i].dma_phys, dma_desc[i].dma_len,
  359                     dma_desc[i].dma_next, dma_desc[i].dma_cmd);
  360 #endif
  361         }
  362 }
  363 
  364 static int
  365 jz4780_mmc_prepare_dma(struct jz4780_mmc_softc *sc)
  366 {
  367         bus_dmasync_op_t sync_op;
  368         int error;
  369         struct mmc_command *cmd;
  370         uint32_t off;
  371 
  372         cmd = sc->sc_req->cmd;
  373         if (cmd->data->len > JZ_MSC_DMA_MAX_SIZE * JZ_MSC_DMA_SEGS)
  374                 return (EFBIG);
  375         error = bus_dmamap_load(sc->sc_dma_buf_tag, sc->sc_dma_buf_map,
  376             cmd->data->data, cmd->data->len, jz4780_mmc_dma_cb, sc,
  377             BUS_DMA_NOWAIT);
  378         if (error)
  379                 return (error);
  380         if (sc->sc_dma_map_err)
  381                 return (sc->sc_dma_map_err);
  382 
  383         sc->sc_dma_inuse = 1;
  384         if (cmd->data->flags & MMC_DATA_WRITE)
  385                 sync_op = BUS_DMASYNC_PREWRITE;
  386         else
  387                 sync_op = BUS_DMASYNC_PREREAD;
  388         bus_dmamap_sync(sc->sc_dma_buf_tag, sc->sc_dma_buf_map, sync_op);
  389         bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, BUS_DMASYNC_PREWRITE);
  390 
  391         /* Configure default DMA parameters */
  392         sc->sc_dma_ctl = JZ_MODE_SEL | JZ_INCR_64 | JZ_DMAEN;
  393 
  394         /* Enable unaligned buffer handling */
  395         off = (uintptr_t)cmd->data->data & 3;
  396         if (off != 0)
  397                 sc->sc_dma_ctl |= (off << JZ_AOFST_S) | JZ_ALIGNEN;
  398         return (0);
  399 }
  400 
  401 static void
  402 jz4780_mmc_start_dma(struct jz4780_mmc_softc *sc)
  403 {
  404 
  405         /* Set the address of the first descriptor */
  406         JZ_MMC_WRITE_4(sc, JZ_MSC_DMANDA, sc->sc_dma_desc_phys);
  407         /* Enable and start the dma engine */
  408         JZ_MMC_WRITE_4(sc, JZ_MSC_DMAC, sc->sc_dma_ctl);
  409 }
  410 
  411 static int
  412 jz4780_mmc_reset(struct jz4780_mmc_softc *sc)
  413 {
  414         int timeout;
  415 
  416         /* Stop the clock */
  417         JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL, JZ_CLOCK_STOP);
  418 
  419         timeout = 1000;
  420         while (--timeout > 0) {
  421                 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & JZ_CLK_EN) == 0)
  422                         break;
  423                 DELAY(100);
  424         }
  425         if (timeout == 0) {
  426                 device_printf(sc->sc_dev, "Failed to stop clk.\n");
  427                 return (ETIMEDOUT);
  428         }
  429 
  430         /* Reset */
  431         JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL, JZ_RESET);
  432 
  433         timeout = 10;
  434         while (--timeout > 0) {
  435                 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & JZ_IS_RESETTING) == 0)
  436                         break;
  437                 DELAY(1000);
  438         }
  439 
  440         if (timeout == 0) {
  441                 /*
  442                  * X1000 never clears reseting bit.
  443                  * Ignore for now.
  444                  */
  445         }
  446 
  447         /* Set the timeouts. */
  448         JZ_MMC_WRITE_4(sc, JZ_MSC_RESTO, 0xffff);
  449         JZ_MMC_WRITE_4(sc, JZ_MSC_RDTO, 0xffffffff);
  450 
  451         /* Mask all interrupt initially */
  452         JZ_MMC_WRITE_4(sc, JZ_MSC_IMASK, 0xffffffff);
  453         /* Clear pending interrupts. */
  454         JZ_MMC_WRITE_4(sc, JZ_MSC_IFLG, 0xffffffff);
  455 
  456         /* Remember interrupts we always want */
  457         sc->sc_intr_mask = JZ_MSC_INT_ERR_BITS;
  458 
  459         return (0);
  460 }
  461 
  462 static void
  463 jz4780_mmc_req_done(struct jz4780_mmc_softc *sc)
  464 {
  465         struct mmc_command *cmd;
  466         struct mmc_request *req;
  467         bus_dmasync_op_t sync_op;
  468 
  469         cmd = sc->sc_req->cmd;
  470         /* Reset the controller in case of errors */
  471         if (cmd->error != MMC_ERR_NONE)
  472                 jz4780_mmc_reset(sc);
  473         /* Unmap DMA if necessary */
  474         if (sc->sc_dma_inuse == 1) {
  475                 if (cmd->data->flags & MMC_DATA_WRITE)
  476                         sync_op = BUS_DMASYNC_POSTWRITE;
  477                 else
  478                         sync_op = BUS_DMASYNC_POSTREAD;
  479                 bus_dmamap_sync(sc->sc_dma_buf_tag, sc->sc_dma_buf_map,
  480                     sync_op);
  481                 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
  482                     BUS_DMASYNC_POSTWRITE);
  483                 bus_dmamap_unload(sc->sc_dma_buf_tag, sc->sc_dma_buf_map);
  484         }
  485         req = sc->sc_req;
  486         callout_stop(&sc->sc_timeoutc);
  487         sc->sc_req = NULL;
  488         sc->sc_resid = 0;
  489         sc->sc_dma_inuse = 0;
  490         sc->sc_dma_map_err = 0;
  491         sc->sc_intr_wait = 0;
  492         sc->sc_intr_seen = 0;
  493         req->done(req);
  494 }
  495 
  496 static void
  497 jz4780_mmc_read_response(struct jz4780_mmc_softc *sc)
  498 {
  499         struct mmc_command *cmd;
  500         int i;
  501 
  502         cmd = sc->sc_req->cmd;
  503         if (cmd->flags & MMC_RSP_PRESENT) {
  504                 if (cmd->flags & MMC_RSP_136) {
  505                         uint16_t val;
  506 
  507                         val = JZ_MMC_READ_2(sc, JZ_MSC_RES);
  508                         for (i = 0; i < 4; i++) {
  509                                 cmd->resp[i] = val << 24;
  510                                 val = JZ_MMC_READ_2(sc, JZ_MSC_RES);
  511                                 cmd->resp[i] |= val << 8;
  512                                 val = JZ_MMC_READ_2(sc, JZ_MSC_RES);
  513                                 cmd->resp[i] |= val >> 8;
  514                         }
  515                 } else {
  516                         cmd->resp[0] = JZ_MMC_READ_2(sc, JZ_MSC_RES) << 24;
  517                         cmd->resp[0] |= JZ_MMC_READ_2(sc, JZ_MSC_RES) << 8;
  518                         cmd->resp[0] |= JZ_MMC_READ_2(sc, JZ_MSC_RES) & 0xff;
  519                 }
  520         }
  521 }
  522 
  523 static void
  524 jz4780_mmc_req_ok(struct jz4780_mmc_softc *sc)
  525 {
  526         struct mmc_command *cmd;
  527 
  528         cmd = sc->sc_req->cmd;
  529         /* All data has been transferred ? */
  530         if (cmd->data != NULL && (sc->sc_resid << 2) < cmd->data->len)
  531                 cmd->error = MMC_ERR_FAILED;
  532         jz4780_mmc_req_done(sc);
  533 }
  534 
  535 static void
  536 jz4780_mmc_timeout(void *arg)
  537 {
  538         struct jz4780_mmc_softc *sc;
  539 
  540         sc = (struct jz4780_mmc_softc *)arg;
  541         if (sc->sc_req != NULL) {
  542                 device_printf(sc->sc_dev, "controller timeout, rint %#x stat %#x\n",
  543                     JZ_MMC_READ_4(sc, JZ_MSC_IFLG), JZ_MMC_READ_4(sc, JZ_MSC_STAT));
  544                 sc->sc_req->cmd->error = MMC_ERR_TIMEOUT;
  545                 jz4780_mmc_req_done(sc);
  546         } else
  547                 device_printf(sc->sc_dev,
  548                     "Spurious timeout - no active request\n");
  549 }
  550 
  551 static int
  552 jz4780_mmc_pio_transfer(struct jz4780_mmc_softc *sc, struct mmc_data *data)
  553 {
  554         uint32_t mask, *buf;
  555         int i, write;
  556 
  557         buf = (uint32_t *)data->data;
  558         write = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
  559         mask = write ? JZ_DATA_FIFO_FULL : JZ_DATA_FIFO_EMPTY;
  560         for (i = sc->sc_resid; i < (data->len >> 2); i++) {
  561                 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & mask))
  562                         return (1);
  563                 if (write)
  564                         JZ_MMC_WRITE_4(sc, JZ_MSC_TXFIFO, buf[i]);
  565                 else
  566                         buf[i] = JZ_MMC_READ_4(sc, JZ_MSC_RXFIFO);
  567                 sc->sc_resid = i + 1;
  568         }
  569 
  570         /* Done with pio transfer, shut FIFO interrupts down */
  571         mask = JZ_MMC_READ_4(sc, JZ_MSC_IMASK);
  572         mask |= (JZ_INT_TXFIFO_WR_REQ | JZ_INT_RXFIFO_RD_REQ);
  573         JZ_MMC_WRITE_4(sc, JZ_MSC_IMASK, mask);
  574         return (0);
  575 }
  576 
  577 static void
  578 jz4780_mmc_intr(void *arg)
  579 {
  580         struct jz4780_mmc_softc *sc;
  581         struct mmc_data *data;
  582         uint32_t rint;
  583 
  584         sc = (struct jz4780_mmc_softc *)arg;
  585         JZ_MMC_LOCK(sc);
  586         rint  = JZ_MMC_READ_4(sc, JZ_MSC_IFLG);
  587 #if defined(JZ_MMC_DEBUG)
  588         device_printf(sc->sc_dev, "rint: %#x, stat: %#x\n",
  589             rint, JZ_MMC_READ_4(sc, JZ_MSC_STAT));
  590         if (sc->sc_dma_inuse == 1 && (sc->sc_intr_seen & JZ_INT_DMAEND) == 0)
  591                 device_printf(sc->sc_dev, "\tdmada %#x dmanext %#x dmac %#x"
  592                     " dmalen %d dmacmd %#x\n",
  593                     JZ_MMC_READ_4(sc, JZ_MSC_DMADA),
  594                     JZ_MMC_READ_4(sc, JZ_MSC_DMANDA),
  595                     JZ_MMC_READ_4(sc, JZ_MSC_DMAC),
  596                     JZ_MMC_READ_4(sc, JZ_MSC_DMALEN),
  597                     JZ_MMC_READ_4(sc, JZ_MSC_DMACMD));
  598 #endif
  599         if (sc->sc_req == NULL) {
  600                 device_printf(sc->sc_dev,
  601                     "Spurious interrupt - no active request, rint: 0x%08X\n",
  602                     rint);
  603                 goto end;
  604         }
  605         if (rint & JZ_MSC_INT_ERR_BITS) {
  606 #if defined(JZ_MMC_DEBUG)
  607                 device_printf(sc->sc_dev, "controller error, rint %#x stat %#x\n",
  608                     rint,  JZ_MMC_READ_4(sc, JZ_MSC_STAT));
  609 #endif
  610                 if (rint & (JZ_INT_TIMEOUT_RES | JZ_INT_TIMEOUT_READ))
  611                         sc->sc_req->cmd->error = MMC_ERR_TIMEOUT;
  612                 else
  613                         sc->sc_req->cmd->error = MMC_ERR_FAILED;
  614                 jz4780_mmc_req_done(sc);
  615                 goto end;
  616         }
  617         data = sc->sc_req->cmd->data;
  618         /* Check for command response */
  619         if (rint & JZ_INT_END_CMD_RES) {
  620                 jz4780_mmc_read_response(sc);
  621                 if (sc->sc_dma_inuse == 1)
  622                         jz4780_mmc_start_dma(sc);
  623         }
  624         if (data != NULL) {
  625                 if (sc->sc_dma_inuse == 1 && (rint & JZ_INT_DMAEND))
  626                         sc->sc_resid = data->len >> 2;
  627                 else if (sc->sc_dma_inuse == 0 &&
  628                     (rint & (JZ_INT_TXFIFO_WR_REQ | JZ_INT_RXFIFO_RD_REQ)))
  629                         jz4780_mmc_pio_transfer(sc, data);
  630         }
  631         sc->sc_intr_seen |= rint;
  632         if ((sc->sc_intr_seen & sc->sc_intr_wait) == sc->sc_intr_wait)
  633                 jz4780_mmc_req_ok(sc);
  634 end:
  635         JZ_MMC_WRITE_4(sc, JZ_MSC_IFLG, rint);
  636         JZ_MMC_UNLOCK(sc);
  637 }
  638 
  639 static int
  640 jz4780_mmc_request(device_t bus, device_t child, struct mmc_request *req)
  641 {
  642         struct jz4780_mmc_softc *sc;
  643         struct mmc_command *cmd;
  644         uint32_t cmdat, iwait;
  645         int blksz;
  646 
  647         sc = device_get_softc(bus);
  648         JZ_MMC_LOCK(sc);
  649         if (sc->sc_req != NULL) {
  650                 JZ_MMC_UNLOCK(sc);
  651                 return (EBUSY);
  652         }
  653         /* Start with template value */
  654         cmdat = sc->sc_cmdat;
  655         iwait = JZ_INT_END_CMD_RES;
  656 
  657         /* Configure response format */
  658         cmd = req->cmd;
  659         switch (MMC_RSP(cmd->flags)) {
  660         case MMC_RSP_R1:
  661         case MMC_RSP_R1B:
  662                 cmdat |= JZ_RES_R1;
  663                 break;
  664         case MMC_RSP_R2:
  665                 cmdat |= JZ_RES_R2;
  666                 break;
  667         case MMC_RSP_R3:
  668                 cmdat |= JZ_RES_R3;
  669                 break;
  670         };
  671         if (cmd->opcode == MMC_GO_IDLE_STATE)
  672                 cmdat |= JZ_INIT;
  673         if (cmd->flags & MMC_RSP_BUSY) {
  674                 cmdat |= JZ_BUSY;
  675                 iwait |= JZ_INT_PRG_DONE;
  676         }
  677 
  678         sc->sc_req = req;
  679         sc->sc_resid = 0;
  680         cmd->error = MMC_ERR_NONE;
  681 
  682         if (cmd->data != NULL) {
  683                 cmdat |= JZ_DATA_EN;
  684                 if (cmd->data->flags & MMC_DATA_MULTI) {
  685                         cmdat |= JZ_AUTO_CMD12;
  686                         iwait |= JZ_INT_AUTO_CMD12_DONE;
  687                 }
  688                 if (cmd->data->flags & MMC_DATA_WRITE) {
  689                         cmdat |= JZ_WRITE;
  690                         iwait |= JZ_INT_PRG_DONE;
  691                 }
  692                 if (cmd->data->flags & MMC_DATA_STREAM)
  693                         cmdat |= JZ_STREAM;
  694                 else
  695                         iwait |= JZ_INT_DATA_TRAN_DONE;
  696 
  697                 blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
  698                 JZ_MMC_WRITE_4(sc, JZ_MSC_BLKLEN, blksz);
  699                 JZ_MMC_WRITE_4(sc, JZ_MSC_NOB, cmd->data->len / blksz);
  700 
  701                 /* Attempt to setup DMA for this transaction */
  702                 if (jz4780_mmc_pio_mode == 0)
  703                         jz4780_mmc_prepare_dma(sc);
  704                 if (sc->sc_dma_inuse != 0) {
  705                         /* Wait for DMA completion interrupt */
  706                         iwait |= JZ_INT_DMAEND;
  707                 } else {
  708                         iwait |= (cmd->data->flags & MMC_DATA_WRITE) ?
  709                             JZ_INT_TXFIFO_WR_REQ : JZ_INT_RXFIFO_RD_REQ;
  710                         JZ_MMC_WRITE_4(sc, JZ_MSC_DMAC, 0);
  711                 }
  712         }
  713 
  714         sc->sc_intr_seen = 0;
  715         sc->sc_intr_wait = iwait;
  716         JZ_MMC_WRITE_4(sc, JZ_MSC_IMASK, ~(sc->sc_intr_mask | iwait));
  717 
  718 #if defined(JZ_MMC_DEBUG)
  719         device_printf(sc->sc_dev,
  720             "REQUEST: CMD%u arg %#x flags %#x cmdat %#x sc_intr_wait = %#x\n",
  721             cmd->opcode, cmd->arg, cmd->flags, cmdat, sc->sc_intr_wait);
  722 #endif
  723 
  724         JZ_MMC_WRITE_4(sc, JZ_MSC_ARG, cmd->arg);
  725         JZ_MMC_WRITE_4(sc, JZ_MSC_CMD, cmd->opcode);
  726         JZ_MMC_WRITE_4(sc, JZ_MSC_CMDAT, cmdat);
  727 
  728         JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL, JZ_START_OP | JZ_CLOCK_START);
  729 
  730         callout_reset(&sc->sc_timeoutc, sc->sc_timeout * hz,
  731             jz4780_mmc_timeout, sc);
  732         JZ_MMC_UNLOCK(sc);
  733 
  734         return (0);
  735 }
  736 
  737 static int
  738 jz4780_mmc_read_ivar(device_t bus, device_t child, int which,
  739     uintptr_t *result)
  740 {
  741         struct jz4780_mmc_softc *sc;
  742 
  743         sc = device_get_softc(bus);
  744         switch (which) {
  745         default:
  746                 return (EINVAL);
  747         case MMCBR_IVAR_BUS_MODE:
  748                 *(int *)result = sc->sc_host.ios.bus_mode;
  749                 break;
  750         case MMCBR_IVAR_BUS_WIDTH:
  751                 *(int *)result = sc->sc_host.ios.bus_width;
  752                 break;
  753         case MMCBR_IVAR_CHIP_SELECT:
  754                 *(int *)result = sc->sc_host.ios.chip_select;
  755                 break;
  756         case MMCBR_IVAR_CLOCK:
  757                 *(int *)result = sc->sc_host.ios.clock;
  758                 break;
  759         case MMCBR_IVAR_F_MIN:
  760                 *(int *)result = sc->sc_host.f_min;
  761                 break;
  762         case MMCBR_IVAR_F_MAX:
  763                 *(int *)result = sc->sc_host.f_max;
  764                 break;
  765         case MMCBR_IVAR_HOST_OCR:
  766                 *(int *)result = sc->sc_host.host_ocr;
  767                 break;
  768         case MMCBR_IVAR_MODE:
  769                 *(int *)result = sc->sc_host.mode;
  770                 break;
  771         case MMCBR_IVAR_OCR:
  772                 *(int *)result = sc->sc_host.ocr;
  773                 break;
  774         case MMCBR_IVAR_POWER_MODE:
  775                 *(int *)result = sc->sc_host.ios.power_mode;
  776                 break;
  777         case MMCBR_IVAR_RETUNE_REQ:
  778                 *(int *)result = return_req_none;
  779                 break;
  780         case MMCBR_IVAR_VDD:
  781                 *(int *)result = sc->sc_host.ios.vdd;
  782                 break;
  783         case MMCBR_IVAR_VCCQ:
  784                 *result = sc->sc_host.ios.vccq;
  785                 break;
  786         case MMCBR_IVAR_CAPS:
  787                 *(int *)result = sc->sc_host.caps;
  788                 break;
  789         case MMCBR_IVAR_TIMING:
  790                 *(int *)result = sc->sc_host.ios.timing;
  791                 break;
  792         case MMCBR_IVAR_MAX_DATA:
  793                 *(int *)result = 65535;
  794                 break;
  795         case MMCBR_IVAR_MAX_BUSY_TIMEOUT:
  796                 *(int *)result = 1000000;       /* 1s max */
  797                 break;
  798         }
  799 
  800         return (0);
  801 }
  802 
  803 static int
  804 jz4780_mmc_write_ivar(device_t bus, device_t child, int which,
  805     uintptr_t value)
  806 {
  807         struct jz4780_mmc_softc *sc;
  808 
  809         sc = device_get_softc(bus);
  810         switch (which) {
  811         default:
  812                 return (EINVAL);
  813         case MMCBR_IVAR_BUS_MODE:
  814                 sc->sc_host.ios.bus_mode = value;
  815                 break;
  816         case MMCBR_IVAR_BUS_WIDTH:
  817                 sc->sc_host.ios.bus_width = value;
  818                 break;
  819         case MMCBR_IVAR_CHIP_SELECT:
  820                 sc->sc_host.ios.chip_select = value;
  821                 break;
  822         case MMCBR_IVAR_CLOCK:
  823                 sc->sc_host.ios.clock = value;
  824                 break;
  825         case MMCBR_IVAR_MODE:
  826                 sc->sc_host.mode = value;
  827                 break;
  828         case MMCBR_IVAR_OCR:
  829                 sc->sc_host.ocr = value;
  830                 break;
  831         case MMCBR_IVAR_POWER_MODE:
  832                 sc->sc_host.ios.power_mode = value;
  833                 break;
  834         case MMCBR_IVAR_VDD:
  835                 sc->sc_host.ios.vdd = value;
  836                 break;
  837         case MMCBR_IVAR_VCCQ:
  838                 sc->sc_host.ios.vccq = value;
  839                 break;
  840         case MMCBR_IVAR_TIMING:
  841                 sc->sc_host.ios.timing = value;
  842                 break;
  843         /* These are read-only */
  844         case MMCBR_IVAR_CAPS:
  845         case MMCBR_IVAR_HOST_OCR:
  846         case MMCBR_IVAR_F_MIN:
  847         case MMCBR_IVAR_F_MAX:
  848         case MMCBR_IVAR_MAX_DATA:
  849                 return (EINVAL);
  850         }
  851 
  852         return (0);
  853 }
  854 
  855 static int
  856 jz4780_mmc_disable_clock(struct jz4780_mmc_softc *sc)
  857 {
  858         int timeout;
  859 
  860         JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL, JZ_CLOCK_STOP);
  861 
  862         for (timeout = 1000; timeout > 0; timeout--)
  863                 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & JZ_CLK_EN) == 0)
  864                         return (0);
  865         return (ETIMEDOUT);
  866 }
  867 
  868 static int
  869 jz4780_mmc_config_clock(struct jz4780_mmc_softc *sc, uint32_t freq)
  870 {
  871         uint64_t rate;
  872         uint32_t clk_freq;
  873         int err, div;
  874 
  875         err = jz4780_mmc_disable_clock(sc);
  876         if (err != 0)
  877                 return (err);
  878 
  879         clk_get_freq(sc->sc_clk, &rate);
  880         clk_freq = (uint32_t)rate;
  881 
  882         div = 0;
  883         while (clk_freq > freq) {
  884                 div++;
  885                 clk_freq >>= 1;
  886         }
  887         if (div >= 7)
  888                 div = 7;
  889 #if defined(JZ_MMC_DEBUG)
  890         if (div != JZ_MMC_READ_4(sc, JZ_MSC_CLKRT))
  891                 device_printf(sc->sc_dev,
  892                     "UPDATE_IOS: clk -> %u\n", clk_freq);
  893 #endif
  894         JZ_MMC_WRITE_4(sc, JZ_MSC_CLKRT, div);
  895         return (0);
  896 }
  897 
  898 static int
  899 jz4780_mmc_update_ios(device_t bus, device_t child)
  900 {
  901         struct jz4780_mmc_softc *sc;
  902         struct mmc_ios *ios;
  903         int error;
  904 
  905         sc = device_get_softc(bus);
  906         ios = &sc->sc_host.ios;
  907         if (ios->clock) {
  908                 /* Set the MMC clock. */
  909                 error = jz4780_mmc_config_clock(sc, ios->clock);
  910                 if (error != 0)
  911                         return (error);
  912         }
  913 
  914         /* Set the bus width. */
  915         switch (ios->bus_width) {
  916         case bus_width_1:
  917                 sc->sc_cmdat &= ~(JZ_BUS_WIDTH_M);
  918                 sc->sc_cmdat |= JZ_BUS_1BIT;
  919                 break;
  920         case bus_width_4:
  921                 sc->sc_cmdat &= ~(JZ_BUS_WIDTH_M);
  922                 sc->sc_cmdat |= JZ_BUS_4BIT;
  923                 break;
  924         case bus_width_8:
  925                 sc->sc_cmdat &= ~(JZ_BUS_WIDTH_M);
  926                 sc->sc_cmdat |= JZ_BUS_8BIT;
  927                 break;
  928         }
  929         return (0);
  930 }
  931 
  932 static int
  933 jz4780_mmc_get_ro(device_t bus, device_t child)
  934 {
  935 
  936         return (0);
  937 }
  938 
  939 static int
  940 jz4780_mmc_acquire_host(device_t bus, device_t child)
  941 {
  942         struct jz4780_mmc_softc *sc;
  943         int error;
  944 
  945         sc = device_get_softc(bus);
  946         JZ_MMC_LOCK(sc);
  947         while (sc->sc_bus_busy) {
  948                 error = msleep(sc, &sc->sc_mtx, PCATCH, "mmchw", 0);
  949                 if (error != 0) {
  950                         JZ_MMC_UNLOCK(sc);
  951                         return (error);
  952                 }
  953         }
  954         sc->sc_bus_busy++;
  955         JZ_MMC_UNLOCK(sc);
  956 
  957         return (0);
  958 }
  959 
  960 static int
  961 jz4780_mmc_release_host(device_t bus, device_t child)
  962 {
  963         struct jz4780_mmc_softc *sc;
  964 
  965         sc = device_get_softc(bus);
  966         JZ_MMC_LOCK(sc);
  967         sc->sc_bus_busy--;
  968         wakeup(sc);
  969         JZ_MMC_UNLOCK(sc);
  970 
  971         return (0);
  972 }
  973 
  974 static device_method_t jz4780_mmc_methods[] = {
  975         /* Device interface */
  976         DEVMETHOD(device_probe,         jz4780_mmc_probe),
  977         DEVMETHOD(device_attach,        jz4780_mmc_attach),
  978         DEVMETHOD(device_detach,        jz4780_mmc_detach),
  979 
  980         /* Bus interface */
  981         DEVMETHOD(bus_read_ivar,        jz4780_mmc_read_ivar),
  982         DEVMETHOD(bus_write_ivar,       jz4780_mmc_write_ivar),
  983 
  984         /* MMC bridge interface */
  985         DEVMETHOD(mmcbr_update_ios,     jz4780_mmc_update_ios),
  986         DEVMETHOD(mmcbr_request,        jz4780_mmc_request),
  987         DEVMETHOD(mmcbr_get_ro,         jz4780_mmc_get_ro),
  988         DEVMETHOD(mmcbr_acquire_host,   jz4780_mmc_acquire_host),
  989         DEVMETHOD(mmcbr_release_host,   jz4780_mmc_release_host),
  990 
  991         DEVMETHOD_END
  992 };
  993 
  994 static devclass_t jz4780_mmc_devclass;
  995 
  996 static driver_t jz4780_mmc_driver = {
  997         "jzmmc",
  998         jz4780_mmc_methods,
  999         sizeof(struct jz4780_mmc_softc),
 1000 };
 1001 
 1002 DRIVER_MODULE(jzmmc, simplebus, jz4780_mmc_driver, jz4780_mmc_devclass, NULL,
 1003     NULL);
 1004 MMC_DECLARE_BRIDGE(jzmmc);

Cache object: 912dc0c2bb667e0d337f22d08eec414f


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