The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/ingenic/jz4780_mp.c

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    1 /*-
    2  * Copyright (c) 2015 Alexander Kabaev <kan@FreeBSD.org>
    3  * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
    4  * All rights reserved.
    5  *
    6  * Redistribution and use in source and binary forms, with or without
    7  * modification, are permitted provided that the following conditions
    8  * are met:
    9  * 1. Redistributions of source code must retain the above copyright
   10  *    notice, this list of conditions and the following disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * $FreeBSD: stable/12/sys/mips/ingenic/jz4780_mp.c 308857 2016-11-19 17:46:18Z br $
   28  */
   29 #include <sys/cdefs.h>
   30 __FBSDID("$FreeBSD: stable/12/sys/mips/ingenic/jz4780_mp.c 308857 2016-11-19 17:46:18Z br $");
   31 
   32 #include <sys/param.h>
   33 #include <sys/conf.h>
   34 #include <sys/kernel.h>
   35 #include <sys/smp.h>
   36 #include <sys/systm.h>
   37 
   38 #include <machine/cpufunc.h>
   39 #include <machine/hwfunc.h>
   40 #include <machine/md_var.h>
   41 #include <machine/smp.h>
   42 
   43 #include <mips/ingenic/jz4780_regs.h>
   44 #include <mips/ingenic/jz4780_cpuregs.h>
   45 
   46 void jz4780_mpentry(void);
   47 
   48 #define JZ4780_MAXCPU   2
   49 
   50 void
   51 platform_ipi_send(int cpuid)
   52 {
   53 
   54         if (cpuid == 0)
   55                 mips_wr_xburst_mbox0(1);
   56         else
   57                 mips_wr_xburst_mbox1(1);
   58 }
   59 
   60 void
   61 platform_ipi_clear(void)
   62 {
   63         int cpuid = PCPU_GET(cpuid);
   64         uint32_t action;
   65 
   66         action = (cpuid == 0) ? mips_rd_xburst_mbox0() : mips_rd_xburst_mbox1();
   67         KASSERT(action == 1, ("CPU %d: unexpected IPIs: %#x", cpuid, action));
   68         mips_wr_xburst_core_sts(~(JZ_CORESTS_MIRQ0P << cpuid));
   69 }
   70 
   71 int
   72 platform_processor_id(void)
   73 {
   74 
   75         return (mips_rd_ebase() & 7);
   76 }
   77 
   78 int
   79 platform_ipi_hardintr_num(void)
   80 {
   81 
   82         return (1);
   83 }
   84 
   85 int
   86 platform_ipi_softintr_num(void)
   87 {
   88 
   89         return (-1);
   90 }
   91 
   92 void
   93 platform_init_ap(int cpuid)
   94 {
   95         unsigned reg;
   96 
   97         /*
   98          * Clear any pending IPIs.
   99          */
  100         mips_wr_xburst_core_sts(~(JZ_CORESTS_MIRQ0P << cpuid));
  101 
  102         /* Allow IPI mbox for this core */
  103         reg = mips_rd_xburst_reim();
  104         reg |= (JZ_REIM_MIRQ0M << cpuid);
  105         mips_wr_xburst_reim(reg);
  106 
  107         /*
  108          * Unmask the ipi interrupts.
  109          */
  110         reg = hard_int_mask(platform_ipi_hardintr_num());
  111         set_intr_mask(reg);
  112 }
  113 
  114 void
  115 platform_cpu_mask(cpuset_t *mask)
  116 {
  117         uint32_t i, m;
  118 
  119         CPU_ZERO(mask);
  120         for (i = 0, m = 1 ; i < JZ4780_MAXCPU; i++, m <<= 1)
  121                 CPU_SET(i, mask);
  122 }
  123 
  124 struct cpu_group *
  125 platform_smp_topo(void)
  126 {
  127         return (smp_topo_none());
  128 }
  129 
  130 static void
  131 jz4780_core_powerup(void)
  132 {
  133         uint32_t reg;
  134 
  135         reg = readreg(JZ_CGU_BASE + JZ_LPCR);
  136         reg &= ~LPCR_PD_SCPU;
  137         writereg(JZ_CGU_BASE + JZ_LPCR, reg);
  138         do {
  139                 reg = readreg(JZ_CGU_BASE + JZ_LPCR);
  140         } while ((reg & LPCR_SCPUS) != 0);
  141 }
  142 
  143 /*
  144  * Spin up the second code. The code is roughly modeled after
  145  * similar routine in Linux.
  146  */
  147 int
  148 platform_start_ap(int cpuid)
  149 {
  150         uint32_t reg, addr;
  151 
  152         if (cpuid >= JZ4780_MAXCPU)
  153                 return (EINVAL);
  154 
  155         /* Figure out address of mpentry in KSEG1 */
  156         addr = MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(jz4780_mpentry));
  157         KASSERT((addr & ~JZ_REIM_ENTRY_MASK) == 0,
  158             ("Unaligned mpentry"));
  159 
  160         /* Configure core alternative entry point */
  161         reg = mips_rd_xburst_reim();
  162         reg &= ~JZ_REIM_ENTRY_MASK;
  163         reg |= addr & JZ_REIM_ENTRY_MASK;
  164 
  165         /* Allow this core to get IPIs from one being started */
  166         reg |= JZ_REIM_MIRQ0M;
  167         mips_wr_xburst_reim(reg);
  168 
  169         /* Force core into reset and enable use of alternate entry point */
  170         reg = mips_rd_xburst_core_ctl();
  171         reg |= (JZ_CORECTL_SWRST0 << cpuid) | (JZ_CORECTL_RPC0 << cpuid);
  172         mips_wr_xburst_core_ctl(reg);
  173 
  174         /* Power the core up */
  175         jz4780_core_powerup();
  176 
  177         /* Take the core out of reset */
  178         reg &= ~(JZ_CORECTL_SWRST0 << cpuid);
  179         mips_wr_xburst_core_ctl(reg);
  180 
  181         return (0);
  182 }

Cache object: 1226a722d1c2150e0f5a00d81b50672f


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