The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/mips/malta/gt_pci.c

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    1 /*      $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
    2 
    3 /*-
    4  * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
    5  * All rights reserved.
    6  *
    7  * Written by Jason R. Thorpe for Wasabi Systems, Inc.
    8  *
    9  * Redistribution and use in source and binary forms, with or without
   10  * modification, are permitted provided that the following conditions
   11  * are met:
   12  * 1. Redistributions of source code must retain the above copyright
   13  *    notice, this list of conditions and the following disclaimer.
   14  * 2. Redistributions in binary form must reproduce the above copyright
   15  *    notice, this list of conditions and the following disclaimer in the
   16  *    documentation and/or other materials provided with the distribution.
   17  * 3. All advertising materials mentioning features or use of this software
   18  *    must display the following acknowledgement:
   19  *      This product includes software developed for the NetBSD Project by
   20  *      Wasabi Systems, Inc.
   21  * 4. The name of Wasabi Systems, Inc. may not be used to endorse
   22  *    or promote products derived from this software without specific prior
   23  *    written permission.
   24  *
   25  * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
   26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   27  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   28  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL WASABI SYSTEMS, INC
   29  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   30  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   31  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   32  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   33  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   34  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   35  * POSSIBILITY OF SUCH DAMAGE.
   36  */
   37 
   38 /*
   39  * PCI configuration support for gt I/O Processor chip.
   40  */
   41 
   42 #include <sys/cdefs.h>
   43 __FBSDID("$FreeBSD: releng/11.1/sys/mips/malta/gt_pci.c 302287 2016-06-29 23:33:44Z gonzo $");
   44 
   45 #include <sys/param.h>
   46 #include <sys/systm.h>
   47 
   48 #include <sys/bus.h>
   49 #include <sys/endian.h>
   50 #include <sys/interrupt.h>
   51 #include <sys/malloc.h>
   52 #include <sys/kernel.h>
   53 #include <sys/module.h>
   54 #include <sys/rman.h>
   55 
   56 #include <vm/vm.h>
   57 #include <vm/pmap.h>
   58 #include <vm/vm_extern.h>
   59 
   60 #include <machine/bus.h>
   61 #include <machine/cpu.h>
   62 
   63 #include <mips/malta/maltareg.h>
   64 
   65 #include <mips/malta/gtreg.h>
   66 #include <mips/malta/gtvar.h>
   67 
   68 #include <isa/isareg.h>
   69 #include <dev/ic/i8259.h>
   70 
   71 #include <dev/pci/pcireg.h>
   72 #include <dev/pci/pcivar.h>
   73 
   74 #include <dev/pci/pcib_private.h>
   75 #include "pcib_if.h"
   76 
   77 #include <mips/malta/gt_pci_bus_space.h>
   78 
   79 #define ICU_LEN         16      /* number of ISA IRQs */
   80 
   81 /*
   82  * XXX: These defines are from NetBSD's <dev/ic/i8259reg.h>. Respective file
   83  * from FreeBSD src tree <dev/ic/i8259.h> lacks some definitions.
   84  */
   85 #define PIC_OCW1        1
   86 #define PIC_OCW2        0
   87 #define PIC_OCW3        0
   88 
   89 #define OCW2_SELECT     0
   90 #define OCW2_ILS(x)     ((x) << 0)      /* interrupt level select */
   91 
   92 #define OCW3_POLL_IRQ(x) ((x) & 0x7f)
   93 #define OCW3_POLL_PENDING (1U << 7)
   94 
   95 /*
   96  * Galileo controller's registers are LE so convert to then
   97  * to/from native byte order. We rely on boot loader or emulator
   98  * to set "swap bytes" configuration correctly for us
   99  */
  100 #define GT_PCI_DATA(v)  htole32((v))
  101 #define GT_HOST_DATA(v) le32toh((v))
  102 
  103 struct gt_pci_softc;
  104 
  105 struct gt_pci_intr_cookie {
  106         int irq;
  107         struct gt_pci_softc *sc;
  108 };
  109 
  110 struct gt_pci_softc {
  111         device_t                sc_dev;
  112         bus_space_tag_t         sc_st;
  113         bus_space_handle_t      sc_ioh_icu1;
  114         bus_space_handle_t      sc_ioh_icu2;
  115         bus_space_handle_t      sc_ioh_elcr;
  116 
  117         int                     sc_busno;
  118         struct rman             sc_mem_rman;
  119         struct rman             sc_io_rman;
  120         struct rman             sc_irq_rman;
  121         unsigned long           sc_mem;
  122         bus_space_handle_t      sc_io;
  123 
  124         struct resource         *sc_irq;
  125         struct intr_event       *sc_eventstab[ICU_LEN];
  126         struct gt_pci_intr_cookie       sc_intr_cookies[ICU_LEN];
  127         uint16_t                sc_imask;
  128         uint16_t                sc_elcr;
  129 
  130         uint16_t                sc_reserved;
  131 
  132         void                    *sc_ih;
  133 };
  134 
  135 static void gt_pci_set_icus(struct gt_pci_softc *);
  136 static int gt_pci_intr(void *v);
  137 static int gt_pci_probe(device_t);
  138 static int gt_pci_attach(device_t);
  139 static int gt_pci_activate_resource(device_t, device_t, int, int, 
  140     struct resource *);
  141 static int gt_pci_setup_intr(device_t, device_t, struct resource *, 
  142     int, driver_filter_t *, driver_intr_t *, void *, void **);
  143 static int gt_pci_teardown_intr(device_t, device_t, struct resource *, void*);
  144 static int gt_pci_maxslots(device_t );
  145 static int gt_pci_conf_setup(struct gt_pci_softc *, int, int, int, int, 
  146     uint32_t *);
  147 static uint32_t gt_pci_read_config(device_t, u_int, u_int, u_int, u_int, int);
  148 static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int, 
  149     uint32_t, int);
  150 static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin);
  151 static struct resource * gt_pci_alloc_resource(device_t, device_t, int, 
  152     int *, rman_res_t, rman_res_t, rman_res_t, u_int);
  153 
  154 static void
  155 gt_pci_mask_irq(void *source)
  156 {
  157         struct gt_pci_intr_cookie *cookie = source;
  158         struct gt_pci_softc *sc = cookie->sc;
  159         int irq = cookie->irq;
  160 
  161         sc->sc_imask |= (1 << irq);
  162         sc->sc_elcr |= (1 << irq);
  163 
  164         gt_pci_set_icus(sc);
  165 }
  166 
  167 static void
  168 gt_pci_unmask_irq(void *source)
  169 {
  170         struct gt_pci_intr_cookie *cookie = source;
  171         struct gt_pci_softc *sc = cookie->sc;
  172         int irq = cookie->irq;
  173 
  174         /* Enable it, set trigger mode. */
  175         sc->sc_imask &= ~(1 << irq);
  176         sc->sc_elcr &= ~(1 << irq);
  177 
  178         gt_pci_set_icus(sc);
  179 }
  180 
  181 static void
  182 gt_pci_set_icus(struct gt_pci_softc *sc)
  183 {
  184         /* Enable the cascade IRQ (2) if 8-15 is enabled. */
  185         if ((sc->sc_imask & 0xff00) != 0xff00)
  186                 sc->sc_imask &= ~(1U << 2);
  187         else
  188                 sc->sc_imask |= (1U << 2);
  189 
  190         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1,
  191             sc->sc_imask & 0xff);
  192         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1,
  193             (sc->sc_imask >> 8) & 0xff);
  194 
  195         bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
  196             sc->sc_elcr & 0xff);
  197         bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
  198             (sc->sc_elcr >> 8) & 0xff);
  199 }
  200 
  201 static int
  202 gt_pci_intr(void *v)
  203 {
  204         struct gt_pci_softc *sc = v;
  205         struct intr_event *event;
  206         int irq;
  207 
  208         for (;;) {
  209                 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3,
  210                     OCW3_SEL | OCW3_P);
  211                 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3);
  212                 if ((irq & OCW3_POLL_PENDING) == 0)
  213                 {
  214                         return FILTER_HANDLED;
  215                 }
  216 
  217                 irq = OCW3_POLL_IRQ(irq);
  218 
  219                 if (irq == 2) {
  220                         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
  221                             PIC_OCW3, OCW3_SEL | OCW3_P);
  222                         irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2,
  223                             PIC_OCW3);
  224                         if (irq & OCW3_POLL_PENDING)
  225                                 irq = OCW3_POLL_IRQ(irq) + 8;
  226                         else
  227                                 irq = 2;
  228                 }
  229 
  230                 event = sc->sc_eventstab[irq];
  231 
  232                 if (!event || TAILQ_EMPTY(&event->ie_handlers))
  233                         continue;
  234 
  235                 /* TODO: frame instead of NULL? */
  236                 intr_event_handle(event, NULL);
  237                 /* XXX: Log stray IRQs */
  238 
  239                 /* Send a specific EOI to the 8259. */
  240                 if (irq > 7) {
  241                         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
  242                             PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
  243                             OCW2_ILS(irq & 7));
  244                         irq = 2;
  245                 }
  246 
  247                 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2,
  248                     OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
  249         }
  250 
  251         return FILTER_HANDLED;
  252 }
  253 
  254 static int
  255 gt_pci_probe(device_t dev)
  256 {
  257         device_set_desc(dev, "GT64120 PCI bridge");
  258         return (0);
  259 }
  260 
  261 static int
  262 gt_pci_attach(device_t dev)
  263 {
  264 
  265         uint32_t busno;                                
  266         struct gt_pci_softc *sc = device_get_softc(dev);
  267         int rid;
  268 
  269         busno = 0;
  270         sc->sc_dev = dev;
  271         sc->sc_busno = busno;
  272         sc->sc_st = mips_bus_space_generic;
  273 
  274         /* Use KSEG1 to access IO ports for it is uncached */
  275         sc->sc_io = MALTA_PCI0_IO_BASE;
  276         sc->sc_io_rman.rm_type = RMAN_ARRAY;
  277         sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports";
  278         /* 
  279          * First 256 bytes are ISA's registers: e.g. i8259's
  280          * So do not use them for general purpose PCI I/O window
  281          */
  282         if (rman_init(&sc->sc_io_rman) != 0 ||
  283             rman_manage_region(&sc->sc_io_rman, 0x100, 0xffff) != 0) {
  284                 panic("gt_pci_attach: failed to set up I/O rman");
  285         }
  286 
  287         /* Use KSEG1 to access PCI memory for it is uncached */
  288         sc->sc_mem = MALTA_PCIMEM1_BASE;
  289         sc->sc_mem_rman.rm_type = RMAN_ARRAY;
  290         sc->sc_mem_rman.rm_descr = "GT64120 PCI Memory";
  291         if (rman_init(&sc->sc_mem_rman) != 0 ||
  292             rman_manage_region(&sc->sc_mem_rman, 
  293             sc->sc_mem, sc->sc_mem + MALTA_PCIMEM1_SIZE) != 0) {
  294                 panic("gt_pci_attach: failed to set up memory rman");
  295         }
  296         sc->sc_irq_rman.rm_type = RMAN_ARRAY;
  297         sc->sc_irq_rman.rm_descr = "GT64120 PCI IRQs";
  298         if (rman_init(&sc->sc_irq_rman) != 0 ||
  299             rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
  300                 panic("gt_pci_attach: failed to set up IRQ rman");
  301 
  302         /*
  303          * Map the PIC/ELCR registers.
  304          */
  305 #if 0
  306         if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
  307                 device_printf(dev, "unable to map ELCR registers\n");
  308         if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
  309                 device_printf(dev, "unable to map ICU1 registers\n");
  310         if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
  311                 device_printf(dev, "unable to map ICU2 registers\n");
  312 #else
  313         sc->sc_ioh_elcr = MIPS_PHYS_TO_KSEG1(sc->sc_io + 0x4d0);
  314         sc->sc_ioh_icu1 = MIPS_PHYS_TO_KSEG1(sc->sc_io + IO_ICU1);
  315         sc->sc_ioh_icu2 = MIPS_PHYS_TO_KSEG1(sc->sc_io + IO_ICU2);
  316 #endif  
  317 
  318 
  319         /* All interrupts default to "masked off". */
  320         sc->sc_imask = 0xffff;
  321 
  322         /* All interrupts default to edge-triggered. */
  323         sc->sc_elcr = 0;
  324 
  325         /*
  326          * Initialize the 8259s.
  327          */
  328         /* reset, program device, 4 bytes */
  329         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
  330             ICW1_RESET | ICW1_IC4);
  331         /*
  332          * XXX: values from NetBSD's <dev/ic/i8259reg.h>
  333          */      
  334         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
  335             0/*XXX*/);
  336         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
  337             1 << 2);
  338         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
  339             ICW4_8086);
  340 
  341         /* mask all interrupts */
  342         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
  343             sc->sc_imask & 0xff);
  344 
  345         /* enable special mask mode */
  346         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
  347             OCW3_SEL | OCW3_ESMM | OCW3_SMM);
  348 
  349         /* read IRR by default */
  350         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
  351             OCW3_SEL | OCW3_RR);
  352 
  353         /* reset, program device, 4 bytes */
  354         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
  355             ICW1_RESET | ICW1_IC4);
  356         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
  357             0/*XXX*/);
  358         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
  359             1 << 2);
  360         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
  361             ICW4_8086);
  362 
  363         /* mask all interrupts */
  364         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
  365             sc->sc_imask & 0xff);
  366 
  367         /* enable special mask mode */
  368         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
  369             OCW3_SEL | OCW3_ESMM | OCW3_SMM);
  370 
  371         /* read IRR by default */
  372         bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
  373             OCW3_SEL | OCW3_RR);
  374 
  375         /*
  376          * Default all interrupts to edge-triggered.
  377          */
  378         bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
  379             sc->sc_elcr & 0xff);
  380         bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
  381             (sc->sc_elcr >> 8) & 0xff);
  382 
  383         /*
  384          * Some ISA interrupts are reserved for devices that
  385          * we know are hard-wired to certain IRQs.
  386          */
  387         sc->sc_reserved =
  388                 (1U << 0) |     /* timer */
  389                 (1U << 1) |     /* keyboard controller (keyboard) */
  390                 (1U << 2) |     /* PIC cascade */
  391                 (1U << 3) |     /* COM 2 */
  392                 (1U << 4) |     /* COM 1 */
  393                 (1U << 6) |     /* floppy */
  394                 (1U << 7) |     /* centronics */
  395                 (1U << 8) |     /* RTC */
  396                 (1U << 9) |     /* I2C */
  397                 (1U << 12) |    /* keyboard controller (mouse) */
  398                 (1U << 14) |    /* IDE primary */
  399                 (1U << 15);     /* IDE secondary */
  400 
  401         /* Hook up our interrupt handler. */
  402         if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 
  403             MALTA_SOUTHBRIDGE_INTR, MALTA_SOUTHBRIDGE_INTR, 1, 
  404             RF_SHAREABLE | RF_ACTIVE)) == NULL) {
  405                 device_printf(dev, "unable to allocate IRQ resource\n");
  406                 return ENXIO;
  407         }
  408 
  409         if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
  410                             gt_pci_intr, NULL, sc, &sc->sc_ih))) {
  411                 device_printf(dev, 
  412                     "WARNING: unable to register interrupt handler\n");
  413                 return ENXIO;
  414         }
  415 
  416         /* Initialize memory and i/o rmans. */
  417         device_add_child(dev, "pci", -1);
  418         return (bus_generic_attach(dev));
  419 }
  420 
  421 static int
  422 gt_pci_maxslots(device_t dev)
  423 {
  424         return (PCI_SLOTMAX);
  425 }
  426 
  427 static int
  428 gt_pci_conf_setup(struct gt_pci_softc *sc, int bus, int slot, int func,
  429     int reg, uint32_t *addr)
  430 {
  431         *addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
  432 
  433         return (0);
  434 }
  435 
  436 static uint32_t
  437 gt_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
  438     int bytes)
  439 {
  440         struct gt_pci_softc *sc = device_get_softc(dev);
  441         uint32_t data;
  442         uint32_t addr;
  443         uint32_t shift, mask;
  444 
  445         if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
  446                 return (uint32_t)(-1);
  447 
  448         /* Clear cause register bits. */
  449         GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
  450         GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
  451         /* 
  452          * Galileo system controller is special
  453          */
  454         if ((bus == 0) && (slot == 0))
  455                 data = GT_PCI_DATA(GT_REGVAL(GT_PCI0_CFG_DATA));
  456         else
  457                 data = GT_REGVAL(GT_PCI0_CFG_DATA);
  458 
  459         /* Check for master abort. */
  460         if (GT_HOST_DATA(GT_REGVAL(GT_INTR_CAUSE)) & (GTIC_MASABORT0 | GTIC_TARABORT0))
  461                 data = (uint32_t) -1;
  462 
  463         switch(reg % 4)
  464         {
  465         case 3:
  466                 shift = 24;
  467                 break;
  468         case 2:
  469                 shift = 16;
  470                 break;
  471         case 1:
  472                 shift = 8;
  473                 break;
  474         default:
  475                 shift = 0;
  476                 break;
  477         }       
  478 
  479         switch(bytes)
  480         {
  481         case 1:
  482                 mask = 0xff;
  483                 data = (data >> shift) & mask;
  484                 break;
  485         case 2:
  486                 mask = 0xffff;
  487                 if(reg % 4 == 0)
  488                         data = data & mask;
  489                 else
  490                         data = (data >> 16) & mask;
  491                 break;
  492         case 4:
  493                 break;
  494         default:
  495                 panic("gt_pci_readconfig: wrong bytes count");
  496                 break;
  497         }
  498 #if 0
  499         printf("PCICONF_READ(%02x:%02x.%02x[%04x] -> %02x(%d)\n", 
  500           bus, slot, func, reg, data, bytes);
  501 #endif
  502 
  503         return (data);
  504 }
  505 
  506 static void
  507 gt_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
  508     uint32_t data, int bytes)
  509 {
  510         struct gt_pci_softc *sc = device_get_softc(dev);
  511         uint32_t addr;
  512         uint32_t reg_data;
  513         uint32_t shift, mask;
  514 
  515         if(bytes != 4)
  516         {
  517                 reg_data = gt_pci_read_config(dev, bus, slot, func, reg, 4);
  518 
  519                 shift = 8 * (reg & 3);
  520 
  521                 switch(bytes)
  522                 {
  523                 case 1:
  524                         mask = 0xff;
  525                         data = (reg_data & ~ (mask << shift)) | (data << shift);
  526                         break;
  527                 case 2:
  528                         mask = 0xffff;
  529                         if(reg % 4 == 0)
  530                                 data = (reg_data & ~mask) | data;
  531                         else
  532                                 data = (reg_data & ~ (mask << shift)) | 
  533                                     (data << shift);
  534                         break;
  535                 case 4:
  536                         break;
  537                 default:
  538                         panic("gt_pci_readconfig: wrong bytes count");
  539                         break;
  540                 }
  541         }
  542 
  543         if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
  544                 return;
  545 
  546         /* The galileo has problems accessing device 31. */
  547         if (bus == 0 && slot == 31)
  548                 return;
  549 
  550         /* XXX: no support for bus > 0 yet */
  551         if (bus > 0)
  552                 return;
  553 
  554         /* Clear cause register bits. */
  555         GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
  556 
  557         GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
  558 
  559         /* 
  560          * Galileo system controller is special
  561          */
  562         if ((bus == 0) && (slot == 0))
  563                 GT_REGVAL(GT_PCI0_CFG_DATA) = GT_PCI_DATA(data);
  564         else
  565                 GT_REGVAL(GT_PCI0_CFG_DATA) = data;
  566 
  567 #if 0
  568         printf("PCICONF_WRITE(%02x:%02x.%02x[%04x] -> %02x(%d)\n", 
  569           bus, slot, func, reg, data, bytes);
  570 #endif
  571 
  572 }
  573 
  574 static int
  575 gt_pci_route_interrupt(device_t pcib, device_t dev, int pin)
  576 {
  577         int bus;
  578         int device;
  579         int func;
  580         /* struct gt_pci_softc *sc = device_get_softc(pcib); */
  581         bus = pci_get_bus(dev);
  582         device = pci_get_slot(dev);
  583         func = pci_get_function(dev);
  584         /* 
  585          * XXXMIPS: We need routing logic. This is just a stub .
  586          */
  587         switch (device) {
  588         case 9: /*
  589                  * PIIX4 IDE adapter. HW IRQ0
  590                  */
  591                 return 0;
  592         case 11: /* Ethernet */
  593                 return 10;
  594         default:
  595                 device_printf(pcib, "no IRQ mapping for %d/%d/%d/%d\n", bus, device, func, pin);
  596                 
  597         }
  598         return (0);
  599 
  600 }
  601 
  602 static int
  603 gt_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
  604 {
  605         struct gt_pci_softc *sc = device_get_softc(dev);
  606         switch (which) {
  607         case PCIB_IVAR_DOMAIN:
  608                 *result = 0;
  609                 return (0);
  610         case PCIB_IVAR_BUS:
  611                 *result = sc->sc_busno;
  612                 return (0);
  613                 
  614         }
  615         return (ENOENT);
  616 }
  617 
  618 static int
  619 gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
  620 {
  621         struct gt_pci_softc * sc = device_get_softc(dev);
  622 
  623         switch (which) {
  624         case PCIB_IVAR_BUS:
  625                 sc->sc_busno = result;
  626                 return (0);
  627         }
  628         return (ENOENT);
  629 }
  630 
  631 static struct resource *
  632 gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
  633     rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
  634 {
  635         struct gt_pci_softc *sc = device_get_softc(bus);        
  636         struct resource *rv = NULL;
  637         struct rman *rm;
  638         bus_space_handle_t bh = 0;
  639 
  640         switch (type) {
  641         case SYS_RES_IRQ:
  642                 rm = &sc->sc_irq_rman;
  643                 break;
  644         case SYS_RES_MEMORY:
  645                 rm = &sc->sc_mem_rman;
  646                 bh = sc->sc_mem;
  647                 break;
  648         case SYS_RES_IOPORT:
  649                 rm = &sc->sc_io_rman;
  650                 bh = sc->sc_io;
  651                 break;
  652         default:
  653                 return (NULL);
  654         }
  655 
  656         rv = rman_reserve_resource(rm, start, end, count, flags, child);
  657         if (rv == NULL)
  658                 return (NULL);
  659         rman_set_rid(rv, *rid);
  660         if (type != SYS_RES_IRQ) {
  661                 bh += (rman_get_start(rv));
  662 
  663                 rman_set_bustag(rv, gt_pci_bus_space);
  664                 rman_set_bushandle(rv, bh);
  665                 if (flags & RF_ACTIVE) {
  666                         if (bus_activate_resource(child, type, *rid, rv)) {
  667                                 rman_release_resource(rv);
  668                                 return (NULL);
  669                         }
  670                 } 
  671         }
  672         return (rv);
  673 }
  674 
  675 static int
  676 gt_pci_activate_resource(device_t bus, device_t child, int type, int rid,
  677     struct resource *r)
  678 {
  679         bus_space_handle_t p;
  680         int error;
  681         
  682         if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
  683                 error = bus_space_map(rman_get_bustag(r),
  684                     rman_get_bushandle(r), rman_get_size(r), 0, &p);
  685                 if (error) 
  686                         return (error);
  687                 rman_set_bushandle(r, p);
  688         }
  689         return (rman_activate_resource(r));
  690 }
  691 
  692 static int
  693 gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires, 
  694                 int flags, driver_filter_t *filt, driver_intr_t *handler, 
  695                 void *arg, void **cookiep)
  696 {
  697         struct gt_pci_softc *sc = device_get_softc(dev);
  698         struct intr_event *event;
  699         int irq, error;
  700 
  701         irq = rman_get_start(ires);
  702         if (irq >= ICU_LEN || irq == 2)
  703                 panic("%s: bad irq or type", __func__);
  704 
  705         event = sc->sc_eventstab[irq];
  706         sc->sc_intr_cookies[irq].irq = irq;
  707         sc->sc_intr_cookies[irq].sc = sc;
  708         if (event == NULL) {
  709                 error = intr_event_create(&event, 
  710                     (void *)&sc->sc_intr_cookies[irq], 0, irq,
  711                     gt_pci_mask_irq, gt_pci_unmask_irq,
  712                     NULL, NULL, "gt_pci intr%d:", irq);
  713                 if (error)
  714                         return 0;
  715                 sc->sc_eventstab[irq] = event;
  716         }
  717 
  718         intr_event_add_handler(event, device_get_nameunit(child), filt, 
  719             handler, arg, intr_priority(flags), flags, cookiep);
  720 
  721         gt_pci_unmask_irq((void *)&sc->sc_intr_cookies[irq]);
  722         return 0;
  723 }
  724 
  725 static int
  726 gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
  727     void *cookie)
  728 {
  729         struct gt_pci_softc *sc = device_get_softc(dev);
  730         int irq;
  731 
  732         irq = rman_get_start(res);
  733         gt_pci_mask_irq((void *)&sc->sc_intr_cookies[irq]);
  734 
  735         return (intr_event_remove_handler(cookie));
  736 }
  737 
  738 static device_method_t gt_pci_methods[] = {
  739         /* Device interface */
  740         DEVMETHOD(device_probe,         gt_pci_probe),
  741         DEVMETHOD(device_attach,        gt_pci_attach),
  742         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
  743         DEVMETHOD(device_suspend,       bus_generic_suspend),
  744         DEVMETHOD(device_resume,        bus_generic_resume),
  745 
  746         /* Bus interface */
  747         DEVMETHOD(bus_read_ivar,        gt_read_ivar),
  748         DEVMETHOD(bus_write_ivar,       gt_write_ivar),
  749         DEVMETHOD(bus_alloc_resource,   gt_pci_alloc_resource),
  750         DEVMETHOD(bus_release_resource, bus_generic_release_resource),
  751         DEVMETHOD(bus_activate_resource, gt_pci_activate_resource),
  752         DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
  753         DEVMETHOD(bus_setup_intr,       gt_pci_setup_intr),
  754         DEVMETHOD(bus_teardown_intr,    gt_pci_teardown_intr),
  755 
  756         /* pcib interface */
  757         DEVMETHOD(pcib_maxslots,        gt_pci_maxslots),
  758         DEVMETHOD(pcib_read_config,     gt_pci_read_config),
  759         DEVMETHOD(pcib_write_config,    gt_pci_write_config),
  760         DEVMETHOD(pcib_route_interrupt, gt_pci_route_interrupt),
  761 
  762         DEVMETHOD_END
  763 };
  764 
  765 static driver_t gt_pci_driver = {
  766         "pcib",
  767         gt_pci_methods,
  768         sizeof(struct gt_pci_softc),
  769 };
  770 
  771 static devclass_t gt_pci_devclass;
  772 
  773 DRIVER_MODULE(gt_pci, gt, gt_pci_driver, gt_pci_devclass, 0, 0);

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