Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]
FreeBSD/Linux Kernel Cross Reference
sys/mips/malta/gt_pci.c
Version:
- FREEBSD - FREEBSD-13-STABLE - FREEBSD-13-0 - FREEBSD-12-STABLE - FREEBSD-12-0 - FREEBSD-11-STABLE - FREEBSD-11-0 - FREEBSD-10-STABLE - FREEBSD-10-0 - FREEBSD-9-STABLE - FREEBSD-9-0 - FREEBSD-8-STABLE - FREEBSD-8-0 - FREEBSD-7-STABLE - FREEBSD-7-0 - FREEBSD-6-STABLE - FREEBSD-6-0 - FREEBSD-5-STABLE - FREEBSD-5-0 - FREEBSD-4-STABLE - FREEBSD-3-STABLE - FREEBSD22 - l41 - OPENBSD - linux-2.6 - MK84 - PLAN9 - xnu-8792
SearchContext: - none - 3 - 10
SearchContext: - none - 3 - 10
1 /* $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */ 2 3 /*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 2001, 2002 Wasabi Systems, Inc. 7 * All rights reserved. 8 * 9 * Written by Jason R. Thorpe for Wasabi Systems, Inc. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed for the NetBSD Project by 22 * Wasabi Systems, Inc. 23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse 24 * or promote products derived from this software without specific prior 25 * written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND 28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * PCI configuration support for gt I/O Processor chip. 42 */ 43 44 #include <sys/cdefs.h> 45 __FBSDID("$FreeBSD: releng/12.0/sys/mips/malta/gt_pci.c 336639 2018-07-23 15:36:55Z avg $"); 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 50 #include <sys/bus.h> 51 #include <sys/endian.h> 52 #include <sys/interrupt.h> 53 #include <sys/malloc.h> 54 #include <sys/kernel.h> 55 #include <sys/module.h> 56 #include <sys/rman.h> 57 58 #include <vm/vm.h> 59 #include <vm/pmap.h> 60 #include <vm/vm_extern.h> 61 62 #include <machine/bus.h> 63 #include <machine/cpu.h> 64 65 #include <mips/malta/maltareg.h> 66 67 #include <mips/malta/gtreg.h> 68 #include <mips/malta/gtvar.h> 69 70 #include <isa/isareg.h> 71 #include <dev/ic/i8259.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 76 #include <dev/pci/pcib_private.h> 77 #include "pcib_if.h" 78 79 #include <mips/malta/gt_pci_bus_space.h> 80 81 #define ICU_LEN 16 /* number of ISA IRQs */ 82 83 /* 84 * XXX: These defines are from NetBSD's <dev/ic/i8259reg.h>. Respective file 85 * from FreeBSD src tree <dev/ic/i8259.h> lacks some definitions. 86 */ 87 #define PIC_OCW1 1 88 #define PIC_OCW2 0 89 #define PIC_OCW3 0 90 91 #define OCW2_SELECT 0 92 #define OCW2_ILS(x) ((x) << 0) /* interrupt level select */ 93 94 #define OCW3_POLL_IRQ(x) ((x) & 0x7f) 95 #define OCW3_POLL_PENDING (1U << 7) 96 97 /* 98 * Galileo controller's registers are LE so convert to then 99 * to/from native byte order. We rely on boot loader or emulator 100 * to set "swap bytes" configuration correctly for us 101 */ 102 #define GT_PCI_DATA(v) htole32((v)) 103 #define GT_HOST_DATA(v) le32toh((v)) 104 105 struct gt_pci_softc; 106 107 struct gt_pci_intr_cookie { 108 int irq; 109 struct gt_pci_softc *sc; 110 }; 111 112 struct gt_pci_softc { 113 device_t sc_dev; 114 bus_space_tag_t sc_st; 115 bus_space_handle_t sc_ioh_icu1; 116 bus_space_handle_t sc_ioh_icu2; 117 bus_space_handle_t sc_ioh_elcr; 118 119 int sc_busno; 120 struct rman sc_mem_rman; 121 struct rman sc_io_rman; 122 struct rman sc_irq_rman; 123 unsigned long sc_mem; 124 bus_space_handle_t sc_io; 125 126 struct resource *sc_irq; 127 struct intr_event *sc_eventstab[ICU_LEN]; 128 struct gt_pci_intr_cookie sc_intr_cookies[ICU_LEN]; 129 uint16_t sc_imask; 130 uint16_t sc_elcr; 131 132 uint16_t sc_reserved; 133 134 void *sc_ih; 135 }; 136 137 static void gt_pci_set_icus(struct gt_pci_softc *); 138 static int gt_pci_intr(void *v); 139 static int gt_pci_probe(device_t); 140 static int gt_pci_attach(device_t); 141 static int gt_pci_activate_resource(device_t, device_t, int, int, 142 struct resource *); 143 static int gt_pci_setup_intr(device_t, device_t, struct resource *, 144 int, driver_filter_t *, driver_intr_t *, void *, void **); 145 static int gt_pci_teardown_intr(device_t, device_t, struct resource *, void*); 146 static int gt_pci_maxslots(device_t ); 147 static int gt_pci_conf_setup(struct gt_pci_softc *, int, int, int, int, 148 uint32_t *); 149 static uint32_t gt_pci_read_config(device_t, u_int, u_int, u_int, u_int, int); 150 static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int, 151 uint32_t, int); 152 static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin); 153 static struct resource * gt_pci_alloc_resource(device_t, device_t, int, 154 int *, rman_res_t, rman_res_t, rman_res_t, u_int); 155 156 static void 157 gt_pci_mask_irq(void *source) 158 { 159 struct gt_pci_intr_cookie *cookie = source; 160 struct gt_pci_softc *sc = cookie->sc; 161 int irq = cookie->irq; 162 163 sc->sc_imask |= (1 << irq); 164 sc->sc_elcr |= (1 << irq); 165 166 gt_pci_set_icus(sc); 167 } 168 169 static void 170 gt_pci_unmask_irq(void *source) 171 { 172 struct gt_pci_intr_cookie *cookie = source; 173 struct gt_pci_softc *sc = cookie->sc; 174 int irq = cookie->irq; 175 176 /* Enable it, set trigger mode. */ 177 sc->sc_imask &= ~(1 << irq); 178 sc->sc_elcr &= ~(1 << irq); 179 180 gt_pci_set_icus(sc); 181 } 182 183 static void 184 gt_pci_set_icus(struct gt_pci_softc *sc) 185 { 186 /* Enable the cascade IRQ (2) if 8-15 is enabled. */ 187 if ((sc->sc_imask & 0xff00) != 0xff00) 188 sc->sc_imask &= ~(1U << 2); 189 else 190 sc->sc_imask |= (1U << 2); 191 192 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1, 193 sc->sc_imask & 0xff); 194 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1, 195 (sc->sc_imask >> 8) & 0xff); 196 197 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0, 198 sc->sc_elcr & 0xff); 199 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1, 200 (sc->sc_elcr >> 8) & 0xff); 201 } 202 203 static int 204 gt_pci_intr(void *v) 205 { 206 struct gt_pci_softc *sc = v; 207 struct intr_event *event; 208 int irq; 209 210 for (;;) { 211 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3, 212 OCW3_SEL | OCW3_P); 213 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3); 214 if ((irq & OCW3_POLL_PENDING) == 0) 215 { 216 return FILTER_HANDLED; 217 } 218 219 irq = OCW3_POLL_IRQ(irq); 220 221 if (irq == 2) { 222 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 223 PIC_OCW3, OCW3_SEL | OCW3_P); 224 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2, 225 PIC_OCW3); 226 if (irq & OCW3_POLL_PENDING) 227 irq = OCW3_POLL_IRQ(irq) + 8; 228 else 229 irq = 2; 230 } 231 232 event = sc->sc_eventstab[irq]; 233 234 if (!event || CK_SLIST_EMPTY(&event->ie_handlers)) 235 continue; 236 237 /* TODO: frame instead of NULL? */ 238 intr_event_handle(event, NULL); 239 /* XXX: Log stray IRQs */ 240 241 /* Send a specific EOI to the 8259. */ 242 if (irq > 7) { 243 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 244 PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL | 245 OCW2_ILS(irq & 7)); 246 irq = 2; 247 } 248 249 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2, 250 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq)); 251 } 252 253 return FILTER_HANDLED; 254 } 255 256 static int 257 gt_pci_probe(device_t dev) 258 { 259 device_set_desc(dev, "GT64120 PCI bridge"); 260 return (0); 261 } 262 263 static int 264 gt_pci_attach(device_t dev) 265 { 266 267 uint32_t busno; 268 struct gt_pci_softc *sc = device_get_softc(dev); 269 int rid; 270 271 busno = 0; 272 sc->sc_dev = dev; 273 sc->sc_busno = busno; 274 sc->sc_st = mips_bus_space_generic; 275 276 /* Use KSEG1 to access IO ports for it is uncached */ 277 sc->sc_io = MALTA_PCI0_IO_BASE; 278 sc->sc_io_rman.rm_type = RMAN_ARRAY; 279 sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports"; 280 /* 281 * First 256 bytes are ISA's registers: e.g. i8259's 282 * So do not use them for general purpose PCI I/O window 283 */ 284 if (rman_init(&sc->sc_io_rman) != 0 || 285 rman_manage_region(&sc->sc_io_rman, 0x100, 0xffff) != 0) { 286 panic("gt_pci_attach: failed to set up I/O rman"); 287 } 288 289 /* Use KSEG1 to access PCI memory for it is uncached */ 290 sc->sc_mem = MALTA_PCIMEM1_BASE; 291 sc->sc_mem_rman.rm_type = RMAN_ARRAY; 292 sc->sc_mem_rman.rm_descr = "GT64120 PCI Memory"; 293 if (rman_init(&sc->sc_mem_rman) != 0 || 294 rman_manage_region(&sc->sc_mem_rman, 295 sc->sc_mem, sc->sc_mem + MALTA_PCIMEM1_SIZE) != 0) { 296 panic("gt_pci_attach: failed to set up memory rman"); 297 } 298 sc->sc_irq_rman.rm_type = RMAN_ARRAY; 299 sc->sc_irq_rman.rm_descr = "GT64120 PCI IRQs"; 300 if (rman_init(&sc->sc_irq_rman) != 0 || 301 rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0) 302 panic("gt_pci_attach: failed to set up IRQ rman"); 303 304 /* 305 * Map the PIC/ELCR registers. 306 */ 307 #if 0 308 if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0) 309 device_printf(dev, "unable to map ELCR registers\n"); 310 if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0) 311 device_printf(dev, "unable to map ICU1 registers\n"); 312 if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0) 313 device_printf(dev, "unable to map ICU2 registers\n"); 314 #else 315 sc->sc_ioh_elcr = MIPS_PHYS_TO_KSEG1(sc->sc_io + 0x4d0); 316 sc->sc_ioh_icu1 = MIPS_PHYS_TO_KSEG1(sc->sc_io + IO_ICU1); 317 sc->sc_ioh_icu2 = MIPS_PHYS_TO_KSEG1(sc->sc_io + IO_ICU2); 318 #endif 319 320 321 /* All interrupts default to "masked off". */ 322 sc->sc_imask = 0xffff; 323 324 /* All interrupts default to edge-triggered. */ 325 sc->sc_elcr = 0; 326 327 /* 328 * Initialize the 8259s. 329 */ 330 /* reset, program device, 4 bytes */ 331 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, 332 ICW1_RESET | ICW1_IC4); 333 /* 334 * XXX: values from NetBSD's <dev/ic/i8259reg.h> 335 */ 336 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, 337 0/*XXX*/); 338 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, 339 1 << 2); 340 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, 341 ICW4_8086); 342 343 /* mask all interrupts */ 344 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1, 345 sc->sc_imask & 0xff); 346 347 /* enable special mask mode */ 348 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, 349 OCW3_SEL | OCW3_ESMM | OCW3_SMM); 350 351 /* read IRR by default */ 352 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0, 353 OCW3_SEL | OCW3_RR); 354 355 /* reset, program device, 4 bytes */ 356 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, 357 ICW1_RESET | ICW1_IC4); 358 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, 359 0/*XXX*/); 360 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, 361 1 << 2); 362 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, 363 ICW4_8086); 364 365 /* mask all interrupts */ 366 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1, 367 sc->sc_imask & 0xff); 368 369 /* enable special mask mode */ 370 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, 371 OCW3_SEL | OCW3_ESMM | OCW3_SMM); 372 373 /* read IRR by default */ 374 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0, 375 OCW3_SEL | OCW3_RR); 376 377 /* 378 * Default all interrupts to edge-triggered. 379 */ 380 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0, 381 sc->sc_elcr & 0xff); 382 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1, 383 (sc->sc_elcr >> 8) & 0xff); 384 385 /* 386 * Some ISA interrupts are reserved for devices that 387 * we know are hard-wired to certain IRQs. 388 */ 389 sc->sc_reserved = 390 (1U << 0) | /* timer */ 391 (1U << 1) | /* keyboard controller (keyboard) */ 392 (1U << 2) | /* PIC cascade */ 393 (1U << 3) | /* COM 2 */ 394 (1U << 4) | /* COM 1 */ 395 (1U << 6) | /* floppy */ 396 (1U << 7) | /* centronics */ 397 (1U << 8) | /* RTC */ 398 (1U << 9) | /* I2C */ 399 (1U << 12) | /* keyboard controller (mouse) */ 400 (1U << 14) | /* IDE primary */ 401 (1U << 15); /* IDE secondary */ 402 403 /* Hook up our interrupt handler. */ 404 if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 405 MALTA_SOUTHBRIDGE_INTR, MALTA_SOUTHBRIDGE_INTR, 1, 406 RF_SHAREABLE | RF_ACTIVE)) == NULL) { 407 device_printf(dev, "unable to allocate IRQ resource\n"); 408 return ENXIO; 409 } 410 411 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC, 412 gt_pci_intr, NULL, sc, &sc->sc_ih))) { 413 device_printf(dev, 414 "WARNING: unable to register interrupt handler\n"); 415 return ENXIO; 416 } 417 418 /* Initialize memory and i/o rmans. */ 419 device_add_child(dev, "pci", -1); 420 return (bus_generic_attach(dev)); 421 } 422 423 static int 424 gt_pci_maxslots(device_t dev) 425 { 426 return (PCI_SLOTMAX); 427 } 428 429 static int 430 gt_pci_conf_setup(struct gt_pci_softc *sc, int bus, int slot, int func, 431 int reg, uint32_t *addr) 432 { 433 *addr = (bus << 16) | (slot << 11) | (func << 8) | reg; 434 435 return (0); 436 } 437 438 static uint32_t 439 gt_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 440 int bytes) 441 { 442 struct gt_pci_softc *sc = device_get_softc(dev); 443 uint32_t data; 444 uint32_t addr; 445 uint32_t shift, mask; 446 447 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr)) 448 return (uint32_t)(-1); 449 450 /* Clear cause register bits. */ 451 GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0); 452 GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr); 453 /* 454 * Galileo system controller is special 455 */ 456 if ((bus == 0) && (slot == 0)) 457 data = GT_PCI_DATA(GT_REGVAL(GT_PCI0_CFG_DATA)); 458 else 459 data = GT_REGVAL(GT_PCI0_CFG_DATA); 460 461 /* Check for master abort. */ 462 if (GT_HOST_DATA(GT_REGVAL(GT_INTR_CAUSE)) & (GTIC_MASABORT0 | GTIC_TARABORT0)) 463 data = (uint32_t) -1; 464 465 switch(reg % 4) 466 { 467 case 3: 468 shift = 24; 469 break; 470 case 2: 471 shift = 16; 472 break; 473 case 1: 474 shift = 8; 475 break; 476 default: 477 shift = 0; 478 break; 479 } 480 481 switch(bytes) 482 { 483 case 1: 484 mask = 0xff; 485 data = (data >> shift) & mask; 486 break; 487 case 2: 488 mask = 0xffff; 489 if(reg % 4 == 0) 490 data = data & mask; 491 else 492 data = (data >> 16) & mask; 493 break; 494 case 4: 495 break; 496 default: 497 panic("gt_pci_readconfig: wrong bytes count"); 498 break; 499 } 500 #if 0 501 printf("PCICONF_READ(%02x:%02x.%02x[%04x] -> %02x(%d)\n", 502 bus, slot, func, reg, data, bytes); 503 #endif 504 505 return (data); 506 } 507 508 static void 509 gt_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg, 510 uint32_t data, int bytes) 511 { 512 struct gt_pci_softc *sc = device_get_softc(dev); 513 uint32_t addr; 514 uint32_t reg_data; 515 uint32_t shift, mask; 516 517 if(bytes != 4) 518 { 519 reg_data = gt_pci_read_config(dev, bus, slot, func, reg, 4); 520 521 shift = 8 * (reg & 3); 522 523 switch(bytes) 524 { 525 case 1: 526 mask = 0xff; 527 data = (reg_data & ~ (mask << shift)) | (data << shift); 528 break; 529 case 2: 530 mask = 0xffff; 531 if(reg % 4 == 0) 532 data = (reg_data & ~mask) | data; 533 else 534 data = (reg_data & ~ (mask << shift)) | 535 (data << shift); 536 break; 537 case 4: 538 break; 539 default: 540 panic("gt_pci_readconfig: wrong bytes count"); 541 break; 542 } 543 } 544 545 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr)) 546 return; 547 548 /* The galileo has problems accessing device 31. */ 549 if (bus == 0 && slot == 31) 550 return; 551 552 /* XXX: no support for bus > 0 yet */ 553 if (bus > 0) 554 return; 555 556 /* Clear cause register bits. */ 557 GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0); 558 559 GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr); 560 561 /* 562 * Galileo system controller is special 563 */ 564 if ((bus == 0) && (slot == 0)) 565 GT_REGVAL(GT_PCI0_CFG_DATA) = GT_PCI_DATA(data); 566 else 567 GT_REGVAL(GT_PCI0_CFG_DATA) = data; 568 569 #if 0 570 printf("PCICONF_WRITE(%02x:%02x.%02x[%04x] -> %02x(%d)\n", 571 bus, slot, func, reg, data, bytes); 572 #endif 573 574 } 575 576 static int 577 gt_pci_route_interrupt(device_t pcib, device_t dev, int pin) 578 { 579 int bus; 580 int device; 581 int func; 582 /* struct gt_pci_softc *sc = device_get_softc(pcib); */ 583 bus = pci_get_bus(dev); 584 device = pci_get_slot(dev); 585 func = pci_get_function(dev); 586 /* 587 * XXXMIPS: We need routing logic. This is just a stub . 588 */ 589 switch (device) { 590 case 9: /* 591 * PIIX4 IDE adapter. HW IRQ0 592 */ 593 return 0; 594 case 11: /* Ethernet */ 595 return 10; 596 default: 597 device_printf(pcib, "no IRQ mapping for %d/%d/%d/%d\n", bus, device, func, pin); 598 599 } 600 return (0); 601 602 } 603 604 static int 605 gt_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 606 { 607 struct gt_pci_softc *sc = device_get_softc(dev); 608 switch (which) { 609 case PCIB_IVAR_DOMAIN: 610 *result = 0; 611 return (0); 612 case PCIB_IVAR_BUS: 613 *result = sc->sc_busno; 614 return (0); 615 616 } 617 return (ENOENT); 618 } 619 620 static int 621 gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result) 622 { 623 struct gt_pci_softc * sc = device_get_softc(dev); 624 625 switch (which) { 626 case PCIB_IVAR_BUS: 627 sc->sc_busno = result; 628 return (0); 629 } 630 return (ENOENT); 631 } 632 633 static struct resource * 634 gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid, 635 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags) 636 { 637 struct gt_pci_softc *sc = device_get_softc(bus); 638 struct resource *rv = NULL; 639 struct rman *rm; 640 bus_space_handle_t bh = 0; 641 642 switch (type) { 643 case SYS_RES_IRQ: 644 rm = &sc->sc_irq_rman; 645 break; 646 case SYS_RES_MEMORY: 647 rm = &sc->sc_mem_rman; 648 bh = sc->sc_mem; 649 break; 650 case SYS_RES_IOPORT: 651 rm = &sc->sc_io_rman; 652 bh = sc->sc_io; 653 break; 654 default: 655 return (NULL); 656 } 657 658 rv = rman_reserve_resource(rm, start, end, count, flags, child); 659 if (rv == NULL) 660 return (NULL); 661 rman_set_rid(rv, *rid); 662 if (type != SYS_RES_IRQ) { 663 bh += (rman_get_start(rv)); 664 665 rman_set_bustag(rv, gt_pci_bus_space); 666 rman_set_bushandle(rv, bh); 667 if (flags & RF_ACTIVE) { 668 if (bus_activate_resource(child, type, *rid, rv)) { 669 rman_release_resource(rv); 670 return (NULL); 671 } 672 } 673 } 674 return (rv); 675 } 676 677 static int 678 gt_pci_activate_resource(device_t bus, device_t child, int type, int rid, 679 struct resource *r) 680 { 681 bus_space_handle_t p; 682 int error; 683 684 if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) { 685 error = bus_space_map(rman_get_bustag(r), 686 rman_get_bushandle(r), rman_get_size(r), 0, &p); 687 if (error) 688 return (error); 689 rman_set_bushandle(r, p); 690 } 691 return (rman_activate_resource(r)); 692 } 693 694 static int 695 gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires, 696 int flags, driver_filter_t *filt, driver_intr_t *handler, 697 void *arg, void **cookiep) 698 { 699 struct gt_pci_softc *sc = device_get_softc(dev); 700 struct intr_event *event; 701 int irq, error; 702 703 irq = rman_get_start(ires); 704 if (irq >= ICU_LEN || irq == 2) 705 panic("%s: bad irq or type", __func__); 706 707 event = sc->sc_eventstab[irq]; 708 sc->sc_intr_cookies[irq].irq = irq; 709 sc->sc_intr_cookies[irq].sc = sc; 710 if (event == NULL) { 711 error = intr_event_create(&event, 712 (void *)&sc->sc_intr_cookies[irq], 0, irq, 713 gt_pci_mask_irq, gt_pci_unmask_irq, 714 NULL, NULL, "gt_pci intr%d:", irq); 715 if (error) 716 return 0; 717 sc->sc_eventstab[irq] = event; 718 } 719 720 intr_event_add_handler(event, device_get_nameunit(child), filt, 721 handler, arg, intr_priority(flags), flags, cookiep); 722 723 gt_pci_unmask_irq((void *)&sc->sc_intr_cookies[irq]); 724 return 0; 725 } 726 727 static int 728 gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res, 729 void *cookie) 730 { 731 struct gt_pci_softc *sc = device_get_softc(dev); 732 int irq; 733 734 irq = rman_get_start(res); 735 gt_pci_mask_irq((void *)&sc->sc_intr_cookies[irq]); 736 737 return (intr_event_remove_handler(cookie)); 738 } 739 740 static device_method_t gt_pci_methods[] = { 741 /* Device interface */ 742 DEVMETHOD(device_probe, gt_pci_probe), 743 DEVMETHOD(device_attach, gt_pci_attach), 744 DEVMETHOD(device_shutdown, bus_generic_shutdown), 745 DEVMETHOD(device_suspend, bus_generic_suspend), 746 DEVMETHOD(device_resume, bus_generic_resume), 747 748 /* Bus interface */ 749 DEVMETHOD(bus_read_ivar, gt_read_ivar), 750 DEVMETHOD(bus_write_ivar, gt_write_ivar), 751 DEVMETHOD(bus_alloc_resource, gt_pci_alloc_resource), 752 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 753 DEVMETHOD(bus_activate_resource, gt_pci_activate_resource), 754 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 755 DEVMETHOD(bus_setup_intr, gt_pci_setup_intr), 756 DEVMETHOD(bus_teardown_intr, gt_pci_teardown_intr), 757 758 /* pcib interface */ 759 DEVMETHOD(pcib_maxslots, gt_pci_maxslots), 760 DEVMETHOD(pcib_read_config, gt_pci_read_config), 761 DEVMETHOD(pcib_write_config, gt_pci_write_config), 762 DEVMETHOD(pcib_route_interrupt, gt_pci_route_interrupt), 763 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow), 764 765 DEVMETHOD_END 766 }; 767 768 static driver_t gt_pci_driver = { 769 "pcib", 770 gt_pci_methods, 771 sizeof(struct gt_pci_softc), 772 }; 773 774 static devclass_t gt_pci_devclass; 775 776 DRIVER_MODULE(gt_pci, gt, gt_pci_driver, gt_pci_devclass, 0, 0);
Cache object: d6a99de18022ad439bee4a4cc9f65738
[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]