The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/mips/malta/gt_pci_bus_space.c

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    1 /*      $NetBSD: bus.h,v 1.12 1997/10/01 08:25:15 fvdl Exp $    */
    2 /*-
    3  * $Id: bus.h,v 1.6 2007/08/09 11:23:32 katta Exp $
    4  *
    5  * SPDX-License-Identifier: BSD-4-Clause
    6  *
    7  * Copyright (c) 1996, 1997 The NetBSD Foundation, Inc.
    8  * All rights reserved.
    9  *
   10  * This code is derived from software contributed to The NetBSD Foundation
   11  * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
   12  * NASA Ames Research Center.
   13  *
   14  * Redistribution and use in source and binary forms, with or without
   15  * modification, are permitted provided that the following conditions
   16  * are met:
   17  * 1. Redistributions of source code must retain the above copyright
   18  *    notice, this list of conditions and the following disclaimer.
   19  * 2. Redistributions in binary form must reproduce the above copyright
   20  *    notice, this list of conditions and the following disclaimer in the
   21  *    documentation and/or other materials provided with the distribution.
   22  * 3. All advertising materials mentioning features or use of this software
   23  *    must display the following acknowledgement:
   24  *      This product includes software developed by the NetBSD
   25  *      Foundation, Inc. and its contributors.
   26  * 4. Neither the name of The NetBSD Foundation nor the names of its
   27  *    contributors may be used to endorse or promote products derived
   28  *    from this software without specific prior written permission.
   29  *
   30  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
   31  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
   32  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
   33  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
   34  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
   35  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
   36  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
   37  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
   38  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
   39  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
   40  * POSSIBILITY OF SUCH DAMAGE.
   41  */
   42 
   43 /*
   44  * Copyright (c) 1996 Charles M. Hannum.  All rights reserved.
   45  * Copyright (c) 1996 Christopher G. Demetriou.  All rights reserved.
   46  *
   47  * Redistribution and use in source and binary forms, with or without
   48  * modification, are permitted provided that the following conditions
   49  * are met:
   50  * 1. Redistributions of source code must retain the above copyright
   51  *    notice, this list of conditions and the following disclaimer.
   52  * 2. Redistributions in binary form must reproduce the above copyright
   53  *    notice, this list of conditions and the following disclaimer in the
   54  *    documentation and/or other materials provided with the distribution.
   55  * 3. All advertising materials mentioning features or use of this software
   56  *    must display the following acknowledgement:
   57  *      This product includes software developed by Christopher G. Demetriou
   58  *      for the NetBSD Project.
   59  * 4. The name of the author may not be used to endorse or promote products
   60  *    derived from this software without specific prior written permission
   61  *
   62  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   63  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   64  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   65  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   66  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   67  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   68  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   69  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   70  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   71  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   72  *
   73  *      from: src/sys/alpha/include/bus.h,v 1.5 1999/08/28 00:38:40 peter
   74  * $FreeBSD$
   75  */
   76 #include <sys/cdefs.h>
   77 __FBSDID("$FreeBSD$");
   78 
   79 #include <sys/param.h>
   80 #include <sys/systm.h>
   81 #include <sys/bus.h>
   82 #include <sys/endian.h>
   83 #include <sys/kernel.h>
   84 #include <sys/malloc.h>
   85 #include <sys/ktr.h>
   86 
   87 #include <vm/vm.h>
   88 #include <vm/pmap.h>
   89 #include <vm/vm_kern.h>
   90 #include <vm/vm_extern.h>
   91 
   92 #include <machine/bus.h>
   93 #include <machine/cache.h>
   94 #include <mips/malta/gt_pci_bus_space.h>
   95 
   96 static bs_r_2_proto(gt_pci);
   97 static bs_r_4_proto(gt_pci);
   98 static bs_w_2_proto(gt_pci);
   99 static bs_w_4_proto(gt_pci);
  100 static bs_rm_2_proto(gt_pci);
  101 static bs_rm_4_proto(gt_pci);
  102 static bs_wm_2_proto(gt_pci);
  103 static bs_wm_4_proto(gt_pci);
  104 static bs_rr_2_proto(gt_pci);
  105 static bs_rr_4_proto(gt_pci);
  106 static bs_wr_2_proto(gt_pci);
  107 static bs_wr_4_proto(gt_pci);
  108 static bs_sm_2_proto(gt_pci);
  109 static bs_sm_4_proto(gt_pci);
  110 static bs_sr_2_proto(gt_pci);
  111 static bs_sr_4_proto(gt_pci);
  112 
  113 static struct bus_space gt_pci_space = {
  114         /* cookie */
  115         .bs_cookie =    (void *) 0,
  116 
  117         /* mapping/unmapping */
  118         .bs_map =       generic_bs_map,
  119         .bs_unmap =     generic_bs_unmap,
  120         .bs_subregion = generic_bs_subregion,
  121 
  122         /* allocation/deallocation */
  123         .bs_alloc =     generic_bs_alloc,
  124         .bs_free =      generic_bs_free,
  125 
  126         /* barrier */
  127         .bs_barrier =   generic_bs_barrier,
  128 
  129         /* read (single) */
  130         .bs_r_1 =       generic_bs_r_1,
  131         .bs_r_2 =       gt_pci_bs_r_2,
  132         .bs_r_4 =       gt_pci_bs_r_4,
  133         .bs_r_8 =       NULL,
  134 
  135         /* read multiple */
  136         .bs_rm_1 =      generic_bs_rm_1,
  137         .bs_rm_2 =      gt_pci_bs_rm_2,
  138         .bs_rm_4 =      gt_pci_bs_rm_4,
  139         .bs_rm_8 =      NULL,
  140 
  141         /* read region */
  142         .bs_rr_1 =      generic_bs_rr_1,
  143         .bs_rr_2 =      gt_pci_bs_rr_2,
  144         .bs_rr_4 =      gt_pci_bs_rr_4,
  145         .bs_rr_8 =      NULL,
  146 
  147         /* write (single) */
  148         .bs_w_1 =       generic_bs_w_1,
  149         .bs_w_2 =       gt_pci_bs_w_2,
  150         .bs_w_4 =       gt_pci_bs_w_4,
  151         .bs_w_8 =       NULL,
  152 
  153         /* write multiple */
  154         .bs_wm_1 =      generic_bs_wm_1,
  155         .bs_wm_2 =      gt_pci_bs_wm_2,
  156         .bs_wm_4 =      gt_pci_bs_wm_4,
  157         .bs_wm_8 =      NULL,
  158 
  159         /* write region */
  160         .bs_wr_1 =      generic_bs_wr_1,
  161         .bs_wr_2 =      gt_pci_bs_wr_2,
  162         .bs_wr_4 =      gt_pci_bs_wr_4,
  163         .bs_wr_8 =      NULL,
  164 
  165         /* set multiple */
  166         .bs_sm_1 =      generic_bs_sm_1,
  167         .bs_sm_2 =      gt_pci_bs_sm_2,
  168         .bs_sm_4 =      gt_pci_bs_sm_4,
  169         .bs_sm_8 =      NULL,
  170 
  171         /* set region */
  172         .bs_sr_1 =      generic_bs_sr_1,
  173         .bs_sr_2 =      gt_pci_bs_sr_2,
  174         .bs_sr_4 =      gt_pci_bs_sr_4,
  175         .bs_sr_8 =      NULL,
  176 
  177         /* copy */
  178         .bs_c_1 =       generic_bs_c_1,
  179         .bs_c_2 =       generic_bs_c_2,
  180         .bs_c_4 =       generic_bs_c_4,
  181         .bs_c_8 =       NULL,
  182 
  183         /* read (single) stream */
  184         .bs_r_1_s =     generic_bs_r_1,
  185         .bs_r_2_s =     generic_bs_r_2,
  186         .bs_r_4_s =     generic_bs_r_4,
  187         .bs_r_8_s =     NULL,
  188 
  189         /* read multiple stream */
  190         .bs_rm_1_s =    generic_bs_rm_1,
  191         .bs_rm_2_s =    generic_bs_rm_2,
  192         .bs_rm_4_s =    generic_bs_rm_4,
  193         .bs_rm_8_s =    NULL,
  194 
  195         /* read region stream */
  196         .bs_rr_1_s =    generic_bs_rr_1,
  197         .bs_rr_2_s =    generic_bs_rr_2,
  198         .bs_rr_4_s =    generic_bs_rr_4,
  199         .bs_rr_8_s =    NULL,
  200 
  201         /* write (single) stream */
  202         .bs_w_1_s =     generic_bs_w_1,
  203         .bs_w_2_s =     generic_bs_w_2,
  204         .bs_w_4_s =     generic_bs_w_4,
  205         .bs_w_8_s =     NULL,
  206 
  207         /* write multiple stream */
  208         .bs_wm_1_s =    generic_bs_wm_1,
  209         .bs_wm_2_s =    generic_bs_wm_2,
  210         .bs_wm_4_s =    generic_bs_wm_4,
  211         .bs_wm_8_s =    NULL,
  212 
  213         /* write region stream */
  214         .bs_wr_1_s =    generic_bs_wr_1,
  215         .bs_wr_2_s =    generic_bs_wr_2,
  216         .bs_wr_4_s =    generic_bs_wr_4,
  217         .bs_wr_8_s =    NULL,
  218 };
  219 
  220 #define rd16(a) le16toh(readw(a))
  221 #define rd32(a) le32toh(readl(a))
  222 #define wr16(a, v) writew(a, htole16(v))
  223 #define wr32(a, v) writel(a, htole32(v))
  224 
  225 /* generic bus_space tag */
  226 bus_space_tag_t gt_pci_bus_space = &gt_pci_space;
  227 
  228 uint16_t
  229 gt_pci_bs_r_2(void *t, bus_space_handle_t handle,
  230     bus_size_t offset)
  231 {
  232 
  233         return (rd16(handle + offset));
  234 }
  235 
  236 uint32_t
  237 gt_pci_bs_r_4(void *t, bus_space_handle_t handle,
  238     bus_size_t offset)
  239 {
  240 
  241         return (rd32(handle + offset));
  242 }
  243 
  244 void
  245 gt_pci_bs_rm_2(void *t, bus_space_handle_t bsh,
  246     bus_size_t offset, uint16_t *addr, size_t count)
  247 {
  248         bus_addr_t baddr = bsh + offset;
  249 
  250         while (count--)
  251                 *addr++ = rd16(baddr);
  252 }
  253 
  254 void
  255 gt_pci_bs_rm_4(void *t, bus_space_handle_t bsh,
  256     bus_size_t offset, uint32_t *addr, size_t count)
  257 {
  258         bus_addr_t baddr = bsh + offset;
  259 
  260         while (count--)
  261                 *addr++ = rd32(baddr);
  262 }
  263 
  264 /*
  265  * Read `count' 2 or 4 byte quantities from bus space
  266  * described by tag/handle and starting at `offset' and copy into
  267  * buffer provided.
  268  */
  269 void
  270 gt_pci_bs_rr_2(void *t, bus_space_handle_t bsh,
  271     bus_size_t offset, uint16_t *addr, size_t count)
  272 {
  273         bus_addr_t baddr = bsh + offset;
  274 
  275         while (count--) {
  276                 *addr++ = rd16(baddr);
  277                 baddr += 2;
  278         }
  279 }
  280 
  281 void
  282 gt_pci_bs_rr_4(void *t, bus_space_handle_t bsh,
  283     bus_size_t offset, uint32_t *addr, size_t count)
  284 {
  285         bus_addr_t baddr = bsh + offset;
  286 
  287         while (count--) {
  288                 *addr++ = rd32(baddr);
  289                 baddr += 4;
  290         }
  291 }
  292 
  293 /*
  294  * Write the 2 or 4 byte value `value' to bus space
  295  * described by tag/handle/offset.
  296  */
  297 void
  298 gt_pci_bs_w_2(void *t, bus_space_handle_t bsh,
  299     bus_size_t offset, uint16_t value)
  300 {
  301 
  302         wr16(bsh + offset, value);
  303 }
  304 
  305 void
  306 gt_pci_bs_w_4(void *t, bus_space_handle_t bsh,
  307     bus_size_t offset, uint32_t value)
  308 {
  309 
  310         wr32(bsh + offset, value);
  311 }
  312 
  313 /*
  314  * Write `count' 2 or 4 byte quantities from the buffer
  315  * provided to bus space described by tag/handle/offset.
  316  */
  317 void
  318 gt_pci_bs_wm_2(void *t, bus_space_handle_t bsh,
  319     bus_size_t offset, const uint16_t *addr, size_t count)
  320 {
  321         bus_addr_t baddr = bsh + offset;
  322 
  323         while (count--)
  324                 wr16(baddr, *addr++);
  325 }
  326 
  327 void
  328 gt_pci_bs_wm_4(void *t, bus_space_handle_t bsh,
  329     bus_size_t offset, const uint32_t *addr, size_t count)
  330 {
  331         bus_addr_t baddr = bsh + offset;
  332 
  333         while (count--)
  334                 wr32(baddr, *addr++);
  335 }
  336 
  337 /*
  338  * Write `count' 2 or 4 byte quantities from the buffer provided
  339  * to bus space described by tag/handle starting at `offset'.
  340  */
  341 void
  342 gt_pci_bs_wr_2(void *t, bus_space_handle_t bsh,
  343     bus_size_t offset, const uint16_t *addr, size_t count)
  344 {
  345         bus_addr_t baddr = bsh + offset;
  346 
  347         while (count--) {
  348                 wr16(baddr, *addr++);
  349                 baddr += 2;
  350         }
  351 }
  352 
  353 void
  354 gt_pci_bs_wr_4(void *t, bus_space_handle_t bsh,
  355     bus_size_t offset, const uint32_t *addr, size_t count)
  356 {
  357         bus_addr_t baddr = bsh + offset;
  358 
  359         while (count--) {
  360                 wr32(baddr, *addr++);
  361                 baddr += 4;
  362         }
  363 }
  364 
  365 /*
  366  * Write the 2 or 4 byte value `val' to bus space described
  367  * by tag/handle/offset `count' times.
  368  */
  369 void
  370 gt_pci_bs_sm_2(void *t, bus_space_handle_t bsh,
  371     bus_size_t offset, uint16_t value, size_t count)
  372 {
  373         bus_addr_t addr = bsh + offset;
  374 
  375         while (count--)
  376                 wr16(addr, value);
  377 }
  378 
  379 void
  380 gt_pci_bs_sm_4(void *t, bus_space_handle_t bsh,
  381     bus_size_t offset, uint32_t value, size_t count)
  382 {
  383         bus_addr_t addr = bsh + offset;
  384 
  385         while (count--)
  386                 wr32(addr, value);
  387 }
  388 
  389 /*
  390  * Write `count' 2 or 4 byte value `val' to bus space described
  391  * by tag/handle starting at `offset'.
  392  */
  393 void
  394 gt_pci_bs_sr_2(void *t, bus_space_handle_t bsh,
  395                        bus_size_t offset, uint16_t value, size_t count)
  396 {
  397         bus_addr_t addr = bsh + offset;
  398 
  399         for (; count != 0; count--, addr += 2)
  400                 wr16(addr, value);
  401 }
  402 
  403 void
  404 gt_pci_bs_sr_4(void *t, bus_space_handle_t bsh,
  405     bus_size_t offset, uint32_t value, size_t count)
  406 {
  407         bus_addr_t addr = bsh + offset;
  408 
  409         for (; count != 0; count--, addr += 4)
  410                 wr32(addr, value);
  411 }

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